Idle Cycles Research Articles

Distributed and Asynchronous Population-Based Optimization Applied to the Optimal Design of Fuzzy Controllers

Designing a controller is typically an iterative process during which engineers must assess the performance of a design through time-consuming simulations; this becomes even more burdensome when using a population-based metaheuristic that evaluates every member of the population. Distributed algorithms can mitigate this issue, but these come with their own challenges. This is why, in this work, we propose a distributed and asynchronous bio-inspired algorithm to execute the simulations in parallel, using a multi-population multi-algorithmic approach. Following a cloud-native pattern, isolated populations interact asynchronously using a distributed message queue, which avoids idle cycles when waiting for other nodes to synchronize. The proposed algorithm can mix different metaheuristics, one for each population, first because it is possible and second because it can help keep total diversity high. To validate the speedup benefit of our proposal, we optimize the membership functions of a fuzzy controller for the trajectory tracking of a mobile autonomous robot using distributed versions of genetic algorithms, particle swarm optimization, and a mixed-metaheuristic configuration. We compare sequential versus distributed implementations and demonstrate the benefits of mixing the populations with distinct metaheuristics. We also propose a simple migration strategy that delivers satisfactory results. Moreover, we compare homogeneous and heterogenous configurations for the populations’ parameters. The results show that even when we use random heterogeneous parameter configuration in the distributed populations, we obtain an error similar to that in other work while significantly reducing the execution time.

Efficient Hint-Based Event (EHE) Issue Scheduling for Hardware Multithreaded RISC-V Pipeline

Hardware multithreading is a common approach for tolerating memory latency by utilizing idle cycles and avoiding CPU stalling. Nowadays, multithreading architectures are commonly used across many processors and various embedded edge devices to improve performance. This work suggests a new multithreading in-order pipeline microarchitecture design for RISC-V and proposes an efficient event-based issue scheduling algorithm. The proposed scheduling algorithm is based on the unique RISC-V ISA that enables decoding of the instruction type in an early stage of the pipeline. The RISC-V-based multithreading architecture is evaluated using a dedicated software simulator. Simulation results show that the proposed algorithm outperforms the classical Round Robin and the coarse grain algorithms. The proposed architecture is evaluated using the standard MiBench benchmark and other common applications, demonstrating pipeline utilization improvement of up to about 26% in terms of IPC using four threads.

Metallurgy and Mechanism of Underwater Wet Cutting Using Oxidizing and Exothermic Flux-Cored Wires.

This paper considers the metallurgical processes of dissociation, ionization, oxidation, deoxidation, and dissolution of oxides during underwater wet cutting. A multiphase mechanism of underwater wet cutting consisting of working and idle cycles of the electrical process in a pulsating vapor gas bubble is proposed. A model of arc penetration into metal due to metal oxidation and stabilization of the arc by the inner walls of a narrow kerf is proposed. For underwater cutting of 10 KhSND, 304L steel, CuAl5, and AlMg4.5Mn0.7 alloy, we provide a principle of modeling the phase composition of the gas mixture based on high oxygen concentration, improving ionization, enthalpy, heat capacity, and thermal conductivity of plasma through the use of a mixture of KNO3, FeCO3 and aluminum. The method of improving the thermophysical properties and ionization of plasma due to the exothermic effect when introducing Fe3O4, MoO2, WO2 oxides and Al, Mg, Ti deoxidizers is proposed. Although a negative effect of refractory slag was revealed, it could be removed by using the method of reducing surface tension through the ionic dissolution of refractory oxides in Na3AlF6 cryolite. In underwater cutting of 10 KhSND and 304L, the steel welding current was 344–402 A with a voltage of 36–39 V; in cutting of CuAl5 and AlMg4.5Mn0.7 alloy, the welding current was 360–406; 240 A, with a voltage of 35–37; 38 V, respectively, with the optimal composition of flux-cored wire: 50–60% FeCO3 and KNO3, 20–30% aluminum, 20% Na3AlF6. Application of flux-cored wires of the KNO3-FeCO3-Na3AlF6-Al system allowed stable cutting of 10KhSND, AISI 304L steels, and CuAl5 bronze with kerf width up to 2.5–4.7 mm.

Comparative Study of Heterogeneous Multicore Scheduling Algorithms on Media Codecs

All modern-day computers and smartphones come with multi-core CPUs. The multicore architecture is generally heterogeneous in nature to maximize computational throughput. These multicore systems exploit thread-level parallelism to deliver higher performance, but they are limited by the requirement of good scheduling algorithms that maximize CPU utility and minimize wasted and idle cycles. With the rise in streaming services and multimedia capabilities of smartphones, it is necessary to have efficient heterogeneous cores which are capable of performing multimedia processing at a fast pace. It is also needed that they utilize efficient scheduling algorithms to achieve this task. This paper compares some heterogeneous multi-core scheduling algorithms available and determines which is the most optimal scheduling algorithm given various codecs.

Accuracy-Adaptive Spintronic Adder for Image Processing Applications

Approximate computing (AC) is a recently emerged computing paradigm that can trade in accuracy for power, area, and delay in accuracy-insensitive applications, such as image processing. Magnetic tunnel junction (MTJ) cells can further these AC advancements as a result of their near-zero current leakage. In addition, due to the non-volatility of MTJs, an MTJ-based circuit can switch into a completely OFF state during idle cycles for further power savings without loss of data or the need for extra components. In this article, two novel MTJ-based approximate full-adder circuits are proposed and evaluated. The proposed 1 bit adder circuits are then extended to an 8 bit accuracy-adaptive adder that dynamically adjusts the level of accuracy as needed. For evaluations, we have employed the proposed accuracy-adaptive adder in the implementation of a Gaussian image processing filter. We have observed that, at the expense of a tolerable loss of accuracy, the proposed accuracy-adaptive adder offers up to 47% and 94% improvements in power and performance, respectively, when compared to its conventional accurate counterparts.

Mathematical Analysis of the Influence of the Flux-Cored Wire Chemical Composition on the Electrical Parameters and Quality in the Underwater Wet Cutting

Abstract The paper presents research in the field of underwater wet cutting with the use of flux-cored wires in order to improve the quality and performance. The research has resulted into the development of gas and slag systems for flux-cored wires and determination of, optimal parameters for cutting stability and quality. The underwater wet cutting mechanism is a cyclical process with the formation of periodic keyholes in metal, and it consists of operating and idle cycles. Efficiency of the cutting process can be determined by analyzing cycle times, welding current, voltage, power and a number of short circuits. To assess the stability and efficiency of the underwater wet cutting process, the authors have developed the method for analyzing oscillograms to calculate the probability density of current, voltage and power. To determine the quality of cutting, the authors have provided a criterion based on the ratio of the voltage probability density in the idle and operating cycles.

Methods of the analytical study of vibratory drum forced vibrations during the soil compaction

The fundamental principles of the vibration theory as a classical science are widely used for the description of movements of technical objects and mechanical systems. Vibrations of real objects are complicated by non-linear characteristics of stiffness of the medium to be compacted and viscous friction forces. Usable vertical movements of a vibratory drum have been determined whereby the technological compaction operation of materials and soils is performed. The methods of the vibratory drum vertical movement determination have been developed by means of considering the vibratory drum downward movement during the semi-period of one rotation of the eccentric weight. The operating process of the road roller vibratory drum is composed of sequential periodic transient operating processes of the material compaction and idle cycles in each turn of the eccentric weight rotation. Within the process of the study the operating process is considered of the vibratory drum downward movement during the material compaction, consisting of free damped and undamped forced downward movements of the vibratory drum. For the first time the damping time of transient processes during the analysis of forced oscillatory processes is regulated by the semi-period time of the eccentric weight rotation t = 0.5T.

Fast Hardware-Based IME With an Idle Cycle and Computational Redundancy Reduction

Extensive efforts have been made to design hardware-based integer motion estimation (IME) that is much faster than software-based IME but suffers from the degradation in the coding efficiency. This is because the strategy for previous efforts was a simple algorithmic modification of the fast IME to facilitate the given hardware design at the expense of coding efficiency. This paper proposes a novel hardware design of the IME that not only offers real-time processing capability but also provides a flexible tradeoff between computational complexity and coding efficiency. First, a prediction unit (PU) loop unrolling scheme is proposed to solve the pipeline stall problem owing to the nature of fast IME algorithms such as the test zone search (TZS). It reduces idle cycles by 89.24%. Next, to further reduce the computational complexity of the TZS algorithm, a computational redundancy among PUs within a coding unit is reduced through a search step synchronization and search point sharing scheme. Thus, the computational complexity is reduced by 72.25%. The proposed schemes eliminate the inefficiency of hardware design; thus, they do not suffer from serious degradation in the coding efficiency. Consequently, the proposed hardware-based IME processes $7680\times4320$ videos at 30 frames per second while increasing the Bjontegaard delta bitrate by only 0.90% on average. The hardware design is synthesized using a 65 nm general purpose CMOS technology, and its gate count is 268.5K at an operating clock frequency of 500 MHz.

Task Packing: Efficient task scheduling in unbalanced parallel programs to maximize CPU utilization

Load imbalance in parallel systems can be generated by external factors to the currently running applications like operating system noise or the underlying hardware like a heterogeneous cluster. HPC applications working on irregular data structures can also have difficulties to balance their computations across the parallel tasks. In this article we extend, improve and evaluate more deeply the Task Packing mechanism proposed in a previous work. The main idea of the mechanism is to concentrate the idle cycles of unbalanced applications in such a way that one or more CPUs are freed from execution. To achieve this, CPUs are stressed with just useful work of the parallel application tasks, provided performance is not degraded. The packing is solved by an algorithm based on the Knapsack problem, in a minimum number of CPUs and using oversubscription. We design and implement a more efficient version of such mechanism. To that end, we perform the Task Packing “in place”, taking advantage of idle cycles generated at synchronization points of unbalanced applications. Evaluations are carried out on a heterogeneous platform using FT and miniFE benchmarks. Results showed that our proposal generates low overhead. In addition the amount of freed CPUs are related to a load imbalance metric which can be used as a prediction for it.

A Message-Passing Microcoded Synchronization for Distributed Shared Memory Architectures

Implementation of concurrent data structures in architectures that provide limited synchronization primitives is a critical challenge. Typical lock-based implementations suffer from well-known problems such as poor scalability and unfairness. In this paper, we propose a client-server based synchronization model that can be applied in data structures with low level of parallelism for distributed shared memory many-core systems that support also message-passing communication. Additionally, we utilize a programmable hardware accelerator with appropriate application interfaces to overcome the performance-flexibility dilemma. Experimental results show that the proposed work performs 20 $\times$ faster than the single lock model with 88 $\times$ less idle cycles and 7 $\times$ less power consumption.

Real-time data analysis for medical diagnosis using FPGA-accelerated neural networks

BackgroundReal-time analysis of patient data during medical procedures can provide vital diagnostic feedback that significantly improves chances of success. With sensors becoming increasingly fast, frameworks such as Deep Neural Networks are required to perform calculations within the strict timing constraints for real-time operation. However, traditional computing platforms responsible for running these algorithms incur a large overhead due to communication protocols, memory accesses, and static (often generic) architectures. In this work, we implement a low-latency Multi-Layer Perceptron (MLP) processor using Field Programmable Gate Arrays (FPGAs). Unlike CPUs and Graphics Processing Units (GPUs), our FPGA-based design can directly interface sensors, storage devices, display devices and even actuators, thus reducing the delays of data movement between ports and compute pipelines. Moreover, the compute pipelines themselves are tailored specifically to the application, improving resource utilization and reducing idle cycles. We demonstrate the effectiveness of our approach using mass-spectrometry data sets for real-time cancer detection.ResultsWe demonstrate that correct parameter sizing, based on the application, can reduce latency by 20% on average. Furthermore, we show that in an application with tightly coupled data-path and latency constraints, having a large amount of computing resources can actually reduce performance. Using mass-spectrometry benchmarks, we show that our proposed FPGA design outperforms both CPU and GPU implementations, with an average speedup of 144x and 21x, respectively.ConclusionIn our work, we demonstrate the importance of application-specific optimizations in order to minimize latency and maximize resource utilization for MLP inference. By directly interfacing and processing sensor data with ultra-low latency, FPGAs can perform real-time analysis during procedures and provide diagnostic feedback that can be critical to achieving higher percentages of successful patient outcomes.

A Novel and Efficient Reader-to-Reader and Tag-to-Tag Anti-Collision Protocol

ABSTRACT Radio Frequency IDentification (RFID) is one of the prominent wireless technologies for implementing a complete smart environment and is preferred over magnetic tapes, bar codes and smart cards due to its low cost and high speed. RFID networks provide identification, location tracking and record management and consist of tags, readers and backend storage devices. In these networks, it is very common to see tag-to-tag or reader-to-reader collisions. For avoiding these collisions and hence to improve the overall system performance many probabilistic and deterministic anti-collision protocols have been proposed, but the majority of these protocols were found to be inefficient in channel distribution. In this work, based on simulation annealing, a novel and efficient reader-to-reader and tag-to-tag anti-collision protocol is proposed by uniformly distributing the available channels among different readers, which reduces reader-to-reader collisions to zero. For a better performance tag state parameters have been preferred over fixed scheduling. Improvement of tag identification ratio from 1% to 12.5%, successful interrogation cycles by up to 25% for a maximum of 1000 readers and reduction in the number of cycles required for interrogation by a minimum of 13.3% and a maximum of 25.5% and reader-to-reader collisions up to 24% for 100 K tags make the proposed protocol much suited to a heavily loaded network. Compared to other contemporary protocols performance gain in the range of 2% to 30% has been observed for the total number of sent/received packets, delay, number of collisions, idle cycles and time cycles.

An efficient control flow validation method using redundant computing capacity of dual-processor architecture

Microprocessors in safety-critical system are extremely vulnerable to hacker attacks and circuit crosstalk, as they can modify binaries and lead programs to run along the wrong control flow paths. It is a significant challenge to design a run-time validation method with few hardware modification. In this paper, an efficient control flow validation method named DCM (Dual-Processor Control Flow Validation Method) is proposed basing on dual-processor architecture. Since a burst of memory-access-intensive instructions could block pipeline and cause lots of waiting clocks, the DCM assigns the idle pipeline cycles of the blocked processor to the other processor to validate control flow at run time. An extra lightweight monitor unit in each processor is needed and a special dual-processor communication protocol is also designed to schedule the redundant computing capacity between two processors to do validation tasks better. To further improve the efficiency, we also design a software-based self-validation algorithm to help reduce validation times. The combination of both hardware method and software method can speed up the validation procedure and protect the control flow paths with different emphasis. The cycle-accurate simulator GEM5 is used to simulate two ARMv7-A processors with out-of-order pipeline. Experiment shows the performance overhead of DCM is less than 22% on average across the SPEC 2006 benchmarks.

A Highly Efficient Predetection-Based Anticollision Mechanism for Radio-Frequency Identification

One of the research areas in radio-frequency identification (RFID) systems is the reduction of the identification processing time for a number of tags within an RFID reader recognition region. In the last decade, many research results regarding anticollision algorithms have been presented in the literature. Most of them are tree-based protocols. However, it is important for tree-based protocols to enhance stability and system throughput, since they may face long identification delays when the network density is high. In this study, we present a highly efficient predetection tree-based algorithm to achieve more efficient tag identification performance. Our proposed mechanism can effectively reduce both collisions and idle cycles by exploiting the predetection technique and adjustable slot size mechanism. The simulation results show that the proposed mechanism can effectively improve tag identification time performance by around 29.9% to 64.8% over previous techniques. Further, the number of query cycles, number of collisions, and total number of slots are reduced compared to previous predetection-based protocols. It is also observed that the proposed scheme can have good performance in large-scale RFID systems.

Downlink Resource Allocation Under Time-Varying Interference: Fairness and Throughput Optimality

We address the problem of downlink resource allocation in the presence of time-varying interference. We consider a scenario where users served by a base station face interference from a neighboring base station. We model the interference from the neighboring base station as an ON/OFF renewal process, that arises due to its idle and busy cycles. The users feedback their downlink signal to interference plus noise ratio (SINR) values to their base station, but these values are outdated. In this setting, we characterize how the resource allocation layer can optimally exploit the reported SINR values, which could be unreliable due to time-varying interference. In particular, we propose resource allocation policies in two well-known paradigms. First, we address the problem of $\alpha $ –fair scheduling, and propose a policy that ensures asymptotic convergence to the optimal $\alpha $ –fair throughput. Second, we propose a throughput optimal resource allocation policy, i.e., a policy that can stably support the largest possible set of traffic rates under the interference scenario considered. Estimating the outage probability from the outdated SINR values plays an important role in both scheduling paradigms, and we accomplish this using tool from renewal theory.

Refresh re-use based transparent test for detection of in-field permanent faults in DRAMs

In this paper, a transparent test technique for testing permanent faults developed during field operation of DRAMs has been proposed. A three pronged approach has been taken in this work. First, a word oriented transparent March test generation algorithm has been proposed that avoids signature based prediction phase; next the proposed transparent March test is structured in a way that facilitates its implementation during refresh cycles of the DRAM; finally the on-chip refresh circuit is modified to allow its re-use during implementation of the proposed transparent March test on DRAM. Re-use of refresh cycles for test purpose ensures periodic testing of DRAM without interruption. Thus, faults are not allowed to accumulate. Moreover, wait for idle cycles of the processor to perform the test are avoided and test finishes within a definite time. Re-using the refresh circuit for test purpose overcomes requirement of additional Design-For-Testability hardware and brings down the area overhead.Both analytic predictions and simulation results for the method proposed here indicate real estate benefits and test time savings in comparison to other reported techniques. The proposed refresh re-use based transparent test technique provides a cost effective solution by providing facility for periodic tests of DRAM without requiring additional test hardware.

Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors

The increasing number of cores on a chip has made the network on chip (NoC) concept the standard communication paradigm for chip multiprocessors. A fault in an NoC leads to undesirable ramifications that can severely impact the performance of a chip. Therefore, it is vital to design fault tolerant NoCs. In this paper, we present Shield , a reliable NoC router architecture that has the unique ability to tolerate both hard and soft errors in the routing pipeline using techniques such as spatial redundancy, exploitation of idle cycles, bypassing of faulty resources and selective hardening. Using Mean Time to Failure and Silicon Protection Factor metrics, we show that Shield is six times more reliable than the baseline-unprotected router and is at least 1.5 times more reliable than existing fault tolerant router architectures. We introduce a new metric called Soft Error Improvement Factor and show that the soft error tolerance of Shield has improved by three times in comparison to the baseline-unprotected router. This reliability improvement is accomplished by incurring an area and power overhead of 34 and 31 percent respectively. Latency analysis using SPLASH-2 and PARSEC reveals that in the presence of faults, latency increases by a modest 13 and 10 percent respectively.

WOM-Code Solutions for Low Latency and High Endurance in Phase Change Memory

This paper describes a write-once-memory-code phase change memory (WOM-code PCM) architecture for next-generation non-volatile memory applications. Specifically, we address the long latency of the write operation in PCM—attributed to PCM SET—by proposing a novel PCM memory architecture that integrates the $\langle 2^2\rangle ^2/3$ WOM-code at the memory organization and memory controller levels. To further improve the write latency of WOM-code PCM, we propose a PCM-refresh approach that uses idle cycles to preemptively set PCM rows to the initial WOM-code state. Finally, to balance write latency improvements against WOM-code PCM overhead, we propose a WOM-code cached PCM (WCPCM) architecture that uses WOM-code PCM as the cache alongside conventional PCM main memory. Since WOM-code techniques inherently impact PCM endurance by increasing the number of bit-writes in comparison to unencoded PCM, we incorporate additional transitions from the $\langle 2^2\rangle ^2/3$ WOM-code transition graph to realize endurance-WOM-code (e-WOM-code) architectures. Transitions between the e-WOM-code states on writes to memory are integrated into an incremental coding for endurance (ICE) approach that exploits redundancies in the conventional WOM-code to reduce the number of bit-writes over unencoded PCM. Simulation results show that the proposed e-WOM-code PCM architecture is able to reduce memory write (read) latency by 19.8 percent (14.7 percent) and the number of bit-writes over unencoded PCM without (with) data-comparison write (DCW), a read-modify-write process that only updates changed cells, by 83.0 percent (22.1 percent) on average across general-purpose (SPEC CPU2006), embedded (MiBench), and high-performance (SPLASH-2) benchmarks. Further, e-WOM-code PCM with PCM-refresh can reduce memory write (read) latency by 51.5 percent (44.1 percent) and the number of bit-writes over unencoded PCM without DCW by 76.5 percent on average across the benchmarks; there is, however, an increase of 19 percent in the number of bit-writes over unencoded PCM with DCW. Finally, for just 4.7 percent memory overhead, the e-WOM-code cached PCM (e-WCPCM) architecture reduces memory write (read) latency by 47.5 percent (41.6 percent) and the number of bit-writes over unencoded PCM without DCW by 68.1 percent on average across the benchmarks; again, there is a 49 percent increase in the number of bit-writes over unencoded PCM with DCW.

A Novel and Efficient Anti-Collision Protocol for RFID Tag Identification

Radio frequency identification (RFID) is prominent technology for fast object identification and tracking. In RFID systems, reader-to-reader or tag-to-tag collisions are common. Majority of probabilistic and deterministic anti-collisions methods are inefficient in channel distribution and improving the performance. In this work, simulation annealing based anti-collision protocol is proposed where there is uniform distribution of channels among readers. In addition, preference is given to tag state parameters over fixed scheduling in order to increase the performance. The tag state parameters named energy efficiency, distance from selected reader and distance from obstacles are considered. The simulation results show that the proposed approach is an effective mechanism where there is a minimum improvement of 16.7% for 100 readers and maximum of 32.7% for 1000 readers in tag identification ratio, and a minimum improvement of 23% for 1000 readers and maximum of 75.3% for 100 readers in total successful interrogation cycles. Further, total time cycles, total IDLE cycles, total number of collisions, delay, and total number of packets sent and received are reduced compared to state-of-art protocols. It is observed that the proposed simulation annealing based protocol is contiguous channels allocation algorithm with zero collision.

A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems

Network-on-Chip (NoC) paradigm is rapidly evolving into an efficient interconnection network to handle the strict communication requirements between the increasing number of cores on a single chip. Diminishing transistor size is making the NoC increasingly vulnerable to both hard faults and soft errors. This paper concentrates on soft errors in NoCs. A soft error in an NoC router results in significant consequences such as data corruption, packet retransmission and deadlock among others. To this end, we propose S oft Error T olerant N oC R outer (STNR) architecture, that is capable of detecting and recovering from soft errors occurring in different control stages of the routing pipeline. STNR exploits the use of idle cycles inherent in NoC packet routing pipeline to perform time redundant executions necessary for soft error tolerance. In doing so, STNR is able to detect and correct all single transient faults in the control stages of the pipeline. Simulation results using PARSEC and SPLASH-2 benchmarks show that STNR is able to accomplish such high level of soft error protection with a minimal impact on latency (an increase of 1.7 and 1.6 percent respectively). Additionally, STNR incurs an area overhead of 7 percent and power overhead of 13 percent as compared to the baseline unprotected router.