Ideal Memristor Research Articles

A flexible and fast digital twin for RRAM systems applied for training resilient neural networks

Resistive Random Access Memory (RRAM) has gained considerable momentum due to its non-volatility and energy efficiency. Material and device scientists have been proposing novel material stacks that can mimic the “ideal memristor” which can deliver performance, energy efficiency, reliability and accuracy. However, designing RRAM-based systems is challenging. Engineering a new material stack, designing a device, and experimenting takes significant time for material and device researchers. Furthermore, the acceptability of the device is ultimately decided at the system level. We see a gap here where there is a need for facilitating material and device researchers with a “push button” modeling framework that allows to evaluate the efficacy of the device at system level during early device design stages. Speed, accuracy, and adaptability are the fundamental requirements of this modelling framework. In this paper, we propose a digital twin (DT)-like modeling framework that automatically creates RRAM device models from device measurement data. Furthermore, the model incorporates the peripheral circuit to ensure accurate energy and performance evaluations. We demonstrate the DT generation and DT usage for multiple RRAM technologies and applications and illustrate the achieved performance of our GPU implementation. We conclude with the application of our modeling approach to measurement data from two distinct fabricated devices, validating its effectiveness in a neural network processing an Electrocardiogram (ECG) dataset and incorporating Fault Aware Training (FAT).

Memristors-coupled neuron models with multiple firing patterns and homogeneous and heterogeneous multistability

Abstract Memristors are extensively used to estimate the external electromagnetic stimulation and synapses for neurons. In this paper, two distinct scenarios, i.e., an ideal memristor serves as external electromagnetic stimulation and a locally active memristor serves as a synapse, are formulated to investigate the impact of a memristor on a two-dimensional Hindmarsh–Rose neuron model. Numerical simulations show that the neuronal models in different scenarios have multiple burst firing patterns. The introduction of the memristor makes the neuronal model exhibit complex dynamical behaviors. Finally, the simulation circuit and DSP hardware implementation results validate the physical mechanism, as well as the reliability of the biological neuron model.

Dynamics of memristive Liu system and its DSP implementation

In this paper, a novel four-dimensional memristive system is investigated to generate abundant dynamical behaviors. By combining the Liu chaotic system with an ideal memristor, an enhanced chaotic system is proposed. Dynamical analysis indicates that the new system sustains stable chaotic states and exhibits complex behaviors, with the help of the Lyapunov exponents, bifurcation diagrams, Poincaré section, parametric offset boosting, and SE complexity. The coexistence of attractors is investigated by the variation of parameters. The chaotic performance is enhanced in the proposed system, broadens the range of parameters for chaotical oscillations, and transforms periodic and quasiperiodic states into chaos. The practical applicability and feasibility of the system are validated via NIST testing and DSP implementation. The system exhibits resilient dynamical characteristics that make it highly suitable for deployment in various domains, including secure communication and signal detection.

Can We Still Find an Ideal Memristor?

In 1971, Chua defined an ideal memristor that links magnetic flux φ and electric charge q. In a magnetic lump with a current-carrying conductor, we found that the direct interaction between physical magnetic flux φ and physical electric charge q is memristive by nature in terms of a time-invariant φ-q curve being nonlinear, continuously differentiable and strictly monotonically increasing. Although we succeeded in demonstrating that the “ideal/real/perfect/… memristor” needs magnetism, the structure still suffers from two serious limitations: 1. a parasitic “inductor” effect and 2. bistability and dynamic sweep of a continuous resistance range. Then, we discussed how to overcome these two limitations to make a fully functioning ideal memristor with multiple or an infinite number of stable states and no parasitic inductance. We then gave a number of innovations to the current memristor structure, such as an “open” structure, nanoscale size, magnetic materials with cubic anisotropy (or even isotropy) and sequential switching of the magnetic domains. Contrary to the conjecture that “an ideal memristor may not exist or may be a purely mathematical concept”, we remain optimistic that an ideal memristor will be discovered in nature or will be made in the laboratory. Our finding of the memristive flux–charge interaction may advance the development and application of the memristor technology.

Are There an Infinite Number of Passive Circuit Elements in the World?

We found that a second-order ideal memristor [whose state is the charge, i.e., in ] degenerates into a negative nonlinear resistor with an internal power source. After extending analytically and geographically the above local activity (experimentally verified by the two active higher-integral-order memristors extracted from the famous Hodgkin–Huxley circuit) to other higher-order circuit elements, we concluded that all higher-order passive memory circuit elements do not exist in nature and that the periodic table of the two-terminal passive ideal circuit elements can be dramatically reduced to a reduced table comprising only six passive elements: a resistor, inductor, capacitor, memristor, mem-inductor, and mem-capacitor. Such a bounded table answered an open question asked by Chua 40 years ago: Are there an infinite number of passive circuit elements in the world?

New Class of Discrete-Time Memristor Circuits: First Integrals, Coexisting Attractors and Bifurcations Without Parameters

The use of ideal memristors in a continuous-time (CT) nonlinear circuit is known to greatly enrich the dynamic behavior with respect to the memristorless counterpart, which is a crucial property for applications in future analog electronic circuits. This can be explained via the flux–charge analysis method (FCAM), according to which CT circuits with ideal memristors have for structural reasons first integrals (or invariants of motion, or conserved quantities) and their state space can be foliated in infinitely many invariant manifolds where they can display different dynamics. The paper introduces a new discretization scheme for the memristor which, differently from those adopted in the literature, guarantees that the first integrals of the CT memristor circuits are preserved exactly in the discretization, and that this is true for any step size. This new scheme makes it possible to extend FCAM to discrete-time (DT) memristor circuits and rigorously show the existence of invariant manifolds and infinitely many coexisting attractors (extreme multistability). Moreover, the paper addresses standard bifurcations varying the discretization step size and also bifurcations without parameters, i.e. bifurcations due to varying the initial conditions for fixed step size and circuit parameters. The method is illustrated by analyzing the dynamics and flip bifurcations with and without parameters in a DT memristor–capacitor circuit and the Poincaré–Andronov–Hopf bifurcation in a DT Murali–Lakshmanan–Chua circuit with a memristor. Simulations are also provided to illustrate bifurcations in a higher-order DT memristor Chua’s circuit. The results in the paper show that DT memristor circuits obtained with the proposed discretization scheme are able to display even richer dynamics and bifurcations than their CT counterparts, due to the coexistence of infinitely many attractors and the possibility to use the discretization step as a parameter without destroying the foliation in invariant manifolds.

The memristor: Principle, mechanism, and application

The memristor is an electronic device and the only fundamental circuit element that can directly implement memory and logic computation between electronic devices. The main characteristic of the memristor is that its resistance value varies with the direction and magnitude of the current flowing through it, and this variation is reversible. It can store charge, similar to RAM in traditional computers, but with more energy-efficient, faster, and higher-density storage. Therefore, the memristor is attracting attention in the research of artificial intelligence and neural networks. This paper summarizes the mathematical principles and application scenarios of memristive systems, including ideal memristors. two theoretically mature resistance change mechanisms are summarized, namely the con-ductive filament model (mainly for RRAM, Resistive random-access Finally, the design of memristor-related circuit components and the current state of research in artificial intelli-gence, especially in the field of neural networks, are reviewed. The authors are optimistic about the future development of memristors for medium and low power edge computing platforms and believe that memristors will become one of the computing platforms for ar-tificial intelligence.

Kendiliğinden Kanal Oluşturmalı Karbon Tabanlı Memristörler İçin DC Dirençlerini Okuyarak Yapılan Bir Sağlamlık Testinin Güvenilirliğinin İncelenmesi

An ideal memristor that has been theoretically predicted almost a half-century ago is a nonlinear power dissipating circuit element. Nowadays, memristive systems such as thin films which are not ideal memristors are also called memristors. Such systems have current-dependent behavior and nonlinear charge-dependent electrical resistance. Self-directed channel Carbon-, Tungsten-, Chrome-, and Tin-based memristors have become commercially available nowadays and they are used for research purposes. All circuit components must be tested before their usage. It is expected that memristors will become commonly used in electronic circuits in the future. However, the literature has just a few memristor tests reported. To the best of our knowledge, there is not a suggested robustness test for the self-directed channel Carbon-based memristors in the literature. In this study, A recently suggested memristor robustness test which could be made using just a multimeter is modified using a series resistor. The test is tried on the Self-Directed Channel Carbon-Based memristors. Unfortunately, the test is found unreliable and invalid for the self-Directed Channel Carbon-Based memristors.

Tunable floating and grounded memristor emulator Model

ABSTRACT A Differential Difference Current Conveyor Transconductance Amplifier (DDCCTA) based resistor tunable memristor emulator has been proposed in this work. The emulator can be used in both grounded and floating circumstances. The proposed design incorporates only one active block along with few passive components. Moreover, the circuit can operate in both incremental and decremental modes, by simply changing the input ports. The circuit demonstrates all the characteristics of an ideal memristor up to 6 MHz. The proposed model has been simulated using TSMC 0.18m process parameter and occupies an area of 51 × 42.5 m2 chip-area, excluding capacitor. The circuit’s reliability has been verified by studying non-ideal, non-volatile, Monte-Carlo, process corner variations analysis. The circuit applicability has been tested through series/parallel combinations. To validate the experimental demonstration, AD844AN and CA3080 have been used to make a prototype, which shows good agreement with theoretical and simulation results.

Evolution between Volatile and Nonvolatile Resistive Switching Behaviors in Ag/TiOx/CeOy/F-Doped SnO2 Nanostructure-Based Memristor Devices for Information Processing Applications

It is well known that higher requirements have been put forward for the computing efficiency and storage speed of the data processing of memory devices in the post Moore era. In particular, if a memory device with multiple physical characteristics can be developed, it will play an important role in realizing multifunctional applications of electronic systems. Here, a nanoscale memristor device with a Ag/TiOx/CeOy/F-doped SnO2 structure was prepared, which shows many interesting physical phenomena with the changing of the applied voltage. In the low-voltage region (<1.5 V), the device presents a volatile property, while it presents a nonvolatile behavior when a higher voltage (>2 V) was applied. Interestingly, the non-zero-crossing current–voltage (I–V) hysteresis behavior caused by the internal electromotive force appears in the voltage region of 0.5–1 V. Furthermore, as the applied voltage increases, the device gradually displays ideal memristor behavior and exhibits the standard resistance switching characteristic accompanied by the negative differential resistance effect in the region of 3.5–4.0 V. Therefore, this nanoscale device with multiple physical properties opens up a promising way for understanding the emerging physical phenomena, and it will be expected to become a potential candidate for the next generation of multifunctional electronic devices.

Hidden firing patterns and memristor initial condition-offset boosting behavior in a memristive Hindmarsh-Rose neuron model

Electromagnetic induction can effectively induce abundant firing patterns in neurons. In modeling a neuron model with the electromagnetic induction effect, an electromagnetic induction current is frequently added to the state equation of membrane potential. To more properly reflect the non-uniform distribution of the ions inside and outside the neuron membrane, an ideal flux-controlled memristor with sinusoidal memductance function and non-linearly modulated input is raised to depict an electromagnetic induction effect on a Hindmarsh–Rose neuron model, and thereby, a three-dimensional (3D) memristive Hindmarsh–Rose (mHR) neuron model is built in this paper. The proposed mHR neuron model possesses no equilibrium point since the involvement of the ideal flux-controlled memristor, which induces the generation of hidden dynamics. Numerical results declare that the mHR neuron model can generate abundant hidden dynamics, i.e., periodic spiking, chaotic spiking, period-doubling bifurcation route, tangent bifurcation, and chaos crisis. These hidden dynamics are much related to the memristor coupling strength and externally applied stimulus. Afterward, the memristor initial condition-offset boosting behavior is revealed. This can trigger the generation of infinite multiple coexisting firing patterns along the memristor variable coordinate. These coexisting firing patterns have identical attractor topology but different locations in the phase plane. Finally, an analog circuit is designed for implementing the mHR neuron model, and PSIM-based circuit simulation is executed. The circuit-simulated results perfectly verify the generation of hidden infinite multiple coexisting initial condition-offset boosting firing patterns in the proposed mHR neuron model.

Characteristic Analysis and Circuit Implementation of a Novel Fractional-Order Memristor-Based Clamping Voltage Drift

The ideal magnetic flux-controlled memristor was introduced into a four-dimensional chaotic system and combined with fractional calculus theory, and a novel four-dimensional commensurate fractional-order system was proposed and solved using the Adomian decomposition method. The system orders, parameters, and initial values were studied as independent variables in the bifurcation diagram and Lyapunov exponents spectrum, and it was discovered that changing these variables can cause the system to exhibit more complex and rich dynamical behaviors. The system had an offset boosting, which was discovered by adding a constant term after the decoupled linear term. Finally, the results of the numerical simulation were verified through the use of analog circuits and FPGA designs, and a control scheme for the system circuit was also suggested.

Embedding the Dynamics of Forced Nonlinear Systems in Multistable Memristor Circuits

A well-known feature of memristors is that they makes the circuit dynamics much richer than that generated by classical <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$RLC$ </tex-math></inline-formula> circuits containing nonlinear resistors. In the case of circuits with ideal memristors, such a multistability property, i.e., the coexistence of many different attractors for a fixed set of parameters, is connected to the fact that the state space is composed of a continuum of invariant manifolds where either convergent or oscillatory and more complex behaviors can be displayed. In this paper we investigate the possibility of designing memristor circuits where known attractors are embedded into the invariant manifolds. We consider a class of forced nonlinear systems containing several systems which are known to display complex dynamics, and we investigate under which conditions the dynamics of any given system of the class can be reproduced by a circuit composed of a two-terminal (one port) element connected to a flux-controlled memristor. It is shown that an input-less circuit is capable to replicate the system attractors generated by varying the constant forcing input, once the parameters of the two-terminal element and the memristor nonlinear characteristic are suitably selected. Indeed, there is a one-one correspondence between the dynamics generated by the nonlinear system for a constant value of the input and that displayed on one of the invariant manifolds of the input-less memristor circuit. Some extensions concerning the case of non-constant forcing terms and the use of charge-controlled memristors are also provided. The results are illustrated via FitzHugh-Nagumo model and Duffing oscillator.

Convergence of Neural Networks with a Class of Real Memristors with Rectifying Characteristics

The paper considers a neural network with a class of real extended memristors obtained via the parallel connection of an ideal memristor and a nonlinear resistor. The resistor has the same rectifying characteristic for the current as that used in relevant models in the literature to account for diode-like effects at the interface between the memristor metal and insulating material. The paper proves some fundamental results on the trajectory convergence of this class of real memristor neural networks under the assumption that the interconnection matrix satisfies some symmetry conditions. First of all, the paper shows that, while in the case of neural networks with ideal memristors, it is possible to explicitly find functions of the state variables that are invariants of motions, the same functions can be used as Lyapunov functions that decrease along the trajectories in the case of real memristors with rectifying characteristics. This fundamental property is then used to study convergence by means of a reduction-of-order technique in combination with a Lyapunov approach. The theoretical predictions are verified via numerical simulations, and the convergence results are illustrated via the applications of real memristor neural networks to the solution of some image processing tasks in real time.

Synchronization of memristor based bidirectionally coupled Hindmarsh-Rose neurons

An ideal memristor is a device whose resistive memory value is determine by its initial conditions and the voltage that has been applied across its terminals. As such, it is a good candidate to model the synaptic plasticity of neural systems. When memristors are included in neural models, they are called memristive neural networks. In this contribution, we investigate the emergence of synchronization in an array of two identical Hindmarsh-Rose neurons bidirectionally coupled through their voltage variables via memristors. We show that, for a sufficiently large positive memductance, synchronization emerges between neurons while the memristors converge to constant synaptic weight values. We illustrate our results with numerical simulations.

A compact floating and grounded memristor model using single active element

Memristor with defined operational specifications is a challenging task that promotes innovation in emulation circuit modelling. This article presents a single active block based compact memristor emulator architecture which is suitable for both floating and grounded circuit topologies. It effectively operates in incremental/decremental modes in both the configurations. The proposed model utilizes only one Differential Voltage Current Conveyor Transconductance Amplifier (DVCCTA) as an active block along with a few passive components. It discourages the use of extra sub-circuit components like multiple active blocks, summers and multipliers. The circuit is intended to work at ±1 V of dc power supply and has a power consumption of 8.74 mW. The proposed emulator model exhibits all the characteristics of an ideal memristor with an operating frequency of 12.8 MHz. It has wide working voltage range of 50–500 mV. The memristor model is built and simulated using the TSMC 0.18 μm CMOS process parameter. The reliability and effectiveness of the proposed model is verified through non-ideal, Monte-Carlo, process corner, non-volatility and temperature variation analysis. Furthermore, the memristor prototype is constructed on the breadboard using discrete ICs AD844AN and CA3080. The experimental outcome is found in accordance with the simulation. The applicability of the proposed memristor model is verified by implementing a memristor based Schmitt trigger circuit.

Compact tunable memristor and inverse-memristor emulators with grounded passive elements

ABSTRACT The circuit-based emulation of memristor elements is becoming increasingly popular due to various advantages it offers over the physical architectures. The work reported in this paper presents the architectures of two novel circuit configurations dedicated to the realisation of an ideal memristor and a new but useful element, inverse memristor, respectively. Both presented circuit emulators are based on VDCC (Voltage Differencing Current Conveyor) active element. Over the previously reported bulky circuit emulators, the presented emulators have a significant design-related advantage since these are multiplier-less and grounded elements-based architectures. The developed circuits possess a tunability feature with respect to biasing voltage as well as the employed resistance. The mathematical description of pinch-off tuning and utilisation of inverse-memristor (for achieving better control over memristor characteristics) have been discussed with MATLAB simulations. To verify the workability of presented circuit architectures, the PSPICE environment has been chosen for simulation purpose. All the simulation results have been illustrated and discussed in detail. Later, the presented emulator circuits are developed using commercial ICs like CA3080 and AD844, and related results are described.

An experimental demonstration of the memristor test

A simple and unambiguous test has been recently suggested [J. Phys. D: Applied Physics, 52, 01LT01 (2018)] to check experimentally if a resistor with memory is indeed a memristor, namely a resistor whose resistance depends only on the charge that flows through it, or on the history of the voltage across it. However, although such a test would represent the litmus test for claims about memristors (in the ideal sense), it has yet to be applied widely to actual physical devices. In this paper, we experimentally apply it to a current-carrying wire interacting with a magnetic core, which was recently claimed to be a memristor (so-called `$\Phi$ memristor') [J. Appl. Phys. 125, 054504 (2019)]. The results of our experiment demonstrate unambiguously that this `$\Phi$ memristor' is not a memristor: it is simply an inductor with memory. This demonstration casts further doubts that ideal memristors do actually exist in nature or may be easily created in the lab.

Memristive functionality based on viscous magnetization dynamics

In viscous dynamics, velocity is proportional to the force. An ideal memristor is a device whose resistance changes at a rate proportional to the driving input. We present a proof-of-principle demonstration of the connection between viscous dynamics and memristive functionality by utilizing a thin-film ferromagnet/antiferromagnet bilayer, where viscous magnetization dynamics results from the frustration at the magnetic interface, and driving is provided by an external magnetic field. Thanks to the atomic scale of frustration effects, the presented approach is amenable to downscaling. It can also be adapted for electronic driving by spin torque, making it attractive for applications in neuromorphic circuits.

Electronically Tunable Flux-Controlled Resistorless Memristor Emulator

This article demonstrates a voltage differencing inverting buffered amplifier (VDIBA)-based resistorless flux-controlled memristor emulator circuit with tunability. Two VDIBA blocks serve as active components, and a grounded capacitor serving as a passive part. The proposed emulator design is devoid of multipliers and resistors through effective utilization of port relationships. Including tunability, the suggested emulator functions in both incremental and decremental modes. It accurately depicts the attributes of an ideal memristor up to 12.7 MHz and consumes a total power of 1.34 mW. The mathematical analysis is substantiated through Cadence simulation in 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu$</tex-math> </inline-formula> m Taiwan Semiconductor Manufacturing Company (TSMC) technology with the supply voltage of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\pm$</tex-math> </inline-formula> 1 V. Nonideal, single/parallel, Monte-Carlo sampling and corner analysis were conducted to confirm circuit resilience. The nonvolatile nature of the presented emulator model has also been included. A breadboard prototype incorporating the ICs CA3080 and LT1193 are built to conduct an experimental demonstration. The experimental findings were consistent with the theoretical expectations and simulation results.