Stacked ICs Research Articles

A new die-level flexible design-for-test architecture for 3D stacked ICs

A die-level design-for-test architecture for 3D stacked ICs is proposed. The main component of this architecture is a newly proposed configurable boundary cell, based on which flexible parallel test is achieved. Both of the number of parallel scan chains and their lengths can be configured during test. This test architecture features light-weight, high flexibility in parallel test configuration, modularity, and IEEE P1149.1 compatibility. In this work, both infrastructure and implementation aspects are illustrated. Experimental results demonstrate desired test acceleration. The acceleration ratio approximately reaches its limit, which equals the number of parallel scan chains, when the number of test vectors is over 300.

Novel BIST Solution to Test the TSV Interconnects in 3D Stacked IC’s

This paper proposes a novel technique of TSV BIST repair that targets the design yield and various test challenges of three-dimensional integrated circuits (3D stacked ICs). The proposed methodology is efficient to cover the various faults during the fabrication, the interconnect breakages, shorts, bridges, void formation, thermal and physical stress, etc., during the TSV fabrication and stacking of 3D ICs. The repair mechanism provides a redundancy feature to replace the failing TSVs with spare TSVs in the design. It provides a significant impact on yield compared to the standard TSV testing approach. Further analysis was performed on different stacked levels of 3D ICs, and the results were compared with the existing industrial methods in terms of the yield and test time parameters. The proposed mechanism showed a significant improvement of 12.5% in the yield and 17.5% in the test time and also recovered all defective chips efficiently.

Analysis of HBM Failure in 3D NAND Flash Memory

Electrostatic discharge (ESD) events are the main factors impacting the reliability of NAND Flash memory. The behavior of human body model (HBM) failure and the corresponding physical mechanism of 3D NAND Flash memory are investigated in this paper. A catastrophic burn-out failure during HBM zapping is first presented. Analysis shows that NMOS fingers’ local heating induced by inhomogeneous substrate resistance Rsub and local heating induced by the drain contact and 3D stacked IC (SIC) structure lead to the failure. Therefore, a new approach is proposed to reduce local heat generation. Finally, by increasing N+ length (NPL) and introducing a novel contact strip, the silicon result shows enhanced ESD robustness.

Towards a Description Synthesis of the Entanglement of the Substrate with the Interconnection Network, for Fast Modeling of 3D RF circuits

3D chip stacking is considered known to overcome conventional 2D-IC issues, using Trough Silicon Via (TSVs) to ensure vertical signal transmission between data. If the electrical behaviour of 3D interconnections (redistribution metal lines and through silicon vias) used in 3D IC stack technologies are to be explored in this paper, the substrate itself is of interest, via Green Kernels by solving Poisson's equation analytically. Using this technique, the substrate coupling and loss in IC's can be analysed. We implement our algorithms in MATLAB. This method has been already used; but, it permits to extract impedances for a stacked uniform layers substrate. We have extended for any numbers of embedded contacts, of any shape. On a second hand, we grasp the background noise between any two points, in the bulk, or at the surface, from a transfer impedance extraction technique. With an analog algorithm, a strength of this work, we calculate unsteady solutions of the heat equation, using a spreading resistance concept. This method has been adapted to stacked layers. With this general tool of impedance field, we investigate on the problems encountered by interconnects, especially the vias, the substrate, and their entanglement. A calculation of thermal mechanical stresses and their effects on substrate crack (max and min stresses), devices (i.e: transistors) and hotspots, are made to track the performance. But, to well understand the interconnection incidence on 3D system performances, it is important to consider the whole electrical context; it seems relevant to consider the possible couplings between vias, not only by the electromagnetic field, but also by any possible energy transfer between interconnects; more generally, one of actual problem is to determine where the energy is really confined in such 3D circuits, before find solutions to limit pollutions coming from electro-magneto -thermal phenomena or background noises.

Reduced Pin-Count Test Strategy for 3D Stacked ICs Using Simultaneous Bi-Directional Signaling Based Time Division Multiplexing

3D Stacked Integrated Circuits (SICs) offer a promising way to cope with the technology scaling; however, the test access requirements are highly complicated due to increased transistor density and a limited number of test channels. Moreover, although the vertical interconnects in 3D SIC are capable of high-speed data transfer, the overall test speed is restricted by scan-chains that are not optimized for timing. Reduced Pin-Count Testing (RPCT) has been effectively used under these scenarios. In particular, Time Division Multiplexing (TDM) allows full utilization of interconnect bandwidth while providing low scan frequencies supported by the scan chains. However, these methods rely on Uni-Directional Signaling (UDS), in which a chip terminal (pin or a TSV) can either be used to transmit or receive data at a given time. This requires that at least two chip terminals are available at every die interface (Tester-Die or Die-Die) to form a single test channel. In this paper, we propose Simultaneous Bi-Directional Signaling (SBS), which allows a chip terminal to be used simultaneously to send and receive data, thus forming a test channel using one pin instead of two. We demonstrate how SBS can be used in conjunction with TDM to achieve reduced pin count testing while using only half the number of pins compared to conventional TDM based methods, consuming only 22.6% additional power. Alternatively, the advantage could be manifested as a test time reduction by utilizing all available test channels, allowing more parallelism and test time reduction down to half compared to UDS-based TDM. Experiments using 45nm technology suggest that the proposed method can operate at up to 1.2 GHz test clock for a stack of 3-dies, whereas for higher frequencies, a binary-weighted transmitter is proposed capable of up to 2.46 GHz test clock.

Test Time Reduction of 3-D Stacked ICs Using Ternary Coded Simultaneous Bidirectional Signaling in Parallel Test Ports

In order to meet the increasing demand for more performance with reduced power consumption and chip form-factor, semiconductor manufacturing is moving toward 3-D stacked integrated circuits (SICs). One of the challenges in bringing this technology into realization is the complicated test accessibility requirements of 3-D chips, which apart from having adequate defect coverage, should also have minimal test time. A major limiting factor in test time improvement of ICs is the number of chip terminals, such as pins or through silicon vias (TSVs) available for bulk vector transport in testing. In the conventional design, a chip terminal is only used to either send or receive data at any given time. In this article, a test accessibility architecture based on ternary encoded simultaneous bidirectional signaling (SBS), intended for use in parallel test access mechanism (TAM) in system on chip (SoC)-based designs, is proposed. This method enables the use of chip terminals to simultaneously send and receive test vectors, effectively doubling the per-pin efficiency during testing. Experiments show that this technique reduces the overall test time (OTT) by up to 53.6% as compared to conventional TAM design methods.

A novel approach to mitigate stress induced defects at metal-dielectric interface in Redistribution layers for 3D IC stacking

Abstract The reliability of a redistribution layers in 3D IC is dependent on how well the different shape and size of metal connection with varying density are connected at the different metallization levels. The widely different coefficient of thermal expansion of metal (Cu ~16.5 × 10−6 m/mK) and dielectric (SiO2 ~ 3 × 10−6 m/mK) often leads to defects, such as cracking at the metal-dielectric interface. In this work, we present a manufacturing level friendly process modification to the conventional approach to present an almost crack free metal-dielectric interface for subsequent processing in the RDL fabrication. After the copper electroplating and chemical mechanical planarization (CMP), we use a cap layer to protect the top layer and anneal the metal. Finally, we repeat the CMP to remove the cap layer before sending the wafers for subsequent processing.

Minimizing Temperature Nonuniformity by Optimal Arrangement of Hotspots in Vertically Stacked Three-Dimensional Integrated Circuits

Abstract The semiconductor packaging technologies have seen its growth from multichip module (MCM), system in package (SiP), system on chip (SoC) to the heterogeneous integration of the MCM. Thermal management of multichip vertically integrated systems poses additional constraints and limitations beyond those for single chip modules. Three-dimensional-integrated circuits (3D ICs) technology is a potential approach for next-generation semiconductor packaging technologies. A 3D IC is formed by vertical interconnection of multiple substrates containing active devices which offer reduced die footprint and interconnect length. This paper discusses the optimal arrangement of two hotspots on each layer of a two-die stacked 3D IC. An analytical heat transfer model for prediction of three-dimensional temperature field of a 3D IC based on the solution of governing energy equations has been developed and used for this study. The model is subject to adiabatic boundary conditions at the walls except for the bottom wall which is subject to convective boundary condition. A feed-forward back propagation artificial neural network (ANN) is employed for obtaining the functional relationship between the location of the hotspots and the objectives. Genetic algorithm is employed for solving two nonconflicting objective functions subject to set of constraints. The first objective aims to minimize the maximum temperature on both layers, and the second objective aims to achieve temperature uniformity in the layers. The results of the optimization study are expected to provide recommendations on the design guidelines for arranging hotspots on vertically stacked substrates.

Thermosonic direct Cu pillar bonding for 3D die stacking

The emerging 3D IC stacking technology as one of the main platforms for 3D integration gains significant performance advantages by using copper (Cu) pillar interconnections. Although thermocompression Cu bonding offers reliable interconnections with demonstrated bond stability at high temperatures, it requires high pressures, high temperatures and long process time. As an alternative to thermocompression bonding, thermosonic flip-chip bonding of Cu-pillared silicon chips is studied here. By exploiting ultrasonic energy and inducing mechanical vibrations, which promotes the interfacial atomic diffusion, Cu-to-Cu bonding was facilitated in significantly lower bonding forces (3–6 MPa), shorter process windows (300–500 ms) and lower thermal budgets (140–240 °C). In this study, thermosonic bonding parameters (i.e., ultrasonic energy, bonding temperature and pressure) were optimized for Cu-pillared chips. The bonded samples were further characterized by die shear strength analysis and interfacial microscopy. It was found that thermosonic bonding can be regarded as a substitute for thermocompression bonding with enhanced bonding strength and invisible Cu interfaces. It was also proposed that thermosonic flip-chip bonding of Cu pillars can be utilized for die-to-wafer integration either as a single process or as a tacking process combined with a global post-processing.

Optimizing the Within Wafer Non-Uniformity at the Chemical Mechanical Planarization step in Interposers and RDL fabrication process for 3D IC stacking

Abstract Chemical Mechanical Planarization (CMP) is an integral step in fabrication processes of through silicon via based Interposer and Redistribution layer for routing. The key motivation in the CMP process is to achieve planarization with minimum recess and dishing on the metal routing sites. In this work we established the metrics for Within-wafer non-uniformity (WIWNU) and optimized the CMP parameters. Currently, there is no standard guideline for reporting the WIWNU during CMP and thus a better understanding and practice is needed to enhance post CMP uniformity across the wafer. The work reported in this article were conducted on 200 mm silicon wafers with either Copper or Tungsten to optimize the uniformity of removal rate with respect to polishing parameters, such as slurry flow, slurry composition, down force, relative velocity of wafer surface with pad, etc. With optimized CMP parameters for blank wafer, the WIWNU in patterned wafer were evaluated and analyzed for additional optimization in non-uniformity.

Advanced Low-K Polymer Dielectric Materials and Interfaces for Fine-Pitch Re-Distribution-Layer (RDL) to Enable 2.5D and Fan-out Packages

The rapid increase of devices with artificial intelligence (AI) and machine learning capabilities is driving the demand for growth in compute performance. With transistor scaling reaching physical limitations, the semiconductor industry is looking to system-scaling to deliver the performance improvements. Advanced packaging architectures capable of supporting these applications are 2.5D interposers, 3D IC stacking, chiplets and fan-out based packaging. All of these architectures require high-density interconnects capable of routing >200 IOs/mm/layer. This talk demonstrates advanced ultra-thin ( <10 µm), low-Dk (< 3.0) polymer dielectric material candidates capable of achieving I/O densities of 500 IOs/mm/layer. Current commercially available solutions based on silicon interposers suffer from conductor and dielectric losses because of restrictions on the dielectric material (SiO2). Polymer based dielectrics offer a compelling alternative because of the potential to reduce the capacitance of the traces and improve power efficiency alongside compatibility with low-cost panel-scalable processes. This idea is explored will be explored in this talk and we will demonstrate through modelling and characterization that low-Dk polymer dielectrics are a superior candidate to current dielectric material candidates The choice of polymer dielectric is driven by technology trends towards a)high-density fine-pitch routing b)system level thermo-mechanical reliability c)panel-scalable processing. This work examines four dielectric material candidates comprising of 3 material classes, namely photo-sensitive epoxy, non-photo-sensitive epoxy and BCB for next-generation interconnect technology. High-speed electrical simulations indicate that low-Dk materials can support data rates of >10Gbps which overcomes the limitations faced by conventional high Dk epoxy dielectrics and SiO2 alternatives. The biggest challenge in moving towards low-Dk materials is that these polymers are typically non-polar and do not adhere well which poses challenges in package integration. This work proposes a unique approach to improve polymer/metal interfacial adhesion by creating a hybrid layer with tailorable material properties using vapor-phase-infiltration (VPI). VPI exposes the polymeric material to a metal-organic reactant such as trimethyl aluminium (TMA) in a heated environment. Diffusional kinetics of the reactant are highly dependent on each step of the sequential process such as temperature, time of hold, exposure time, and co-reactants used. This process is superior compared to Atomic Layer deposition (ALD) in promoting the diffusion of organometallic precursors into the polymer subsurface because of a hold-period after exposure. VPI thereby provides a highly adaptable process to create tunable hybrid interfaces with target properties. VPI-treated polymers showed a 3X improvement in adhesion strength at the polymer/metal interface. This work dives into the kinetic factors required to achieve this adhesion improvement and characterizes the corresponding material structure changes. In summary, advanced low-Dk polymer dielectrics capable of meeting next-generation high-performance computing requirements are discussed. This work evaluates the key performance benefits from moving to low-Dk dielectric materials and tackles a critical challenge of integrating these materials as re-distribution layer (RDL) dielectrics by demonstrating 3X improvement in adhesion using VPI.

3D IC Stacking Technology for Reducing Power Consumption of Logic LSI System

3D IC Stacking Technology for Reducing Power Consumption of Logic LSI System

Full-field microsurface profilometry using image correlation without vertical scanning.

A full-field microprofilometry involving innovative image correlation was developed for profile measurement without vertical scanning. High-speed optical inspection has become critical for confirming precise dimensions in semiconductor fabrication such as microbumping in 3D stacked ICs and precision manufacturing. A digital micromirror device (DMD) is designed to serve as a point-light-source array in a quasiconfocal optical configuration and perform lateral scanning to minimize signal crosstalk between neighboring testing points. More importantly, multiple diffractive images are detected and measured with a prebuilt depth-correlated database to extract the height information of a tested surface. A 100-nm repeatability can be realized in the absence of a detector pinhole and without vertical scanning, thus achieving high-speed submicrometer-scale surface profilometry.

Time Division Multiplexing based Test Access for Stacked ICs

The test cost and complexity of stacked ICs (SICs) are higher than those of 2D-ICs because an SIC is tested at more stages before shipping. The existing test access architectures and their optimization techniques for SICs underutilize the tester-channel frequency because the test data is shifted at low scan-shift frequency due to test power constrain. Moreover, the wafer-level test frequency is constrained by limited probe-pin to pad contact current; however, the package-level test can be performed at a higher frequency yet lower than the tester-channel frequency offered by the testers. Therefore, we present a time-multiplexed test access architecture for SICs that leverages the tester-channel frequency at both the wafer-level and package-level tests. Unlike exiting architectures, the proposed architecture does not require the knowledge of the number of dies to be stacked and the hierarchical tier of each die. The proposed architecture is discussed for SICs based on IEEE standards 1149.1 and 1500. The experimental results with a synthetic SIC, constructed with ITC’02 benchmark SoCs, show significant reduction in the test time. Furthermore, the analyses based on the test frequency limits and the number of stacked dies show that the proposed architecture scales well with increasing frequency limits and the number of stacked dies.

High-Efficiency Stacked Power Amplifier IC With 23% Fractional Bandwidth for Average Power Tracking Application

This paper presents a two-stage stacked power amplifier integrated circuit (PAIC) for broadband and high efficiency using a 2-μm InGap/GaAs HBT process with a second-harmonic control circuit and a bias-switching circuit for an average power tracking (APT) application. For APT operation, active bias circuits with a bias switching circuit for the stacked stage were proposed. A simple L-section matching network with a second-harmonic termination circuit was adopted for broad bandwidth and high efficiency. The frequency-independent power and efficiency contours for fundamental and second-harmonic frequency band were extracted at the current-source plane of the transistor. The implemented two-stage PAIC was evaluated using a long-term evolution signal with a peak-to-average power ratio (PAPR) of 7.5 dB and a signal bandwidth of 10 MHz. From 1.55 to 1.95 GHz, the power amplifier exhibited average output power ranging from 27.4 to 28.5 dBm, a power gain of more than 28.6 dB, and a power-added efficiency (PAE) of 36.5 to 41.2% at an ACLR of -30 dBc. At an average output power back-off of 5 dB, the PAE improved to 29.5% with APT using an external buck-boost dc-dc converter, while it was 18.7% without APT.

Nitrogen passivation formation on Cu surface by Ar–N2 plasma for Cu-to-Cu wafer stacking application

Wafer stacking technology provides reduced interconnect delay, improved bandwidth, reduced form factor, and decreased cost. Solder-based metallic die bonding is presently utilized in high-volume manufacturing, but Cu-based metallic wafer bonding is quickly becoming a key bonding technique for next generation 3D IC and heterogeneous stacking applications. In this study, Ar–N2 plasma treatment on Cu surface was investigated to passivate Cu surface with nitrogen and to enhance the bonding quality of Cu-to-Cu wafer bonding. The Ar–N2 plasma treatment was performed by conventional DC sputtering under 5 mTorr working pressure with different Ar–N2 partial pressures. Then, the effect of Ar–N2 plasma treatment on Cu surface was evaluated structurally and electrically. It was observed that the Ar–N2 plasma treatment with high nitrogen partial pressure over a sufficient plasma treatment time provided activated Cu surface, reduction of copper oxide and chemisorbed nitrogen, and copper nitride passivation. The Ar–N2 plasma treatment of Cu surface was found to be a potential pretreatment method for Cu-to-Cu bonding.

Hybrid P-Channel/N-Substrate Poly-Si Nanosheet Junctionless Field-Effect Transistors With Trench and Gate-All-Around Structure

This paper demonstrates the gate-all-around P/N hybrid nanosheet p-channel junctionless field-effect transistors (GAA NS-JLFET) with trench and raised source and drain structure. The GAA NS-JLFET exhibits the superior electrical properties, including high field-effect mobility (18.9 cm2/Vs), high on/off current ratio (>5 × 106), steep subthreshold slope (136 mV/dec.), and low DILB (60 mV/V). The high mobility and steep subthreshold slope of this GAA NS-JLFET indicates that the conducting hole filled the whole thin nanosheet channel. This GAA NS-JLFET is simple to fabricate and highly favorable for use in advanced system-on-panel and three-dimensional stacked ICs applications.

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

A Design for Testability of Open Defects at Interconnects in 3D Stacked ICs

A novel efficient TSV built-in test for stacked 3D ICs

A through-silicon via (TSV) is established as the main enabler for a three-dimensional integrated circuit (3D IC) that increases system density and compactness. The exponential increase in TSV density led to TSV-induced catastrophic and parametric faults. We propose an original architecture that detects errors caused by TSV manufacturing defects. The proposed design for testability is a built-in technique that detects errors in an early manufacturing stage and is hence very economically attractive. The proposal is capable of testing each and every TSV in the network. The technique achieves high fault coverage and high observability.

過渡熱解析による3次元積層IC内のアンダーフィル層の熱抵抗の評価

過渡熱解析による3次元積層IC内のアンダーフィル層の熱抵抗の評価