Reliability Of IC Packages Research Articles

Effects of Creep Parameters of Lead-Free Solders on Fatigue Reliability of 3D IC Packages with through Silicon Vias

3D IC packaging technologies are emerging as they are able to respond to the demands for smaller form-factor, faster, high density interconnection at cheaper cost. Moreover, for a 3D IC package, through silicon vias (TSVs) provide high wiring density interconnection, thus improve electrical performance due to shorter interconnection from the chip to the substrate. However, TSV technology is still facing severe challenges as the physical design problems due to the existence of the copper vias remain resolved. Apart from thermal expansion mismatch, the problems are due in part to the nonlinear behavior of SAC lead-free solder used in the package as an echo of environmental concerns and RoHS directive. However, there exists a wide range of values of the parameters of the creep model used to describe the nonlinear behavior of SAC. The effects of the variations of these parameters on the thermal reliability of IC packages, particularly the 3D IC package with built-in TSVs considered herein, is of interest. Presented in the paper is a study on assessment of the influence of the creep parameters of SAC solders on the isothermal fatigue reliability of a 3D IC package with built-in TSVs. The results show that as the strain rate is linear proportional to C1, a larger C1 tends to enlarge the strain rate hence decrease the fatigue life. However, the relationship between the fatigue life of the specific IC package is not linear. Although the variation of C2 causes a large variation in the fatigue life, its effect becomes insignificant when a moderate value of C2 is considered. As a power parameter to the hyperbolic sine function of the creep model, C3 contributes a 40% variation to the fatigue life. Lastly, the fatigue life increases with C4 value, and the gain of fatigue life increases as C4 approaches the upper limit considered herein.

Study of Interfacial Moisture Diffusion at Epoxy/Cu Interface

The delamination at the epoxy/copper interface adversely affects the reliability of IC packages and this is a common failure mode during the qualification process. One of the factors governing the interfacial delamination is the moisture content at the interface. This study has developed an experimental measurement procedure for interfacial moisture diffusion using the Fourier Transform Infrared–Multiple Internal Reflection (FT-IR–MIR) technique with a new calibration method. In this study, interfacial moisture was detected by FT-IR–MIR on an isothermal gloptop epoxy system at selected locations on the epoxy/copper interface of samples which went through 1000 h of 85% relative humidity at 85°C pre-conditioning. By comparing the FT-IR–MIR results for epoxy samples with different pre-conditioning times, the interfacial moisture contents at different positions in the epoxy sample were obtained and a comparison was made. This study has demonstrated that the seepage mechanism along the epoxy/copper interface is the major driver for interfacial delamination under moisture pre-conditioning. It is the prevailing mechanism as compared to the established bulk diffusion mechanism in the epoxy molding compound. Surface analyses conducted on fracture surfaces of button shear test specimens show that interfacial moisture diffusion affects the cuprous oxide content in the epoxy/copper interfacial region and this leads to adhesion degradation.

Solid state interfacial reaction of Sn–37Pb and Sn–3.5Ag solders with Ni–P under bump metallization

Thermal aging is one of the accelerated tests for IC package reliability during manufacturing processes and under actual usage conditions. During the process of thermal aging, intermetallic compounds (IMC) grow continuously due to element diffusion, resulting in their morphology change and thickness increase. In this work, the solid state reaction between electroless Ni–P and two types of Sn-based solders (Sn–3.5Ag and Sn–37Pb) has been investigated. Three distinctive layers, Ni 3Sn 4, NiSnP and Ni 3P, were found between the Sn-containing solders and Ni–P under bump metallization. The growth rates of Ni 3Sn 4 IMC at different temperatures were obtained from the aged samples and the activation energy of Ni 3Sn 4 growth was estimated. The kinetic data obtained show that the Ni 3Sn 4 in the Sn–3.5Ag/Ni–P joints grows much faster than with the Sn–37Pb solder under the same condition. Kirkendall voids are found inside the Ni 3P layer after thermal aging. The void formation mechanism is due to net Ni out-flux into the solder area.

A computer‐controlled environmental test system for high pin‐count integrated circuit packages

AbstractAn automated environmental stress testing system, designed and assembled for testing of high pin‐count integrated circuit packages and surface mount solder joint reliability is described. Details are given of the software and hardware used in the control of the environment chambers used, in monitoring of test specimen reliability parameters and in control and monitoring of special purpose integrated circuits for testing of IC package reliability. In addition, an automatic system for monitoring of the resistance of fine pitch surface mount solder joints and for detection and recording of thermally induced intermittent open circuits in these joints is described.

Effect of material interactions during thermal shock testing on IC package reliability

This study attempts to elucidate the interaction of three main material components in a plastic package: mold compound, die attach, and die coating. The investigation was divided into three parts, addressing the combined effect of the previous three components, the influence of the thickness of the polyimide coating, and the effect of the mold compound alone, respectively. Five mold compounds (first generation low-stress, second generation low stress, third generation ultra low-stress, moisture resistant, and anti-crack compound for thin packages), two die attach resins (low-stress epoxy and ultra low-stress silicone-modified epoxy), and two die coats (standard polyimide and photo-sensitive polyimide) were tested. The authors discuss how combining different high- and low-stress materials affects the failure rate and the types of failures. Three main results were obtained: (1) die attach is the most important factor since its compliance during thermal shock affected the interfacial integrity of the die; (2) thicker coatings of polyimide (>8 mu m) give better protection to the die surface; and (3) the anticrack molding formulation with the lowest CTE produces the fewest failures.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>