This paper discusses the problems associated with obtaining adequate test coverage from random self-test for thermal conduction modules (TCMs) in the air-cooled IBM Enterprise System/9000™ Type 9121 processors. Each 9121 TCM contains approximately a quarter of a million circuits. The present complexity of the TCMs made previous testing methods such as chip-in-place (CIP) testing inviable. The solution was to apply self-test techniques to the 9121 TCMs during the manufacturing process. Analytical and simulation techniques were used to predict the random-pattern testability of the TCMs. The results of the self-test process for the five distinct 9121 processor TCMs are presented. Methods of identifying and modifying random-pattern-resistant logic structures are discussed. It is also proposed that a hybrid approach combining random self-test with deterministic test generation can be used to enhance testability.