I7 Processor Research Articles

High-performance multi-GPU solver for describing nonlinear acoustic waves in homogeneous thermoviscous media

A double-precision numerical solver to describe the propagation of high-intensity ultrasound fluctuations using a novel finite-amplitude compressible acoustic model working in multiple processing units (GPUs) is presented. The present solver is based on a conservative hyperbolic formulation derived from a variational analysis of the compressible Navier–Stokes equations and is implemented using an explicit high-order finite difference strategy. In this work, a WENO–Z reconstruction scheme along with a high-order finite-difference stencil are used to approximate the contributions of convective and diffusive spatial operators, respectively. The spatial operators are then associated to a low–storage Runge–Kutta scheme to integrate the system explicitly in time. The present multi-GPU implementation aims to make the best use of every single GPU and gain optimal performance of the algorithm on the per-node basis. To assess the performance of the present solver, a typical mini-server computer with 4 Tesla K80 dual GPU accelerators is used. The results show that the present formulation scales linearly for large domain problems. Moreover, when compared to an OpenMP implementation running with an i7 processor of 4.2 GHz, this is outperformed by our MPI-GPU implementation by a factor of 99. In this work, the present multi-GPU solver is illustrated with a three-dimensional simulation of a highly-intense focused ultrasound propagation.

EVALUATION OF OPENMP OPTIMIZATION IN HETEROGENEOUS COMPUTING MODE BY CODE OFFLOADING ON INTEL XEON PHI CO-PROCESSOR

As the computing needs are increasing, the utilization of compute powers of multi-processors and co-processors together is an active area of research. This paradigm is known as Heterogeneous computing. With the increasing data sizes and complexity of algorithms, and dead lock reached in processor clock frequency due to power constraints, multi core and many core CPUs and GPUs have been used for parallel computing. This has become an inevitable approach for high volume data processing such as image processing. In the process of evaluation the authors had earlier tested on the Intel Quad Core i7 (8 threads) processor and dual Intel Xeon 12 core (48 threads) CPUs by optimizing an image processing code on K-Means clustering in multispectral feature space using remote sensing data[1]. The maximum speedup 5x is achieved on Intel i7 core CPU and speedup of 13x is achieved on Intel Xeon CPU by invoking dynamic scheduling when number of threads deployed are large. In continuation of the earlier studies, the present study analyses the Intel Xeon phi coprocessor 7120P(device) HPC accelerator performance with processor base frequency of 1.24 GHz along with OpenMP Parallel computing model. It is observed that the offloading will not give best result with small data size. To get the full benefits of offloading on Intel Xeon phi coprocessor, computation offloading with OpenMP utilizing both processor and coprocessor gains accelerations and increases the performance if communication overhead is less than the computation times which is highly application dependent.

Osseous and digital subtraction angiography image fusion via various enhancement schemes and Laplacian pyramid transformations

Image fusion is a significant medical imaging tool which integrates the complimentary information from various sources into a single frame for enhanced visual perception. The fusion of osseous and vascular information is used for the localization of various medical abnormalities. The emergence of gradient reversal artefacts and halo effects in the fused image are of major concern for the researchers. In this paper we propose an image fusion technique to mitigate the artefact issues in case of bone and vessel image fusion. An ideal image fusion rule transfers maximum information from source images to fused image with least amount of distortion or loss. In this regard we have transformed the source images with the help of KL transformations and Ripplet transform. The artefacts are controlled via anisotropic diffusion filtering. The Laplacian pyramidal based fusion is employed to fuse the mask and DSA images. For the validation of our proposed methodology conventional as well gradient based metrics along with human visual perception are employed. The proposed methodology outperforms eight other state-of-the-art image fusion techniques with far better visual results. The entire algorithm is implemented in MATLAB 2012 with core i5 processor.

Exploration of Compiler Optimization Sequences Using a Hybrid Approach

Finding a program-specific compiler optimization sequence is a challenge, due to the large number of optimizations provided by optimizing compilers. As a result, researchers have proposed design-space exploration schemes. This paper also presents a design-space exploration scheme, which aims to search for a compiler optimization sequence. Our hybrid approach relies on sequences previously generated for a set of training programs, with the purpose of finding optimizations and their order of application. In the first step, a clustering algorithm chooses optimizations, and in the second step, a metaheuristic algorithm discovers the sequence, in which the compiler will apply each optimization. We evaluate our approach using the LLVM compiler, and an I7 processor, respectively. The results show that we can find optimization sequences that result in target codes that, when executed on the I7 processor, outperform the standard optimization level O3, by an average improvement of 8.01 % and 6.07 %, on Polybench and cBench benchmark suites, respectively. In addition, our approach outperforms the method proposed by Purini and Jain, Best10, by an average improvement of 24.22 % and 38.81 %, considering the two benchmarks suites.

REPLICA MBTAC: multithreaded dual-mode processor

Prevailing trend in design of chip multiprocessors (CMP) has been that single-core processors are replicated. Therefore, they typically define asynchronous computational model, require heavily locality-aware memory allocation, and present high overheads in intercommunication. This kind of properties make parallel programming very challenging and prone to errors. We introduce our new dual-mode MultiBunched/Threaded Architecture with Chaining (MBTAC) processor core, the main building block of the REPLICA CMP. It provides a modern, sophisticated way for writing general purpose parallel programs backed up by native execution capabilities/realization of key concepts. These include support for cost-efficient machine instruction-level synchronization and uniform shared global memory for enabling easy-to-program memory allocation of data structures and data movement. MBTAC makes use of low-overhead thread-context switching solution; it has parallel computing savvy functional unit organization to exploit inter-thread instruction-level parallelism and highly efficient multioperations. To evaluate the goodness of our proposal, we implemented three MBTAC constellations featuring up to 2048 parallel threads on FPGA, compared it with respect to DLX and Intel’s Core i7 processors. The results point toward high performance in communication-intensive problems, simplified parallel programmability, and regular, implementation-friendly structure.

Performance and energy metrics for multi-threaded applications on DVFS processors

Due to their internal execution characteristics, application programs exploit the hardware very differently, which leads to a quite diverse behavior concerning their performance or the energy consumed for their execution. A change of the operational frequency of DVFS processors leads to further variations in performance and energy consumption, as does the exploitation of thread parallelism on multicores. This article combines frequency scaling and thread-parallelism and considers several new metrics for the evaluation of an application's performance and energy consumption. As application programs, the PARSEC benchmark suite and the SPLASH-2 benchmark suite are investigated. The PARSEC benchmark suite provides an up-to-date collection of applications with different workloads on chip-multiprocessors. The SPLASH-2 is a common suite for scientific studies on parallel shared memory machines. Intel Core i7 processors are used as hardware platforms for the evaluation.

Effective Implementation of Matrix–Vector Multiplication on Intel's AVX multicore Processor

Matrix–vector multiplication kernel is one of the most important and common computational operations which form the core of varied important application areas such as scientific and engineering applications. Therefore, it is substantial to optimize and accelerate its implementation. This paper proposes an optimized algorithm for single-precision matrix–vector multiplication (SGEMV) on the Intel core i7 processor. An overview of the Intel's advanced vector extension instructions in implementing dense matrix–vector multiplication kernels in parallel has been comprehensively addressed. Also, a variety of performance optimization techniques using Intel's advanced vector extension (AVX) instruction sets, memory access optimization, and OpenMP parallelization has been designed. Additionally, the performance of the proposed algorithms is evaluated in compared to the latest version of Intel Math Kernel Library SGEMV 2017 subroutines because Intel Math Kernel Library subroutines also consider the same optimization methods that are used in this paper. In this paper, we have introduced an overview of the optimization techniques, have explained the specific details of handling them in the proposed algorithm, and also have showed the advantages and the challenges of combining them together in contrast to the previous works which usually have concentrated on a single technique and the performance achieved by it. The guidelines of parallel implementation of the proposed algorithm and the characteristics of the target architecture that should be considered when implementing this algorithm have been investigated. An overview of the Intel's advanced vector extension instructions in implementing dense matrix–vector multiplication kernels in parallel has been comprehensively addressed. A comparative study of the two most popularly used C++ compilers: Intel C++ compiler 17.0 in Intel Parallel Studio XE 2017 against Microsoft Visual Studio C++ compiler 2015 has been investigated. Finally, the comparison between two primary ways of utilizing AVX instructions: inline assembly and intrinsic functions, and the comparison between single-core and multi-core platforms have introduced. The results are evaluated in Intel Core i7-5600U processor of 2.6 GHz with 128 KB L1 cache, 512 KB L2 cache, and 4MB L3 cache running on windows 10 operating system and on a Broadwell system. The obtained results of the proposed optimized algorithm are implemented on square matrices of different large sizes range from 1024 to 19456. The results indicate a performance improvement of 18.2% and 14.1% for (y = A. x) and (y = AT. x) respectively in compared with the results which are obtained using the latest version of Intel Math Kernel Library 2017(SGEMV) subroutines on multi-core platform.

Heat Development and Comparison Between the Steady and Pulsating Flows Through Aluminum Foam Heat Sink

Continuous improvements in electronic devices for high-performance computers have led to a need for new and more effective methods of chip cooling. The first purpose of this study was to investigate the heat transfer development and characteristics of aluminum foam heat sink subjected to steady water flow for electronics cooling (Intel core i7 processor). The second purpose was to implement a new type of water flow through the aluminum foam, which is pulsating or oscillating flow in order to achieve more uniform temperature distribution over the electronic surfaces. The aluminum foam heat sink was subjected to a water flow covering the non-Darcy laminar flow regime (297–1353 Reynolds numbers). The bottom side of the heat sink was heated with a heat flux between 8.5 and 13.8 W/cm2. The pulsating flow frequency was ranged from 0.04 to 0.1 Hz. In addition, in order to complement the experimental studies, a numerical model was developed using finite element method and compared with the experimental data. The results revealed that the thermal entry length of the fluid flow through metal foam (porous media) is much smaller than that for laminar internal flow through empty channel. The result also showed that the local surface temperature increases along with increasing the axial flow direction for steady water flow case. On the other hand, for pulsating flow, the local temperature distributions act as a convex profile with the maximum surface temperature at the center of the test section. In addition, it was observed that the pulsating water flow through the aluminum foam heat sink achieves enhancement by 14% in the average Nusselt number and by 73% in temperature uniformity over the surface compared with steady water flow case.

On the injection of hardware faults in virtualized multicore systems

Virtualized multicore systems represent an emerging computing paradigm in the critical systems industry. Virtualization-based solutions leverage the different cores of the processor to run operating systems and applications within separate partitions, to support the development of parallel mixed-criticality systems, and to improve fault-tolerance by protecting and isolating the operating environments. The critical systems industry is subjected to international standards, which recommend fault injection as a mean to contribute with evidence to safety cases. This paper proposes a framework to inject hardware faults in virtualized multicore systems. Our proposal capitalizes on the error reporting architecture of modern processors and allows injecting faults both at hypervisor- and guest-OS-level. We implement the framework in the context of the widely used Intel Core i7 processor and Xen hypervisor. We demonstrate the use of the framework by means of about 60,000 injection experiments in a Linux-based virtualized multicore system installation.

A Comparative Experimental Design and Performance Analysis of Snort-Based Intrusion Detection System in Practical Computer Networks

As one of the most reliable technologies, network intrusion detection system (NIDS) allows the monitoring of incoming and outgoing traffic to identify unauthorised usage and mishandling of attackers in computer network systems. To this extent, this paper investigates the experimental performance of Snort-based NIDS (S-NIDS) in a practical network with the latest technology in various network scenarios including high data speed and/or heavy traffic and/or large packet size. An effective testbed is designed based on Snort using different muti-core processors, e.g., i5 and i7, with different operating systems, e.g., Windows 7, Windows Server and Linux. Furthermore, considering an enterprise network consisting of multiple virtual local area networks (VLANs), a centralised parallel S-NIDS (CPS-NIDS) is proposed with the support of a centralised database server to deal with high data speed and heavy traffic. Experimental evaluation is carried out for each network configuration to evaluate the performance of the S-NIDS in different network scenarios as well as validating the effectiveness of the proposed CPS-NIDS. In particular, by analysing packet analysis efficiency, an improved performance of up to 10% is shown to be achieved with Linux over other operating systems, while up to 8% of improved performance can be achieved with i7 over i5 processors.

Using the Vehicle Routing Problem to reduce field completion times with multiple machines

The Vehicle Routing Problem (VRP) is a powerful tool used to express many logistics problems, yet unlike other vehicle routing challenges, agricultural field work consists of machine paths that completely cover a field. In this work, the allocation and ordering of field paths among a number of available machines has been transformed into a VRP that enables optimization of completion time for the entire field. A basic heuristic algorithm (a modified form of the common Clarke-Wright algorithm) and a meta-heuristic algorithm, Tabu Search, were employed for optimization. Both techniques were evaluated through computer simulations in two fields: a hypothetical basic rectangular field and a more complex, real-world field. Field completion times and effective field capacity were calculated for cases when 1, 2, 3, 5, and 10 vehicles were used simultaneously. Although the Tabu Search method required more than two hours to produce its solution on an Intel i7 processor compared to less than one second for the method based on Clarke-Wright, Tabu Search provided better solutions that resulted in reduced field completion times and increased effective field capacity. The benefit provided by Tabu Search was larger in the more complex field and as the number of vehicles increased. With ten vehicles in the real-world field, the benefit provided by Tabu Search over the modified Clarke-Wright resulted in reduced completion time of 32%, but even with only three vehicles a 15% reduction was obtained. While ten vehicles may only be applicable with future autonomous machines, simultaneous usage of three machines is not uncommon in current production. As producers consider using multiple machines to improve field completion times and effective field capacity, optimization of the vehicle routing will play an important role in ensuring those improvements are fully realized.

Paralelização do algoritmo SUFI2: Uma abordagem Windows

The Soil and Water Assessment Tool (SWAT) has been used for evaluating land use changes on water resources worldwide, and like many models, SWAT requires calibration. However, the execution time of these calibrations can be rather long, reducing the time available for proper analysis. This paper presents a Windows approach for calibrating SWAT using a multinodal cluster computer, composed of six computers with i7 processors (3.2 GHz; 12 cores), 8 GB RAM and 1 TB HDD each. The only requirement for this type of cluster is to have 64-bit processors. Our computers were setup with Windows Server HPC 2012 R2, a network switch 10/100, and regular Ethernet cables. We used the SUFI2 algorithm that comes with SWAT-CUP package to perform calibrations with 100 simulations at node level. Calibration runs were configured as follows: 1-12 (1 process interval), and 12-72 (12 processes interval), resulting in 17 runs. Each run was repeated three times, and results are presented as the mean execution time, in order to minimize any influence of resources fluctuations. Results showed that time of execution was reduced by almost half by using nine processes (15 min) in comparison with the one node control (28 min). We observed a linear decrease of execution time from one to nine processes. With additional processes, execution time increased about 23% and stabilized at 80% of the control. All processing is divided into five steps: distribute files (2.24% of all processing time), organize samples (0.89%), run SWAT (47.59%), collect results (46.51%) and cleanup (0.28%). Normal 0 21 false false false PT-BR X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabela normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:10.0pt; font-family:"Calibri","sans-serif";}

SOLAR: Services-oriented Deep Learning Architectures

Deep learning has been an emerging field of machine learning during past decades. However, the diversity and large scale data size have posed significant challenge to construct a flexible and high performance implementations of deep learning neural networks. In order to improve the performance as well to maintain the scalability, in this paper we present SOLAR, a services-oriented deep learning architecture using various accelerators like GPU and FPGA. SOLAR provides a uniform programming model to users so that the hardware implementation and the scheduling is invisible to the programmers. At runtime, the services can be executed either on the software processors or the hardware accelerators. To leverage the trade-offs between the metrics among performance, power, energy, and efficiency, we present a multitarget design space exploration. Experimental results on the real state-of-the-art FPGA board demonstrate that the SOLAR is able to provide a ubiquitous framework for diverse applications without increasing the burden of the programmers. Moreover, the speedup of the GPU and FPGA hardware accelerator in SOLAR can achieve significant speedup comparing to the conventional Intel i5 processors with great scalability.

Optimizing image spatial filtering on single CPU core

Nowadays, computing becomes a service on cloud computing resources. Users reserve virtual machines to execute their applications with minimum number of processing cores to save money. Optimizing user applications on the level of single core of a physical machine is highly desirable to users to reduce cost, as well as to cloud providers to reduce power consumption. In this paper, we showed how to exploit all the processing resources available in a single CPU physical core to optimize the performance of the 2D spatial filtering operation, a basic kernel in important image and multimedia applications such as image enhancement, edge detection, image segmentation, and image analysis. We proposed a novel computational procedure to restructure the conventional image filtering operation. Then, we demonstrated the merits of combining hand-optimized source-code restructuring, auto-optimized compiler techniques including vectorization, and hand-optimized threading to squeeze the performance of a single CPU core. Our intensive performance evaluations, using Sobel filters, on a variety of image sizes using the Linux Perf tool on a single core of the quad-core Intel Core i7 processor showed that our source-code restructurings with compiler auto-vectorization, using Intel AVX vector instructions, is 1.3X better than the non-restructured auto-vectorized version of the CImg library for computing the image gradient. Moreover, using OpenMP library directives we studied different image partitioning strategies to better exploit the two hardware threads inside a CPU core which boosted performance to 2.6X. Compared with the conventional CImg implementation, we obtained an average enhancement of 5.0X for image sizes ranging from 0.5 MPixel to 8 MPixel. However, comparing our best-optimized code to the conventional non-optimized serial code, without threading, resulted in a significant enhancement of 23X. The overall results showed how significant performance in important image processing applications can be obtained by applying source-code restructurings before employing any automatic compiler optimizations to exploit ILP, DLP and TLP parallelism degrees inside a single core of a multi-core CPU.

Edge Detection and Features Extraction for Dental X-Ray

Recently, the dental X-Ray images have been used in different applications, particularly in the forensic field. The researchers focuses on the separation of the underlying teeth individually to obtain their features. These features can be utilized as a key solution for the identifications. In this paper, an edge detection of the involved teeth is proposed using a three stages MATLAB algorithm based on different methods such as, CLAHE, Canny, Otsu's, and 8-Connectivity. In addition, the proposed algorithm extracts the features of the investigated teeth as an exported file. These features are Standard Deviation (STD), Euler number and Area which are extracted from the bite-wing images. The stages of the proposed algorithm are image segmentation, classification and features extraction. It is important to note that the missing teeth has been considered in case of appearance. The missing teeth are assumed to be a separated objects. This is to overtake the problem of missing teeth after registering the original ones in the stored database used for identifications. The obtained results show the clear outperformance of the proposed algorithm in terms of edge detection and features’ extraction. The missing teeth in an image are tested and the achieved results presents the detection and features of such teeth dramatically. The proposed system is implemented and tested in the MATLAB software environment using a personal computer of a Core(TM) i7 processor and 6 GB RAM over a 64-Windows 10 operating system.

Experimental study of using γ-Al2O3–water nanofluid flow through aluminum foam heat sink: Comparison with numerical approach

The interaction between nanofluids and porous structured heat sinks is not well documented. In addition, the micro-miniaturization of electronic components has led to an increase in the heat dissipation rate of electronic chips. As a result, researchers are now searching for new cooling techniques that allow for the rapid removal of the heat generated from electronic components. The purpose of this study was to investigate the heat transfer characteristics and thermal performance of an ERG aluminum foam heat sink for the Intel core i7 processor. The aluminum foam heat sink was subjected to a steady flow of γ-Al2O3-water nanofluid covering the entire non-Darcy flow regime (210–631 Reynolds numbers). The γ-Al2O3 nanoparticle concentrations (volume percent) ranged from 0.1vol% to 0.6vol%. The experimental results revealed that the average Nusselt number was enhanced by 20% when the ERG aluminum foam was used (compared with the empty channel). The results also revealed that at low volume fractions of 0.1vol% and 0.2vol%, the γ-Al2O3-water nanofluids led to an enhancement in both the local and average Nusselt numbers. The maximum enhancement of the heat transfer rate was achieved at 0.2vol% and there was a sudden drop in the positive effect at 0.3vol% (compared with pure water). The positive effect then showed a slight increase along with increases in the volume fraction of the nanoparticles up to 0.6vol%. This heat transfer enhancement trend due to the presence of nanofluids is related to the mechanism which causes the superior thermal properties of nanofluids. When compared with pure water, optimal removal of the heat generated from the surface was achieved at a 0.2vol% concentration of γ-Al2O3-water nanofluid. The average enhancement percentages of the Nusselt number at a 0.2vol% nanofluid concentration compared with pure water were 37% and 28% at Reynolds numbers of 601.3 and 210, respectively. The numerical results were in good agreement with the experimental data of local Nusselt number and local temperature with a maximum relative error of 3% and 2%, respectively.

Performance Evaluation of Matrix-Matrix Multiplications Using Intel's Advanced Vector Extensions (AVX)

Intel's Advanced Vector Extensions is known as single instruction multiple data streams (SIMD), and the instruction sets is introduced in the second-generation Intel Core processor family. This new technology is supported by new generations of Intel and AMD processors. The advanced vector extensions (AVX) exploits single instruction multiple data (SIMD) computing units for fine grained-parallelism. These instructions process multiple data elements simultaneously and independently. Many applications such as signal processing, recognition, visual processing, scientific and engineering numerical, physics and other areas of applications need for vector floating point performance supported by AVX. Matrix-Matrix multiplications is the core of many important algorithms such as signal processing, scientific and engineering numerical, so it is substantial to accelerate implementation of matrix-matrix multiplications. It is very important to use appropriate compilers that can optimally utilize the new features of the evolving processors. For this purpose, a clear vision on the performance of the compilers on performance characteristics of AVX is needed. In addition choosing the appropriate programming method is substantial to gain the best performance. In this paper, the performance evaluation of matrix-matrix multiplications in three forms (C=A. B, C=A. BT, and C=AT. B), using Intel's advanced vector extension (AVX) instruction sets has been reported. The obtained results are compared using inline assembly versus intrinsic functions for programming. A comparative study to indicate the effects of two widely used C++ compilers: Intel C++ compiler (ICC) in Intel Parallel Studio XE 2016 against Microsoft Visual Studio C++ compiler 2015 (MSVC++) has been investigated. The results are evaluated on Intel Core i7 processor on a Broadwell system for square matrices of different large sizes. The results demonstrate that the Intel compiler has better performance than MSVC++ compiler by 1.34, 1.32, and 1.22 using inline assembly language and by 1.36, 1.19, and 1.25 using intrinsic functions for C=A. B, C=A. BT, and C=AT. B, respectively. The performance of using intrinsic functions compared to the inline assembly demonstrates that the intrinsic functions has better performance than inline assembly by 2.1, 2.13, and 2.18 using Intel compiler and by 2.08, 2.49, and 2.11 using MSVC++ compiler for C=A. B, C=A. BT, and C=AT. B, respectively.

Onboard Robust Visual Tracking for UAVs Using a Reliable Global-Local Object Model.

In this paper, we present a novel onboard robust visual algorithm for long-term arbitrary 2D and 3D object tracking using a reliable global-local object model for unmanned aerial vehicle (UAV) applications, e.g., autonomous tracking and chasing a moving target. The first main approach in this novel algorithm is the use of a global matching and local tracking approach. In other words, the algorithm initially finds feature correspondences in a way that an improved binary descriptor is developed for global feature matching and an iterative Lucas–Kanade optical flow algorithm is employed for local feature tracking. The second main module is the use of an efficient local geometric filter (LGF), which handles outlier feature correspondences based on a new forward-backward pairwise dissimilarity measure, thereby maintaining pairwise geometric consistency. In the proposed LGF module, a hierarchical agglomerative clustering, i.e., bottom-up aggregation, is applied using an effective single-link method. The third proposed module is a heuristic local outlier factor (to the best of our knowledge, it is utilized for the first time to deal with outlier features in a visual tracking application), which further maximizes the representation of the target object in which we formulate outlier feature detection as a binary classification problem with the output features of the LGF module. Extensive UAV flight experiments show that the proposed visual tracker achieves real-time frame rates of more than thirty-five frames per second on an i7 processor with 640 × 512 image resolution and outperforms the most popular state-of-the-art trackers favorably in terms of robustness, efficiency and accuracy.

Efficient deterministic and non-deterministic pseudorandom number generation

A high performance and high quality pseudorandom number generator is presented in this paper. It takes less than one clock cycle to generate a pseudorandom byte on an Intel core i3 processor and passes all the 6 TestU01 batteries of tests. The generator can work in either deterministic mode or non-deterministic mode. When working in deterministic mode, it can be used for high speed data encryption and in other applications that require deterministic and reproducible pseudorandom sequences. When working in non-deterministic mode, the generator behaves much like a true random number generator, but with the advantages of low cost, high performance, and general availability. It is good for many applications that currently rely on true random number generators

Computing an unevenness field from 3D laser range data to obtain traversable region around a mobile robot

We introduce a novel measure of terrain unevenness, which is computed in terms of ranges of neighbouring laser beams of a 3D laser scanner mounted on a mobile robot. The unevenness so computed over all sampled points forms an unevenness field around the robot. We explore the nature of this measure of unevenness through analysis, and arrive at a reasonable policy for setting thresholds on unevenness in order to detect obstacles, and in the process mark out the traversable region around the mobile robot. The traversable region is obtained as a connectivity graph over 180×32 cells in about 30 ms time on an Intel i3 processor. This connectivity graph can be potentially used for path planning of the mobile robot. Conceptually and computationally the measure is simple and efficient. It has an added advantage of being robust against small tilts of the sensor during locomotion. It also works well on slopes. Although there are numerous ways of detecting traversable regions in the literature, it is the novelty of the measure and its analysis, which we believe is our contribution through this paper. We demonstrate its usefulness through experimental results and compare its performance with a standard method that uses both height and slope between neighbouring range points to detect obstacles.