Hysteretic Buck Research Articles

A Power-Efficient 1–2-MHz Hysteretic Buck Converter With High DVS Rate Enabled by Isosceles-Triangular Shunt Current Push–Pull Technique

This letter presents a DC-DC buck converter featuring rapid dynamic voltage scaling (DVS) speed without sacrificing efficiency. The proposed isosceles-triangular shunt current (ITSC) push-pull technique allows an arithmetically-simplified turningpoint voltage for optimal DVS to be independent of passive components while supplying a sufficient current of 35 A/μs. Currenttailing handover (CTH), also presented in this work, can realize no voltage droop after DVS even under resistive loads. Combining ITSC and CTH aids in enhancing load-transient response. The chip fabricated in a 180-nm CMOS operates at the slow switching frequency of 1–2 MHz, offering a peak efficiency of 97.6%. A high DVS rate of 7 V/μs, enabled by the proposed ITSC, is measured.

A 40nm CMOS Hysteretic Buck DC-DC Converter With Digital-Controlled Power-Driving-Tracked-Duration Current Pump

A fast-transient voltage-mode hysteretic buck converter with digital-controlled power-driving-tracked-duration (PDTD) auxiliary current pump is proposed. The pump injection current duration is digitally controlled by the driving signal of the power stage. It aims at enhancing the transient response time which is limited by the large inductor used in typical buck converters and reducing the multiple undershoot/overshoot effect encountered in conventional current pump injection technique. The converter has been fabricated using TSMC 40nm CMOS technology with the silicon area of $830\mu \text{m}\times 620\mu \text{m}$ . The proposed converter regulates properly in both Continuous Conduction Mode (CCM) and Discontinuous Conduction Mode (DCM). The measured output ripple is about 30mVpk and the switching frequency is about 1.45MHz. The peak efficiency is 93%. The measured load transient settling time for a 60-to-300mA/300-to-60mA load step change is 369ns/335ns, resulting in 350% faster than that of conventional counterpart without PDTD control scheme. The performance comparison with the representative state-of-art works has shown that the proposed converter shows good balance on performance metrics and the best figure-of-merit (FOM) in transient-response efficiency.

A Current-Mode Hysteretic Buck Converter With Multiple-Reset RC-Based Inductor Current Sensor

A current-mode hysteretic buck converter is described in which inductor current is sensed by a resistor-capacitor (RC) network. The inductor current sensing RC network is reset multiple times per switching clock period, which allows it to have time constant much smaller than switching clock period and therefore occupy small silicon area. A frequency regulator ensures the switching frequency to be constant regardless of the operating condition of the buck converter and also integrates comparator delay compensator as its loop filter. The current-mode hysteretic buck converter implemented in a 65 nm complementary metal-oxide-semiconductor (CMOS) process provides 0.6–2.0 V output from 3.3 V input with 1 MHz switching frequency. The maximum load current is 1.5 A and the measured peak power efficiency is 96.3%.

A Quasi-V2 Hysteretic Buck Converter With Adaptive COT Control for Fast DVS and Load-Transient Response in RF Applications

This brief proposes a buck converter with adaptive constant on time (ACOT) control, including transient-enhanced technique for fast dynamic voltage scaling (DVS) and load-transient response in RF applications. The proposed ACOT control achieves high performance in DVS tracking response to shorten up-tracking time and down-tracking time. Moreover, the high bandwidth transient-enhanced technique in ACOT control improves load-transient response suffering from low bandwidth compensation loop. In addition, the proposed buck converter operates at 2.5 MHz for high power density and 90.1% peak efficiency. This brief is implemented by TSMC 0.18 $\mu \text{m}$ 1P6M CMOS technology with a chip area 1.81 mm2. Measurement results achieve that the output voltage have both 0.6 $\mu \text{s}$ and 0.6 $\mu \text{s}$ recovery time in 600 mA step-up load and 600 mA step-down load, respectively. For 0.6 V step, the output voltage have both 2 $\mu \text{s}$ in up-tracking time and down-tracking time.

A Current-Mode Delay-Based Hysteretic Buck Regulator With Enhanced Efficiency at Ultra-Light Loads for Low-Power Microcontrollers

A current-mode buck regulator with delay-based hysteretic control for microcontroller applications is proposed. Unlike conventional hysteretic buck regulators with accurate explicit hysteretic bands, the proposed design relies only on the inherent delay of a low-speed single-threshold comparator to realize the hysteretic band, and can be seamlessly used across all loads in continuous conduction mode and discontinuous conduction mode without modifying the controller's parameters. Moreover, without additional adaptation circuits or frequency regulation loops, the proposed delay-based hysteretic operation does not increase variations in the switching frequency with process and temperature, and results in even less variations in the switching frequency with the input and output voltages when compared to corresponding designs with accurate explicit hysteretic bands. The simplicity of the design reduces silicon area and quiescent current significantly, which in turns enables achieving high efficiency at both heavy and light load conditions as strictly required by low-power microcontrollers. The regulator is designed in a 65 nm digital CMOS technology. It occupies 0.18 mm2 and supports a wide range of input voltages (1.8–4.2 V), output voltages (0.9–1.5 V), and load current (up to 300 mA). Measurement results show that the proposed regulator achieves 95% peak efficiency, while achieving between 62% and 87% efficiency at 10-μA load across all operating conditions.

Fixed‐frequency hysteretic buck converter with novel adaptive window control and transient response improvement

This study presents a fixed-frequency hysteretic buck converter designed and fabricated using 0.18-µm complementary metal–oxide–semiconductor process. With a phase-locked loop (PLL)-based adaptive window control, the proposed buck converter can achieve a fixed switching frequency, and this frequency can be tuned within a certain range through a reference clock frequency. Concurrently, a novel auxiliary circuit is proposed to monitor the converter's output loading dynamics to reduce the converter's transient recovery time. It will also help to regulate the output voltage at the steady-state operation as well. With the supply voltage ranging from 3 to 4.2 V and an output voltage of 1.8 V, the simulated switching frequency is maintained at 10 MHz because of the PLL control. The transient response time is only 0.3 and 0.4 µs for a 400 mA step-up load and step-down load, respectively.

A 96.5% Efficiency Current Mode Hysteretic Buck Converter With 1.2% Error Auto-Selectable Frequency Locking

This paper proposes a current mode hysteretic buck converter with auto-selectable frequency locking. In this work, the hysteresis of the hysteretic comparator and the resistance of the feedback network are adjusted simultaneously to fix the switching frequency. The proposed switching frequency locking scheme can improve the power efficiency and fix the spectral components of the output at specific frequencies by suitably lowering the switching frequency under light load conditions. Implemented in a 65 nm complementary metal oxide semiconductor (CMOS), the proposed converter achieves peak efficiency of 96.5% for a 3.3 V input with less than 1.2% frequency error while locking at 1, 0.5, and 0.25 MHz.

A Hysteretic Buck Converter With 92.1% Maximum Efficiency Designed for Ultra-Low Power and Fast Wake-Up SoC Applications

This paper presents a dc–dc converter for integration in the power management unit of an ultra-low power microcontroller. The converter is designed to significantly reduce the wake-up energy and startup delay of the supplied core. The use of a minimized output capacitor is the key factor to save the wake-up energy. The converter is buffered with only 56 nF and guarantees a stable output of 1.2 V with a voltage ripple smaller than 30 mV. The controller of the proposed dc–dc converter is based on a predictive peak current control that allows the system to control the energy transfer at extremely low power consumption. The proposed circuit is implemented in 130-nm CMOS technology with an area of only 0.14 mm2. It achieves a high conversion efficiency of 92.1% and a small quiescent current of 440 nA. It operates from 1.8 to 3.3 V with a maximum load of 2.65 mA.

Current-Mode Hysteretic Buck Converter With Spur-Free Control for Variable Switching Noise Mitigation

This paper proposes a current-mode hysteretic buck converter with a spur-free constant-cycle frequency-hopping controller that fully eliminates spurs from the switching noise spectrum irrespective of variations in the switching frequency and operating conditions. As a result, the need for frequency regulation loops to ensure nonvarying switching frequency (i.e., fixed spurs location) in hysteretic controllers is eliminated. Moreover, compared to frequency regulation loops, the proposed converter offers the advantage of eliminating mixing and interference altogether due to its spur-free operation, and thus, it can be used to power, or to be integrated within noise-sensitive systems while benefiting from the superior dynamic performance of its hysteretic operation. The proposed converter uses dual-sided hysteretic band modulation to eliminate the inductor current imbalance that results from frequency hopping along with the output voltage transients and low-frequency noise floor peaking associated with it. Moreover, a feedforward adaptive hysteretic band controller is proposed to reduce variations in the switching frequency with the input voltage, and an all-digital soft-startup circuit is proposed to control the in-rush current without requiring any off-chip components. The converter is implemented in a 0.35- μ m standard CMOS technology and it achieves 92% peak efficiency.

A 6 A, 93% Peak Efficiency, 4-Phase Digitally Synchronized Hysteretic Buck Converter With ±1.5% Frequency and ±3.6% Current-Sharing Error

A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc–dc converter achieves 93% peak efficiency for $V_{i}= 2$ V and $V_{o}= 1.6$ V.

주파수 전압 변환을 이용한 듀얼 모드 벅 변환기 모드 제어 설계

본 논문은 넓은 부하 전류를 요구하는 휴대 기기에서 사용될 목적으로 주파수 전압 변환을 이용하여 모드 제어 가능한 듀얼 모드 벅 변환기를 설명한다. 기존의 히스테스테릭 벅 변환기의 문제인 저 부하에서의 PLL 보상 및 효율 저하를 제안하는 듀얼 벅 변환기의 개선된 PFM 모드를 통해 해결한다. 또한 기존의 듀얼 모드 벅 변환기의 주요 회로인 모드 제어기에서의 부하 변화 감지의 어려움과 느린 모드 전환 속도를 제안하는 모드 제어기로 개선 시킨다. 제안하는 모드 제어기는 최소 1.5us의 모드 전환 시간을 가진다. 제안하는 DC-DC 벅 변환기는 <TEX>$0.18{\mu}m$</TEX> CMOS 공정에서 설계하였으며 칩 면적은 <TEX>$1.38mm{\times}1.37mm$</TEX>이다. 기생 소자를 포함한 인덕터와 커패시터를 고려한 후 모의실험 결과는 1~500mA의 부하 전류 범위에서 입력 전압을 2.7~3.3V를 가지며 PFM 모드는 65mV이내, 히스테리틱 모드에서는 고정된 스위칭 주파수 상태에서 16mV의 출력 리플 전압을 가지는 1.2V의 출력 전압을 생성한다. 제안하는 듀얼 모드 벅 변환기의 최대 효율은 80mA에서 95%를 나타내며 해당 전체 부하 범위에서 85% 이상의 효율을 지닌다. This paper describes a Dual Buck Converter with mode control using variable Frequency to Voltage for portable devices requiring wide load current. The inherent problems of PLL compensation and efficiency degradation in light load current that the conventional hysteretic buck converter has faced have been resolved by using the proposed Dual buck converter which include improved PFM Mode not to require compensation. The proposed mode controller can also improve the difficulty of detecting the load change of the mode controller, which is the main circuit of the conventional dual mode buck converter, and the slow mode switching speed. the proposed mode controller has mode switching time of at least 1.5us. The proposed DC-DC buck converter was implemented by using <TEX>$0.18{\mu}m$</TEX> CMOS process and die size was <TEX>$1.38mm{\times}1.37mm$</TEX>. The post simulation results with inductor and capacitor including parasitic elements showed that the proposed circuit received the input of 2.7~3.3V and generated output of 1.2V with the output ripple voltage had the PFM mode of 65mV and 16mV at the fixed switching frequency of 2MHz in hysteretic mode under load currents of 1~500mA. The maximum efficiency of the proposed dual-mode buck converter is 95% at 80mA and is more than 85% efficient under load currents of 1~500mA.

A 95 nA quiescent current hysteretic mode buck converter with sample and hold reference

A nano ampere (nA) hysteretic mode buck converter is presented in this paper. Nano ampere current sleep phase and fast response burst phase are implemented. The converter achieves nano-watt power consumption in sleep phase while ensures fast wake-up from sleep phase to burst phase. New developed ultra low power sample-hold voltage reference and 1 kHz oscillator draw currents of 20 and 10 nA respectively. The circuit was implemented in a 0.35 μm CMOS process. The measurement result shows that the converter's quiescent current (Iq) in sleep phase is as low as 95 nA. Benefit from the ultra-low Iq, the circuit achieves conversion efficiency of 79.8% at 2 μA load, regulating output at 2.5 V with a 3.6 V supply. The peak efficiency is up to 94% at 50 mA load.

Ultra-fast Adaptive Frequency-controlled Hysteretic Buck Converter for Portable Devices

The paper describes a hysteretic buck converter including a differentiator and an adaptive hysteresis window controller. Differentiating the feedback signal achieves ultra-fast switching of the buck converter. The adaptive hysteresis window control allows a monotonous operation with predictable noise spectrum, and gives way to efficient design for variable supply and output voltages. The measurement results in a 0.13-μm CMOS process indicated that the switching frequency became double times higher, and the voltage ripple was reduced by up to 69%. They also indicated that the normalized switching frequency variation was reduced by 74% with variable V DD and by 63% with variable V OUT . The power efficiency was improved by 3.5% depending on loading condition.

A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit

This paper proposes a monolithic capacitor-current-controlled hysteretic buck converter with a transient-optimized feedback circuit (TOFC) for compact-sized portable devices. The proposed TOFC simultaneously optimizes both load and dynamic voltage scaling (DVS) transient responses to minimize output voltage undershoot/overshoot and settling time. In addition, a transient-hold (TH) technique, which prevents transient response optimization from being affected by the error amplifier without increasing the compensation capacitance, is also proposed to save chip area. This work is implemented in a 0.35 μm CMOS process with a chip area of 0.88 mm 2 . Measurement results show that, for a 500 mA load transient, the output voltage settles in 0.9 μs with an undershoot/overshoot of less than 35 mV. For a 0.6-V DVS transient, output voltage settles in 3 μs with negligible undershoot/overshoot. Moreover, 96% peak efficiency is measured at 500 mW output power.

A Fixed-Frequency Quasi-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;${\rm V}^{2}$&lt;/tex&gt;&lt;/formula&gt; Hysteretic Buck Converter With PLL-Based Two-Stage Adaptive Window Control

This paper proposes a fast transient quasi- ${\rm V}^{2}$ fixed-frequency hysteretic buck converter designed and fabricated using TSMC 2P4M 0.35- $\mu{\rm m}$ CMOS process. The proposed converter can achieve fixed frequency switching through a novel phase-locked-loop-based two-stage adaptive window control. Under ultralight load conditions, the proposed converter operates in a pulse frequency modulation mode to reduce the switching loss and improve light load efficiency. A quasi- ${\rm V}^{2}$ technique is applied for obtaining inductor current information without relying on an output capacitor with a high equivalent series resistance; therefore, the output voltage ripple can be reduced. The experimental results show that the proposed converter can operate at a load current ranging from 18 to 700 mA, a supply voltage ranging from 2.7 to 4.2 V, and an output voltage of 1.2 V. The off-chip inductor and output capacitor are 2.2 $\mu{\rm H}$ and 10 $\mu{\rm F}$ , respectively. Through the PLL control, the switching frequency is maintained at 1 MHz. The transient response time is approximately 5 $\mu{\rm s}$ , and the highest efficiency registered is 95.6%.

A CMOS Hysteretic DC-DC Buck Converter with a Constant Switching Frequency

This paper describes a CMOS hysteretic DC-DC buck converter with a constant switching frequency for mobile applications. The inherent problems of a large output ripple voltage that the conventional hysteretic DC-DC buck converters has faced have been resolved by using the proposed DCDC buck converter which employed a ramp generator circuit to be able to increase a switching frequency. The proposed architecture enables the settling response time of charge pump circuit within the converter to become less than 6us suitable for mobile applications. The proposed DC-DC buck converter was implemented by using 0.35 um BCDMOS process and die size was 1.37 mm x 1.37 mm. The measurement results showed that the proposed circuit received the input of 3.7 V and generated output of 1.2 V with the output ripple voltages less than 20 mV under load currents of 100~400 mA at the fixed switching frequency of 2 MHz. The maximum efficiency of the proposed hysteretic buck converter was measured to be around 93%.

작은 출력 전압 리플과 연속 전도모드에서 고정된 스위칭 주파수를 가지는 히스테리틱 벅 변환기 설계

An efficient fast response hysteretic buck converter suitable for mobile application is propoesed. The problems of large output ripple and difficulty in using of small power inductor that conventional hysteretic converter has are improved by adding ramp generator. and the changeable switching frequency with load current is fixed by adding a delay time control circuit composed of PLL structure resulting in decrease of EMI noise. The circuits are implemented by using BCDMOS 0.35um 2-polt 4-metal process. Measurement results show that the converter operates with a switching frequency of 1.85MHz when drives 80mA load current. As the converter drives over 170mA load current, the switching frequency is fixed on 2MHz. The converter has output ripple voltage of less 20mV and more than efficiency 85% with 50~500mA laod current condition.

Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications

An integrated DC-DC hysteretic buck converter with ultrafast adaptive output transient response for reference tracking is presented. To achieve the fastest up-tracking speed, the maximum charging current control is introduced to charge up the output voltage with the maximum designed current. For down-tracking, the output is discharged by the load only to save energy. Although the converter works with hysteretic voltage mode control, an adaptive delay compensation scheme is employed to keep the switching frequency constant at 850 kHz to within plusmn2.5% across the whole operation range. The integrated buck converter was fabricated using a 0.35 mum CMOS process. With an input voltage of 3 V, the output voltage can be regulated between 0.5 and 2.5 V. With a load resistor of 10 Omega, the up-tracking speed of the maximum reference step (0.5 to 2.5 V) is 12.5 mus/V. All design features are verified by extensive measurements.