Hysteresis Dispersion Research Articles

Effect of temperature on the hysteresis phenomenon and dispersion regimes for alumina/water based nanofluids

The present paper deals with a comprehensive experimental study of the hysteresis phenomenon of alumina-water based nanofluids taking place during heating-cooling cycles. The emphasis was particularly put on the relationship between this phenomenon and the dispersion state of alumina nanoparticles. Thus, by carrying out simultaneous thermal conductivity and dynamic viscosity measurements, five dispersion regimes were highlighted. The influence of the temperature on these two properties as well as the pH of the solution was then investigated for six characteristic conditions in the well-dispersed and chain-like agglomerated regimes and for temperatures between 20 and 80 °C. The results evidenced that as long as the temperature, and as a consequence the pH, does not exceed a critical value, no hysteresis phenomenon occurs during the heating and cooling processes. Eventually, it was found out that this critical temperature is strongly dependent on the dispersion regime and the initial pH of the nanofluid.

Comparison of control strategies for hysteresis attenuation in electromechanical actuators subject to dispersion

This paper addresses the difficulties of designing highly efficient robust controllers for a class of systems exhibiting high hysteresis with parameters dispersion that limits control accuracy and performance homogeneity over the parametric uncertainties range. Two control strategies to solve the problem are assessed. First, a Reference Model Sliding Mode Control (RMSMC) feedback controller known to be robust to parametric uncertainty is designed to compensate hysteresis, regardless of the hysteresis quantity. Secondly, a strategy based on a feedforward controller with a Neural Network inverse model and a PID feedback controller is proposed. In this case, hysteresis dispersion is addressed through the integration of a backlash estimator for computing the Neural Network inverse model. The control strategies are implemented for position control of a Limited-Angle Torque Motor (LATM) exhibiting uncertain hysteresis. Experimental tests demonstrated the very good accuracy and robustness of the Neural Network inverse model and the PID controller for position tracking when the LATM is subject to dispersion and the benefits of the Reference Model Sliding Mode Control (RMSMC) feedback controller for the rejection of external disturbances.

Degradation of NO-nitrided SiC MOS interfaces by excimer ultraviolet light irradiation

The impact of excimer ultraviolet (UV) light irradiation on SiO2/SiC(0001) and (112̄0) interfaces was examined to get insight into the effect of NO nitridation. While NO nitridation appears to be effective in passivating the electron traps at the SiO2/SiC interfaces, we found that the nitridation induces additional traps that are not active until UV light is irradiated. The traps include those causing hysteresis and frequency dispersion in the C–V characteristics and those affecting the long-term reliability of MOS devices. A non-nitrided SiO2/SiC interface was less sensitive to UV light, indicating the instability of the nitrided SiC MOS structure.

Insight into interface electrical properties of metal–oxide–semiconductor structures fabricated on Mg-implanted GaN activated by ultra-high-pressure annealing

GaN-based metal–oxide–semiconductor (MOS) devices, such as n- and p-type capacitors and inversion- and accumulation-type p-channel field effect transistors (MOSFETs), were fabricated by Mg-ion implantation and ultra-high-pressure annealing (UHPA) under 1-GPa nitrogen pressure. Even though UHPA was conducted at 1400 °C without protective layers on GaN surfaces, n-type MOS capacitors with SiO2 gate dielectrics formed on non-ion-implanted regions exhibited well-behaved capacitance–voltage characteristics with negligible hysteresis and frequency dispersion, indicating distinct impact of UHPA in suppressing surface degradation during high-temperature annealing. Efficient activation of the implanted Mg dopants and reasonable hole accumulation at the SiO2/GaN interfaces were also achieved for p-type capacitors by UHPA, but the fabricated inversion- and accumulation-type p-channel GaN MOSFETs were hardly turned on. The findings reveal extremely low hole mobility at GaN MOS interfaces and suggest an intrinsic obstacle for the development of GaN-based MOS devices.

A method for estimating defects in ferroelectric thin film MOSCAPs

We propose a capacitance measurement scheme that enables quantitative characterization of ferroelectric thin films integrated on semiconductors. The film defect density is estimated by measurements of the CV hysteresis and frequency dispersion, whereas important device parameters such as memory window and endurance can be extracted by a unidirectional CV method. The simple measurement scheme and the usage of metal-oxide-semiconductor capacitors rather than MOSFETs make the proposed methods suitable for the future optimization of ferroelectric field effect transistor and negative capacitance field effect transistor gate stacks. Specifically, we present data for the narrow bandgap semiconductor InAs and show that low temperature characterization is critical to reduce the influence of the minority carrier response; however, the methods should be transferrable to room temperature for semiconductors with a wider bandgap. Our results clearly indicate that the defect density of the HfxZr1−xO2 (HZO) films increases at the crystallization temperature, but the increase is modest and remains independent of the annealing temperature at even more elevated temperatures. It is also shown that the shrinkage of the memory window caused by field cycling is not accompanied by an increase in defect density.

Correlating device behaviors with semiconductor lattice damage at MOS interface by comparing plasma-etching and regrown recessed-gate Al2O3/GaN MOS-FETs

We correlate electical behaviors of recessed-gate Al2O3/GaN MOS-FETs with the lattice damage at MOS interface region by directly comparing plasma-etching (inductively coupled plasma, ICP) and regrown (selective-area-growth, SAG) methods. Firstly the regrown AlGaN/GaN heterostructure are evaluated, showing high crystal quality and good 2DEG transport properties and reaching the level of as-grown one. Then based on the as-grown and regrown heterostructures, ICP and SAG E-mode MOS-FETs were fabricated, respectively. ICP MOS-FET suffers from negative shift of Vth, leaky gate current, large Vth hysteresis and current dispersion, while SAG MOS-FET demonstrates stable and nondegradating device performances. Compared to SAG MOS interface, high interface-traps-density is deduced in ICP MOS interface which causes serious electron trapping effects. These traps are found to be related to the lattice damage of plasma-etching GaN accompanying a rough and disorder surface morphology and the increase of nitrogen-vacancy and GaO bonds, responsible for the degenerated device behaviors. Step-flow surface morphology is preserved for SAG sample, which results in the high-quality MOS interface. The results reveal the impacts of lattice damage at MOS interface on GaN device behaviors and also provide a pathway to settle them down.

Hysteresis Dispersion Compensation with Neural Network based Controller

Hysteresis is a commonly encountered physical phenomenon in many systems. It results in a dependence of the state of a system to its history. This non-linearity makes it particularly difficult to control accurately. There are many ways for compensating hysteresis, one of them consists of building an inverse model of the hysteresis and using it as a feedforward controller. Coupled to a feedback mechanism, the hysteresis impact can thus be minimized. However, the performance of these controllers decreases when exposed to dispersion in the hysteresis quantity or shape. The capacity of neural networks to model non-linear phenomena is not to be proven and will be put at use. In this paper, an artificial neural network model was trained to replace the conventional hysteresis inverse model. The controller performance was evaluated on a limited-angle torque motor, which exhibits hysteresis due to the magnetization saturation of the ferromagnetic materials. The experimental results pointed out the superior robustness to system dispersion of the Neural Network based controller for time and frequency response.

Facile Process for Surface Passivation Using (NH4)2S for the InP MOS Capacitor with ALD Al2O3.

Ammonium sulfide ((NH4)2S) was used for the passivation of an InP (100) substrate and its conditions were optimized. The capacitance–voltage (C–V) characteristics of InP metal-oxide-semiconductor (MOS) capacitors were analyzed by changing the concentration of and treatment time with (NH4)2S. It was found that a 10% (NH4)2S treatment for 10 min exhibits the best electrical properties in terms of hysteresis and frequency dispersions in the depletion or accumulation mode. After the InP substrate was passivated by the optimized (NH4)2S, the results of x-ray photoelectron spectroscopy (XPS) and the extracted interface trap density (Dit) proved that the growth of native oxide was suppressed.

Improved dielectric properties of BeO thin films grown by plasma enhanced atomic layer deposition

Beryllium oxide (BeO) thin films were grown on a p-type Si substrate by plasma enhanced atomic layer deposition (PEALD) using diethylberyllium as a precursor and O2 plasma. The PEALD BeO exhibited self-saturation and linear growth rates. The dielectric properties of PEALD were compared with those of thermal atomic layer deposition (ThALD). X-ray photoelectron spectroscopy was performed to determine the bandgap energy of PEALD BeO (8.0 eV) and ThALD BeO (7.9 eV). Capacitance–voltage curves revealed that PEALD BeO had low hysteresis and frequency dispersion compared to ThALD BeO. In addition, PEALD showed a dielectric constant of 7.15 (at 1 MHz) and low leakage current (7.25×10-9 A/cm2 at −1 MV/cm). These results indicate that the highly activated radicals from oxygen plasma prompt the chemical reaction at the substrate, thus reducing nucleation delay and interface trap density.

Characteristics of Al2O3/native oxide/n-GaN capacitors by post-metallization annealing

This work investigated characteristics of Al2O3/native oxide/n-GaN MOS capacitors by post-metallization annealing (PMA). A native oxide interlayer which composed of ε- and γ-Ga2O3 phases (Native oxide) and the reduced amount of one (Reduced) on n-GaN were prepared by cleaning only a sulfuric acid peroxide mixture (SPM) and both SPM and buffered hydrofluoric acid, respectively. The effect of trimethylaluminum precursor on removal of a native oxide layer was not observed during Al2O3 deposition using atomic layer deposition. An as-grown capacitor (Native oxide) exhibited a small flatband voltage (Vfb) hysteresis of ∼30 mV and a large frequency dispersion, suggesting that the initial growth of the Al2O3 resulted in the formation of electrical defects on the GaN surface. Both the Vfb hysteresis and frequency dispersion were drastically improved by PMA of the device at 300 °C. The positive fixed charge values (QIL) estimated from the relationships between capacitance equivalent thickness and Vfb were +6.1 × 1012 and +0.4–1.0 × 1012 cm−2 for as-grown and PMA-processed capacitors in the PMA temperature range of 300 °C–600 °C, respectively. The interface state density (Dit) determined using a conductance method was also significantly reduced (by an order of magnitude) after PMA processing at 300 °C. These trends in the QIL and Dit data were observed in both the Native oxide and Reduced capacitors, indicating that this interlayer does not greatly affect fixed charge generation at the Al2O3/native oxide and Al2O3/modified native oxide interfaces. As a result, two types of treatments result in insignificant difference in the electrical properties of the capacitors.

Lack of correlation between C-V hysteresis and capacitance frequency dispersion in accumulation of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks

The correlation between capacitance-voltage hysteresis and accumulation capacitance frequency dispersion of metal gate/high-k/n-InGaAs metal-oxide-semiconductor stacks is experimentally assessed. Samples fabricated employing forming gas annealing (FGA) or substrate air exposure to obtain different densities of defects were thoroughly characterized and the results were compared with previous literature on the topic. Results indicate a lack of correlation between capacitance-voltage hysteresis and accumulation capacitance dispersion with frequency, suggesting that defects with remarkably different kinetics are involved in each phenomenon. This is assessed through the dependence of the capacitance-voltage hysteresis with DC bias and stress time, observing that permanent interface defect depassivation under bias has no effect on the hysteresis width after stress. Overall, capacitance-voltage hysteresis probes slow trapping mechanisms throughout the oxide and the bandgap, which are consistent with the negative charge trapping characteristic of the current-time curves for FGA samples at constant voltage stress. Instead, accumulation capacitance frequency dispersion probes defects with short trapping/detrapping characteristic times that can be linked to the stress induced leakage current of air exposed samples under constant DC stress. Experimental results indicate that each effect must be assessed separately due to the large difference in the kinetics of the probed defects.

Effect of high-pressure deuterium annealing with high-κ stack onto In0.53Ga0.47As MOS capacitors on 300 mm Si substrate

In this paper, we studied the passivation effects of deuterium (D2) high-pressure annealing (HPA) on In0.53Ga0.47As MOS capacitors (MOSCAPs) on 300 mm Si substrate. We found that D2 HPA is effective in improving capacitance–voltage (C–V) characteristics of the In0.53Ga0.47As MOSCAPs. A significant improvement in C–V hysteresis and frequency dispersion is observed, and, more importantly, the value of the interface trap density (Dit) considerably decreases when using the D2 HPA. In addition, we explored the impact of HPA under other ambient conditions, such as H2 HPA. The D2 HPA yields better C–V characteristics and lower Dit in In0.53Ga0.47As MOSCAPs than H2 HPA. Our findings in this work indicate that D2 HPA would be an effective remedy to further passivate the interface quality between the gate dielectric and the In0.53Ga0.47As channel in III–V MOSFETs.

(Invited) Gate Stack Technology for Advanced GaN-Based Mos Devices

GaN-based power devices have received much attention for their application in the next-generation high-frequency and high-power devices. Recently, AlGaN/GaN heterojunction field-effect transistors (HFETs) with Schottky gate structures have been implemented into modern wireless communication systems. However, their applications are restricted because of large gate leakage current through the Schottky contacts and their normally-on operation. To overcome these limitations, MOS gate stacks on GaN-based materials have been intensively studied. Moreover, normally-off vertical power MOSFETs on free-standing GaN substrates have become a hot topic in power electronics. In contrast with the Si-based semiconductors, deposition of wide bandgap insulators on the AlGaN and GaN surfaces is thought to be a plausible method for fabricating MOS gate stacks. Among the various insulating materials, Al2O3 and SiO2 exhibit a sufficiently wide bandgap and thermal stability for MOS device applications. However, it is well known that Al2O3 involves an essential problem of electron trapping, thus leading to significant Id-Vg hysteresis and Vth instability. In addition, poor electrical properties of GaN-based MOS devices have been reported even for the well-established ALD-Al2O3 and CVD-SiO2 films. We have investigated suitable insulating materials and deposition methods for AlGaN/GaN MOS-HFETs and GaN-MOSFETs. This paper reviews our recent findings on gate stack engineering for advanced GaN-based MOS devices and discusses a common guiding principle to improve device performance and reliability. We implemented nitrogen incorporated Al2O3 (AlON) gate dielectrics into the AlGaN/GaN MOS-HFETs and successfully improved the performance and reliability of the devices. Our physical and electrical characterizations revealed superior thermal stability of the AlON/AlGaN interface and the importance of conducting dielectric deposition under a reactive nitric atmosphere to suppress intermixing at the interface. Recently, we demonstrated high current and high voltage (20A/730V) normally-off AlGaN/GaN MOS-HFETs with the AlON gate dielectrics. For fabricating GaN-MOS structures, oxidation of the GaN surface is a fundamental method of obtaining gate insulators, but severe drawbacks, such as insufficient conduction band offset at GaOx/GaN interfaces and rough surface morphology have been pointed out. Thus, we proposed GaN-MOS structures with thin GaOx interlayers, in which oxide interlayers were formed by oxidation of GaN surface prior to SiO2 deposition. We also found that high-quality SiO2/GaOx/GaN stacked structures were formed by optimizing conditions for plasma-enhanced CVD of SiO2 films. Consequently, well-behaved C-V curves with negligible hysteresis and frequency dispersion were obtained. Moreover, an extremely low interface state density (< 1010 cm-2eV-1) and an improved reliability in terms of reproducibility and robustness against dielectric breakdown were achieved by rapid thermal annealing of SiO2/GaOx/GaN MOS devices.

Interface trap characterization of Al2O3/GaN vertical-type MOS capacitors on GaN substrate with surface treatments

We report on the interface trap properties Al2O3/GaN vertical-type metal-oxide-semiconductor (MOS) capacitors homogeneously grown on GaN substrates with different surface treatments. The electrical and microstructure characteristics are analyzed with regard to the behaviors and natures of different trap states at and close to the MOS interface. It is shown that only acid cleaning could not effectively suppress the interface traps, while a following (NH4)2S passivation drastically reduce the interface state density to the detection limit of ∼1011 cm−2eV−1. At the same time, border traps and fixed charges located close to the MOS interface are also suppressed, leading to a neglecting electrical hysteresis and frequency dispersion in the capacitance-voltage measurement.

A transient simulation approach to obtaining capacitance–voltage characteristics of GaN MOS capacitors with deep-level traps

In this study, GaN MOS capacitance–voltage device simulations considering various interface and bulk traps are performed in the transient mode. The simulations explain various features of capacitance–voltage curves, such as plateau, hysteresis, and frequency dispersions, which are commonly observed in measurements of GaN MOS capacitors and arise from complicated combinations of interface and bulk deep-level traps. The objective of the present study is to provide a good theoretical tool to understand the physics of various nonideal measured curves.

Ferroelectric system dynamics simulated by a second-order Landau model

By using a second-order time-dependent Ginzburg–Landau model, we simulate the dynamic polarization hysteresis behavior of a ferroelectric system subjected to a sinusoidal electric field. We examine polarization hysteresis loop structure as a function of both field amplitude and field frequency. The relationship between the latter and hysteresis loop area, i.e., hysteresis dispersion, is calculated. Departing from previous work that established that the considered model produces experimentally expected hysteresis dispersion in the low-frequency regime, we demonstrate that (i) this model also produces experimentally expected hysteresis dispersion in the high-frequency regime; (ii) this dispersion implies, in agreement with experimental observations, that system relaxation is characterized by an effective characteristic time which is inversely proportional to field amplitude when the latter is sufficiently high; and (iii) the considered model predicts a symmetry-breaking transition that depends on both field frequency and field amplitude.

Examining the relationship between capacitance-voltage hysteresis and accumulation frequency dispersion in InGaAs metal-oxide-semiconductor structures based on the response to post-metal annealing

In this work, we investigated the effect of forming gas annealing (FGA, 5% H2/95% N2, 250°C to 450°C) on border trap density in high-k/InGaAs metal-oxide-semiconductor (MOS) systems using accumulation frequency dispersion and capacitance-voltage (CV) hysteresis analysis. It is demonstrated that the optimum FGA temperature that reduces the accumulation frequency dispersion is 350°C for HfO2/n-InGaAs and 450°C for Al2O3/n-InGaAs MOS system. Volume density of border traps (Nbt) is estimated using the accumulation frequency dispersion based on a distributed model for border traps. It is shown that for HfO2/n-InGaAs MOS system, Nbt is reduced from 9.4×1019cm−3eV−1 before FGA to 6.3×1019cm−3eV−1 following FGA at 350°C. For the case of Al2O3/n-InGaAs MOS system, Nbt is reduced from 5.7×1019cm−3eV−1 for no FGA to 3.4×1019cm−3eV−1 for FGA at 450°C. Furthermore, it is shown that the most pronounced reduction in border trap density estimated from CV hysteresis analysis is observed at the same optimum FGA temperature that reduces the accumulation frequency dispersion, indicating that these two techniques for border trap analysis are correlated.

Oxide Charge Engineering of Atomic Layer Deposited AlOxNy/Al2O3 Gate Dielectrics: A Path to Enhancement Mode GaN Devices.

Nitrogen incorporation to produce negative fixed charge in Al2O3 gate insulator layers is investigated as a path to achieve enhancement mode GaN device operation. A uniform distribution of nitrogen across the resulting AlOxNy films is obtained using N2 plasma enhanced atomic layer deposition (ALD). The flat band voltage (Vfb) increases to a significantly more positive value with increasing nitrogen concentration. Insertion of a 2 nm thick Al2O3 interlayer greatly decreases the trap density of the insulator/GaN interface, and reduces the voltage hysteresis and frequency dispersion of gate capacitance compared to single-layer AlOxNy gate insulators in GaN MOSCAPs.

Magnetization plateaus and frequency dispersion of hysteresis on frustrated dipolar array

Competings or frustrated interactions are common for condensed matter systems. In consideration of the effect of dipole–dipole interaction, the static properties of square lattice spin systems are investigated using the Wang–Landau algorithm. The dynamic hysteresis is also simulated using the Monte Carlo (MC) method. The step-like magnetization under a DC magnetic field and two distinct peaks in hysteresis dispersion under an AC magnetic field are observed. Then, the formation of the properties of the frustrated dipolar array are discussed.

(Invited) An Investigation of the InGaAs MOS System for Future High Mobility Channel Applications

As silicon devices reach the limit of dimensional scaling there is a growing interest in the use of high electron mobility channels, such as InxGa1-xAs, in conjunction high dielectric constant (high-k) gate oxides for n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) in FinFET structures [1] and in 3D integration schemes [2]. The understanding and control of electrically active defect states at the high-k/InxGa1-xAs interface and of charges within the atomic layer deposited (ALD) high-k films will be essential for the successful implementation of high mobility channel materials in MOSFET or tunnel FET configurations. The objective of this presentation will be to provide an overview of the current understanding of the density and distribution of electrically active defects at the high-k/InGaAs interface and of defect states located in the interfacial oxide transition region which are manifest as accumulation frequency dispersion and capacitance-voltage hysteresis. The presentation will focus on InGaAs with a 53% Indium concentration. The electrically active interface state density distribution is determined from fully fabricated InGaAs MOSFET structures based on the full gate capacitance in conjunction with the Maserjian Y-function and Poisson-Schrodinger simulations [3]. Comparisons to simulations will be discussed in terms of identifying potential candidates for the physical origin of the interface defects. Very significant progress has been made in recent years in the passivation and intrinsic elimination of high-k/In0.53Ga0.47As interface defects to the point where genuine surface inversion for n and p type InGaAs MOS structures can be achieved and this research will be reviewed [4]. The characteristic signatures of capacitance and conductance, which indicate genuine surface inversion for an InGaAs MOS structure in inversion, will also be discussed [5]. While significant attention has been focussed on interface states and fixed charges in the InGaAs MOS system, the issue capacitance-voltage (CV) hysteresis has received relatively little attention to date [4]. This is now becoming a more pressing issue as progress is being made in controlling interface defect levels. Results will be presented covering CV hysteresis for the HfO2/InGaAs and Al2O3/InGaAs MOS structures with a range of high-k oxide thicknesses. The experimental results indicate that the defect states responsible for the hysteresis are located in the oxide transition region near the InGaAs/high-k interface and that engineering of this interface region, which contains native oxides of In, Ga and As, is the key to the control of CV hysteresis and accumulation frequency dispersion [7]. Finally, the presentation will cover the application of CV analysis to the understanding and quantification of charged defect components for InGaAs on insulator structures for 3D integration [8]. The authors acknowledge the financial support of Science Foundation Ireland through the INVENT project (SFI/09/IN.1/I2633) and the EU through the project COMPOSE3 (FP7-ICT- 2013-11-619325). [1] M. Radosavljevic et al., Tech.Dig.-Int. Electron Devices Meet, 126 (2010) [2] L. Czornomaz, et al., Tech.Dig.-Int. Electron Devices Meet. 6479088, (2012) [3] V. Djara, et al., Microelectronic Engineering 109 182–188 (2013) [4] N. Goel, D. et al., Tech. Dig. - Int. Electron Devices Meet. 363, (2008) [5] É. O’Connor, et al., Appl. Phys Lett 99, 212901 (2011) [6] Scott Monaghan, et al., IEEE Transaction on Electron Devices, 61, 4176 (2014) [7] Jun Lin, et al., J. Appl. Phys. 114, 144105 (2013) [8] K. Cherkaoui et al., Microelectronic Engineering 147 63–66 (2015)