Hyper-Threading Technology Research Articles

Proposing Disk Scheduling Algorithm to Enhance the Efficiency of Disk Performance

Management of disk scheduling is a very important aspect of operating system. Disk scheduling involves a careful examination of pending requests to determine the most efficient way to serve these requests. A disk scheduler examines the positional relationship among waiting requests, then reorders the queue so that the requests will be serviced with minimum seek. Performance of the disk scheduling completely depends on how efficient is the scheduling algorithm to allocate services to the request in a better manner. After the arrival of the multi-core processor, the speed of the processors became much faster with the Hyper-Threading technology, and with this the speed of the processors increased dramatically with a record speed. All processers need CPU time and read/write time together to complete their execution. Read/write operations require the operating system to access the disk to store and retrieve data. In the recent years many algorithms (FIFO, SSTF, SCAN, C-SCAN, LOOK, etc.) are developed in order to optimize the system disk I/O performance. The purpose of this study is to obtain a new scheduling algorithm that reduces seek time, sum of head movement, spin time, and transfer time, so as to improve disk performance efficiency in a better way to try to synchronize with CPU performance.

Understanding HTT Architecture and its impact on processor's performance

This paper deals with Hyper-Threading Technology architecture and also architecture design and working of Intel's processor. Hyper- Threading Technology transforms a single physical processor into two logical processors by sharing physical execution resources and duplicating the architecture state for the two logical processors. This means that operating systems and user programs can schedule processes or threads to logical processors in the same way that they would on multiple physical processors. In terms of microarchitecture, this means that instructions from both logical processors will persist and run on shared execution resources at the same time, this technology is bound to get more popular in the future as it introduces a replacement strategy for achieving extra performance while reducing transistor and power costs.

Effect of Hyper-Threading in Latency-Critical Multithreaded Cloud Applications and Utilization Analysis of the Major System Resources

Multithreaded latency-critical applications represent an important subset of workloads running on public cloud systems. Most of these systems deploy powerful computing servers including Intel Hyper-Threading processors. Understanding how performance is affected by the consumption of the main system resources is a major concern for cloud providers in order to devise virtualization strategies that improve the system efficiency. With this aim, this paper first characterizes the impact of QPS on tail latency, analyzing different scenarios varying the number of threads and the thread-to-core allocation (single-task and multi-task execution) policy. The characterization study reveals that the performance of some applications does not scale with the number of threads, and the performance of some others is insensitive to the Hyper-Threading technology, so they can be allocated in less physical cores and improve system utilization. Identifying these applications, however, at run-time is challenging. Despite identifying these applications at run-time is challenging, this paper shows that they can be successfully detected at run-time by analyzing the utilization trend of the major system resources. In addition to CPU, we have also studied how assigning the share of each application of other major shared system resources impacts on performance. We outline considerations cloud providers should take into account to improve performance and resource utilization.

Using hyperthreading technology to increase the processing speed of ML algorithms

Using hyperthreading technology to increase the processing speed of ML algorithms

Design and implementation of an elastic processor with hyperthreading technology and virtualization for elastic server models

The server models functioning in the industry are required to be more elastic in nature. They are constantly scaling-up and scaling-down on required computation power depending on different conditions. These elastic cloud platforms use accelerators like DSP’s, TPU’s, GPU’s, FPGA’s, and multi-core processors to provide exponential computing power and outsource their services. This process is not only costly and non-efficient but is also responsible for damaging the server’s hardware architecture. Furthermore, these additions degrade the level of threading and symmetric parallel processing capability of the architecture. Intel uses hyperthreading technology (HTT) to split the workload between hardware and operating system to avoid additions, but that too is only possible up until a certain limit. This paper presents design methodology and implementation of an elastic-natured 32-bit RISC-pipelined processor inspired from Intel Xeon and MIPS to function as a standard integrated platform for server models. It implements concepts of hyperthreading technology (HTT) and virtualization on hardware basis. It will allow to derive multiple outputs from units on hardware basis to enhance security and performance without compromising compatibility. The designed elastic core uses a probabilistic node-based closed-queuing network model for server analysis and implementation. Hence, elastic behavior from individual core microarchitecture to server model architecture enables a generic automated scaling self-aware optimization architecture.

Multi-Core Processors: Concepts and Implementations

This research paper aims at comparing two multi-core processors machines, the Intel core i7-4960X processor (Ivy Bridge E) and the AMD Phenom II X6. It starts by introducing a single-core processor machine to motivate the need for multi-core processors. Then, it explains the multi-core processor machine and the issues that rises in implementing them. It also provides a real life example machines such as TILEPro64 and Epiphany-IV 64-core 28nm Microprocessor (E64G401). The methodology that was used in comparing the Intel core i7 and AMD phenom II processors starts by explaining how processors' performance are measured, then by listing the most important and relevant technical specification to the comparison. After that, running the comparison by using different metrics such as power, the use of Hyper-Threading technology, the operating frequency, the use of AES encryption and decryption, and the different characteristics of cache memory such as the size, classification, and its memory controller. Finally, reaching to a roughly decision about which one of them has a better over all performance.

Parallel real-world LU decomposition: Gauss vs. Crout algorithm

Abstract This paper presents numerical experiments with assorted versions of parallel LU matrix decomposition algorithms (Gauss and Crout algorithm). The tests have been carried out on the hardware platform with fourcore Skylake processor featuring hyperthreading technology doubling virtually core number. Parallelization algorithms have been implemented with the aid of classic POSIX threads library. Experiments have shown that basic 4-thread acceleration of all parallel implementations is almost equal to the number of threads/processors. Both algorithms are worth considering in real-world applications (Florida University collection). Gauss algorithm is a better performer, with respect to timing, in the case of matrices with lower density of nonzeros, as opposed to higher density matrices. The latter are processed more efficiently with the aid of Crout algorithm implementation.

Survey on covert channels in virtual machines and cloud computing

AbstractCovert channels have been known for a long time because of their versatile forms of appearance. For nearly every technical improvement or change in technology, such channels have been (re‐)created or known methods have been adapted. For example, the introduction of hyperthreading technology has introduced new possibilities for covert communication between malicious processes because they can now share the arithmetic logical unit as well as the L1 and L2 caches, which enable establishing multiple covert channels. Even virtualization, which is known for its isolation of multiple machines, is prone to covert‐ and side‐channel attacks because of the sharing of resources. Therefore, it is not surprising that cloud computing is not immune to this kind of attacks. Moreover, cloud computing with multiple, possibly competing users or customers using the same shared resources may elevate the risk of illegitimate communication. In such a setting, the “air gap” between physical servers and networks disappears, and only the means of isolation and virtual separation serve as a barrier between adversary and victim. In the work at hand, we will provide a survey on vulnerable spots that an adversary could exploit trying to exfiltrate private data from target virtual machines through covert channels in a cloud environment. We will evaluate the feasibility of example attacks and point out proposed mitigation solutions in case they exist.

Energy Study of Monte Carlo and Quasi-Monte Carlo Algorithms for Solving Integral Equations

In the past few years the development of exascale computing technology necessitated to obtain an estimate for the energy consumption when large-scale problems are solved with different high-performance computing (HPC) systems. In this paper we study the energy efficiency of a class of Monte Carlo (MC) and Quasi-Monte Carlo (QMC) algorithms for a given integral equation using hybrid HPC systems. The algorithms are applied to solve quantum kinetic integral equations describing ultra-fast transport in quantum wire. We compare the energy performance of the algorithms using a GPU-based computer platform and CPU-based computer platform both with and without hyper-threading (HT) technology. We use SPRNG library and CURAND generator to produce parallel pseudo-random (PPR) sequences for the MC algorithms on CPU-based and GPU -based platforms, respectively. For our QMC algorithms Sobol and Halton sequences are used to produce parallel quasi-random (PQR) sequences.We compare the obtained results of the tested algorithms with respect to the given energy metric. The results of our study demonstrate the importance of taking into account not only scalability of the HPC intensive algorithms but also their energy efficiency. They also show the need for further optimisation of the QMC algorithms when GPU-based computing platforms are used.

The pseudo-distance technique for parallel lossless compression of color-mapped images

Data compression is a challenging process with important practical applications. Specialized techniques for lossy and lossless data compression have been the subject of numerous investigations during last several decades. Previously, we studied the use of the pseudo-distance technique (PDT) in lossless compression of color-mapped images and its parallel implementation. In this paper we present a new technique (PDT2) to improve compression gain of PDT. We also present a parallelized implementation of the new technique, which results in substantial gains in compression time while providing the desired compression efficiency. We demonstrate that on non-dithered images PDT2 outperforms PDT by 22.4% and PNG by 29.3%. On dithered images, PDT2 achieves compression gains of 7.1% over PDT and 23.8% over PNG. We also show that the parallel implementation of PDT2, while compromising compression less than 0.3%, achieves near linear speedup and utilization of Intel Hyper-Threading technology on supported systems improves speedup on average 18%.

Speeding up the FDK algorithm for tomographic image reconstruction in multi-core processors with hyper-threading technology

At present work we propose the use of multi-core processors to parallelize and speed up the Feldkamp, David e Kress (FDK) algorithm for tomography image reconstruction. Are commented the bases of computed tomography and the image reconstruction process. Proposes a computational implementation of the algorithm and its parallelization. The serial and parallel versions of the algorithm are compared; and measured the speedup achieved by the parallel version to be tested with different amounts of cores. The parallel version got a speedup of 10.62 to be executed in a computer with two processors INTEL with 6 physical cores each one. When using multi-core processors from INTEL beyond the physical cores we have logical cores that can be used by the operating system, when analyzing the speed gains achieved by the use of logical cores we note that the gain is around 0.15 per logic core while the speedup achieved by physical cores is around 0.7 per core.

Hyper Threading Technology in Hardware Architecture for Processor Efficiency Enhancement

Intel’s Hyper-Threading Technology brings the concept of simultaneous multi-threading to the Intel architecture. Hyper-Threading Technology makes a single physical processor appear as two logical processors; the physical execution resources are shared and the architecture state is duplicated for the two logical processors. From a software or architecture perspective, this means operating systems and user programs can schedule processes or threads to logical processors as they would on multiple physical processors. From a micro architecture perspective, this means that instructions from both logical processors will persist and execute simultaneously on shared execution resources. This paper describes the Hyper-Threading Technology architecture of Intel’s first implementation on the Intel Xeon processor family. Hyper-Threading Technology is an important addition to Intel’s enterprise product line and will be integrated into a wide variety of products.

Agent based load balancing scheme using affinity processor scheduling for multicore architectures

Multicore architecture otherwise called as CMP has many processors packed together on a single chip utilizes hyper threading technology. The main reason for adding large amount of processor core brings massive advancements in parallel computing paradigm. The enormous performance enhancement in multicore platform injects lot of challenges to the task allocation and load balancing on the processor cores. Altogether it is a crucial part from the operating system scheduling point of view. To envisage this large computing capacity, efficient resource allocation schemes are needed. A multicore scheduler is a resource management component of a multicore operating system focuses on distributing the load of some highly loaded processor to the lightly loaded ones such that the overall performance of the system is maximized. We already proposed a hard-soft processor affinity scheduling algorithm that promises in minimizing the average waiting time of the non critical tasks in the centralized queue and avoids the context switching of critical tasks. In this paper we are incorporating the agent based load balancing scheme for the multicore processor using the hard-soft processor affinity scheduling algorithm. Since we use the actual round robin scheduling for non critical tasks and due to soft affinity the load balancing is done automatically for non critical tasks. We actually modified and simulated the linux 2.6.11 kernel process scheduler to incorporate the hard-soft affinity processor scheduling concept. Our load balancing performance is depicted with respect to different load balancing algorithms and we could realize the performance improvement in terms of response time against the various homogeneous and heterogeneous load conditions. The results also shows the comparison of our agent based load balancing algorithm against the traditional static and dynamic sender, receiver initiated load balancing algorithms.

Middleware strategies for clouds and grids in e‐Science

Middleware strategies for clouds and grids in e‐Science

Evaluating new architectural features of the Intel(r) Xeon(r) 7500 Processor for hpc workloads

In this paper we take a look at what the Intel Xeon Processor 7500 family, code namedNehalem-EX, brings to high performance computing. We compare two families of Intel Xeonbased systems (Intel Xeon 7500 and Intel Xeon 5600) and present a performance evolutionof 16 node clusters based on these CPUs. We compare CPU generations utilizing dual socketplatforms and a cluster across a number of HPC benchmarks and focused on differentperformance field and aspect. We will evaluate also technologies and features like Intels HyperThreading Technology (HT) and Intel Turbo Boost Technology (Turbo Mode) and theperformance implication of these technologies for HPC.

Performance evaluation of intel's quad core processors for embedded applications

Recently, multiprocessing is implemented using either chip multiprocessing (CMP) or Simultaneous multithreading (SMT). Multi-core processors, represent CMP processors, are widely used in desktop and server applications and are now appearing in real-time embedded applications. We are investigating optimal configurations of some of the available multi-core processors suitable for developing real-time software for a multithreaded application used for pavement performance measurements. For the application discussed in this paper we are considering the use of either the Intel core 2 quad or the core i7 (a quad core processor with hyper threading (HT) technology.) Processor performance is a major requirement in this set of real-time, computational intensive embedded applications. The performance of both processors is measured and evaluated using single and multithreaded workloads supplied by different benchmark suites. As for the core i7 processor we also provide an evaluation for the HT technology implemented in each core of this processor.

Exploiting ILP, TLP, and DLP to Improve Multi-Core Performance of One-Sided Jacobi SVD

This paper shows how the performance of singular value decomposition (SVD) is enhanced through the exploitation of ILP, TLP, and DLP on Intel multi-core processors using superscalar execution, multi-threading computation, and streaming SIMD extensions, respectively. To facilitate the exploitation of TLP on multiple execution cores, the well-known cyclic one-sided Jacobi algorithm is restructured to work in parallel. On two dual-core Intel Xeon processors with hyper-threading technology running at 3.0 GHz, our results show that the multi-threaded implementation of one-sided Jacobi SVD gives about four times faster than the single-threaded superscalar implementation. Furthermore, the multi-threaded SIMD implementation speeds up the execution of single-threaded one-sided Jacobi by a factor of 10, which is close to the ideal speedup. On a reasonable large matrix size fitted in the L2 cache, our results show a performance of 11 GFLOPS (double-precision) is achieved on the target system through the exploitation of ILP, TLP, and DLP as well as memory hierarchy.

Performance Evaluation of Multi-Core Intel Xeon Processors on Basic Linear Algebra Subprograms

Multi-core technology is a natural next step in delivering the benefits of Moore's law to computing platforms. On multi-core processors, the performance of many applications would be improved by parallel processing threads of codes using multi-threading techniques. This paper evaluates the performance of the multi-core Intel Xeon processors on the widely used basic linear algebra subprograms (BLAS). On two dual-core Intel Xeon processors with Hyper-Threading technology, our results show that a performance of around 20 GFLOPS is achieved on Level-3 (matrix-matrix operations) BLAS using multi-threading, SIMD, matrix blocking, and loop unrolling techniques. However, on a small size of Level-2 (matrix-vector operations) and Level-1 (vector operations) BLAS, the use of multi-threading technique speeds down the execution because of the thread creation overheads. Thus the use of Intel SIMD instruction set is the way to improve the performance of single-threaded Level-2 (6 GFLOPS) and Level-1 BLAS (3 GFLOPS). When the problem size becomes large (cannot fit in L2 cache), the performance of the four Xeon cores is less than 2 and 1 GFLOPS on Level-2 and Level-1 BLAS, respectively, even though eight threads are executed in parallel on eight logical processors.

Parallel protein secondary structure prediction schemes using Pthread and OpenMP over hyper-threading technology

Protein secondary structure prediction has a fundamental influence on today's bioinformatics research. In this work, tertiary classifiers for the protein secondary structure prediction are implemented on Denoeux Belief Neural Network (DBNN) architecture. Hydrophobicity matrix, orthogonal matrix, BLOSUM62 matrix and PSSM matrix are experimented separately as the encoding schemes for DBNN. Hydrophobicity matrix, BLOSUM62 matrix and PSSM matrix are applied to DBNN architecture for the first time. The experimental results contribute to the design of new encoding schemes. Our accuracy of the tertiary classifier with PSSM encoding scheme reaches 72.01%, which is almost 10% better than the previous results obtained in 2003. Due to the time consuming task of training the neural networks, Pthread and OpenMP are employed to parallelize DBNN in the Hyper-Threading enabled Intel architecture. Speedup for 16 Pthreads is 4.9 and speedup for 16 OpenMP threads is 4 in the 4 processors shared memory architecture. Both speedup performance of OpenMP and Pthread is superior to that of other research. With the new parallel training algorithm, thousands of amino acids can be processed in reasonable amount of time. Our research also shows that Hyper-Threading technology for Intel architecture is efficient for parallel biological algorithms.

An efficient implementation of a 3D wavelet transform based encoder on hyper-threading technology

Video medical compression algorithms based on the 3D wavelet transform obtain both excellent compression rates and very good quality, at the expense of a higher execution time. The goal of this work is to improve the execution time of our 3D Wavelet Transform Encoder. We examine and exploit the characteristics and advantages of a hyper-threading processor. The Intel Hyper-threading Technology (HT) is a technique based on simultaneous multi-threading (SMT), which allows several independent threads to issue instructions to multiple functional units in a single cycle. In particular, we present two approaches: data-domain and functional, which differ in the way that the decomposition of the application is performed. The first approach is based on data division, where the same task is performed simultaneously by each thread on an independent part of the data. In the second approach, the processing is divided in different tasks that are executed concurrently on the same data set. Based on the latter approach, we present three proposals that differ in the way that the tasks of the application are divided between the threads. Results show speedups of up to 7% and 34% by the data-domain and functional decomposition, respectively, over a version executed without hyper-threading technology. Finally, we design several implementations of the best method with Pthreads and OpenMP using functional decomposition. We compare them in terms of execution speed, ease of implementation and maintainability of the resulting code.