Hypercube Architecture Research Articles

Universal Fault‐Tolerant Hypercube Architecture without a Switching Mechanism

AbstractThis paper proposes a new universal fault‐tolerant hypercube architecture. This architecture is obtained by constructing a basic fault‐tolerant hypercube and expanding it using the product of graphs. The basic cube is constructed by partitioning all processing elements (PEs) into subsets with weak connectivity using the Hamming distance between PE numbers and by connecting all PEs in each subset to a spare PE through buses. This architecture can maintain the original network topology and size without the addition of any switching hardware and can be applied to any size hypercube. Moreover, because the number of spare PE ports is equal to or fewer than the number of original PE ports, the same kind of PE can be used for both original PEs and spares.

On mapping systolic algorithms onto the hypercube

Consideration is given to the problem of mapping systolic array algorithms into efficient algorithms for a fixed-size hypercube architecture. The authors describe in detail several optimal implementations of algorithms given for one-way one- and two-dimensional systolic arrays. Since interprocessor communication is many times slower than local computation in parallel computers built to date, the problem of efficient communication is specifically addressed for these mappings. In order to validate the technique experimentally, five systolic algorithms were mapped in various ways onto a 64-node NCUBE/7 MIMD hypercube machine. The algorithms are for the following problems: the shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, matrix multiplication, and computing the Boolean transitive closure. Experimental evidence indicates that good performance is obtained for the mappings. >

PMothra: scheduling mutants for execution on a hypercube

Reliable software testing is a time consuming operation. In addition to the time spent by the tester in identifying, locating, and correcting bugs, a significant time is spent in the execution of the program under test and its instrumented or fault induced variants. When using mutation based testing to achieve high reliability, the number of such variants can be very large. In this paper we describe the architecture of a tool named P M othra that is designed to provide an architecture-transparent interface to a tester. In its current version, P M othra exploits the hypercube architecture by scheduling the execution of mutants on a 128-node Ncube/7 hypercube.

A recursive doubling algorithm for solution of tridiagonal systems on hypercube multiprocessors

The recursive doubling algorithm as developed by Stone can be used to solve a tridiagonal linear system of size n on a parallel computer with n processors using O(log n) parallel arithmetic steps. In this paper, we give a limited processor version of the recursive doubling algorithm for the solution of tridiagonal linear systems using O( n / p + log p) parallel arithmetic steps on a parallel computer with p < n processors. The main technique relies on fast parallel prefix algorithms, which can be efficiently mapped on the hypercube architecture using the binary-reflected Gray code. For p ≪ n this algorithm achieves linear speedup and constant efficiency over its sequential implementation as well as over the sequential LU decomposition algorithm. These results are confirmed by numerical experiments obtained on an Intel iPSC/d5 hypercube multiprocessor.

A note on the parallel Cholesky factorization of wide banded matrices

In this note, we will describe two algorithms for factoring symmetric positive definite band matrices. Both algorithms are designed for a p × p array of processors with local memory with p ⪕ O(m) , where m is the semibandwidth of the matrix. The p × p model is appropriate for the Ametek Series 2010, which is a mesh, or the popular hypercube architectures, which contain the mesh. Furthermore, the p × p model is studied, since it is the minimal connectivity which is required to implement these algorithms. The first algorithm is achieved by reflecting or folding a systolic array of Brent and Luk. An alternate approach, a torus wrap of the band matrix, is used to give an efficient method which allows the matrix to stay in place during the course of the algorithm. Both algorithms achieve nearly optimal efficiency for matrices whose bandwidth is large relative to the size of the processor array. In fact, their efficiency is asymptotically 1; in lieu of 1/3 efficiency algorithm that can be derived directly from that of Brent and Luk or as presented by Chan et al. We conclude with a medium grain adaptation of these methods, which maintains their near optimality.

Mapping strategies in message-based multiprocessor systems

Machines with distributed memory have the mapping problem—assigning processes to processors. In this paper we define the mapping problem as an optimization problem and discuss the question, how far is an optimum solution from an average or random solution. The term robustness is introduced and explained in detail with two examples, the SUPRENUM and the hypercube architecture. For the SUPRENUM architecture we show that a simple mapping strategy (optimal clustering of the processes) gives almost as good results as the optimal mapping. Optimal mapping is more important for the hypercube architecture. For nonhomogeneous networks adaptive routing seems promising.

On the communication structures of hyper-ring and hypercube multicomputers

The well-known torus and its variants, which we call hyper-rings, as well as hypercube architectures are further studied and evaluated as interconnection networks for multicomputers. Comparisons are made among hyper-rings and between hyper-ring and hypercube networks under different communication patterns. It is concluded that although it is believed that a hypercube is generally superior to hyper-rings in performance, this is not always the case, particularly for locally constrained applications, where communications occur mostly among neighboring nodes.

Performability of the hypercube (reliability)

The authors address the problem of modeling and evaluating the composite performance and reliability measures (performability) of a hypercube architecture running a specific application. A generalized stochastic Petri net (GSPN) is used to model the component failures and repairs in the hypercube. The GSPN model defines the dimension and number of subcubes available for the application. This model generalizes previously proposed models for hypercube reliability and automatically generates the underlying Markov chain needed for performability analysis. A novel performability analysis algorithm is presented that computes both the moments and the distribution of performability in O(N/sup 3/). The algorithm is conceptually simpler than those previously reported. An example is given to illustrate the modeling process and demonstrate the importance of performability analysis for mission-critical systems. >

Modeling the performance of hypercubes: A case study using the particle-in-cell application

We have mapped onto the iPSC hypercube a particle-in-cell (PIC) algorithm that executes a plasma simulation. PIC simulates the movement of charged particles under the influence of an electrostatic field. This application provides a simple example of the problems associated with load balancing on distributed memory architectures. We present several alternative solutions to mappings of the algorithm onto the hypercube. One solution's performance is modeled and benchmarked with data from an implementation on the iPSC. The model is used to predict performance for larger size problems and a state-of-the-art hypercube architecture. We also introduce the use of provably optimal global communication algorithms that are needed for the PIC implementation on the hypercube.

A programming aid for hypercube architectures

A program development tool that automatically performs scheduling and synchronization insertion for hypercube systems is presented in this paper. We use a programming methodology in which a program is written as a set of procedures called from the main program. This program is converted into a macro dataflow graph which is used by the tool to generate executable code for hypercube machines. The program restructured by our tool outperformed the manually developed code, while increasing the program development productivity at the same time.

A parallel global adaptive quadrature algorithm for hypercubes

We have developed a one-dimensional parallel global adaptive quadrature algorithm for a machine with hypercube architecture, and studied the heuristics present in the algorithm. A mathematical model for how long time it takes to process a balanced tree of sub-intervals under certain (almost implementable) conditions is developed. The results from numerical experiments are given. The speedups achieved depend on the problem and are ranging from 0.83 to 30.5 on a 32-processor hypercube.

Optimally universal parallel computers

It is shown that any program written for the idealized shared-memory model of parallel computation can be simulated on a hypercube architecture with only constant factor inefficiency, provided that the original program has a certain amount of parallel slackness.

Automated mesh decomposition and concurrent finite element analysis for hypercube multiprocessor computers

This paper discusses a concurrent finite element formulation for linear and nonlinear transient analysis using an explicit time integration scheme. The formulation has been developed for execution on hypercube multiprocessor computers. The formulation includes a new decomposition algorithm which automatically divides an arbitrary finite element mesh into regions and assigns each region to a processor on the hypercube. The algorithm selects the assignment of regions so as to minimize interprocessor communication and to balance the computational load across the processors. The decomposition algorithm is detetministic in nature and relies on a scheme which reduces the bandwidth of the matrix representation of the connectivities in the mesh. The algorithms have been implemented on a 32-processor Intel hypercube (the iPSC/d5 machine): speedup factors of greater than 31 have been obtained. Performance limitations of the hypercube architecture for finite element analysis are discussed.

A behavioural simulator and its use for the validation of hypercube architectures

The synthesis of software algorithms and their hardware implementation require the use of efficient CAD tools providing detailed simulations and performance analysis. This paper presents a new behavioural simulator whose functional model is characterized by strict and non-strict functions, and by the concept of static and dynamic instances defined at different hierarchical levels of the structural description. Then, an extensive application of the simulator for the study of hypercube architectures is described.

$LU$ Factorization Algorithms on Distributed-Memory Multiprocessor Architectures

In this paper, we consider the effect that the data-storage scheme and pivoting scheme have on the efficiency of $LU$ factorization on a distributed-memory multiprocessor. Our presentation will focus on the hypercube architecture, but most of our results are applicable to distributed-memory architectures in general. We restrict our attention to two commonly used storage schemes (storage by rows and by columns) and investigate partial pivoting both by rows and by columns, yielding four factorization algorithms. Our goal is to determine which of these four algorithms admits the most efficient parallel implementation. We analyze factors such as load distribution, pivoting cost, and potential for pipelining. We conclude that, in the absence of loop-unrolling, $LU$ factorization with partial pivoting is most efficient when pipelining is used to mask the cost of pivoting. The two schemes that can be pipelined are pivoting by interchanging rows when the coefficient matrix is distributed to the processors by columns, and pivoting by interchanging columns when the matrix is distributed to the processors by rows.

The class kernel-models in DEVS-scheme: a hypercube architecture example

DEVS-Scheme is a realization of DEVS (Discrete Event System Specification) formalism in a LISP-based, object-oriented environment, which supports hierarchical, modular specification of discrete event models. We describe the taxonomical organization of classes in DEVS-Scheme in which the hypercube-models class is described in detail. As an example, we illustrate specification of a hypercube model of a computer architecture. DEVS-Scheme represents a significant step toward implementing system-theoretic based formalisms and operations.

Gray codes, Fast Fourier Transforms and hypercubes

Fast Fourier Transforms are a widely-used and powerful tool for the analysis and solution of many problems. They have been used in such diverse areas as medicine, acoustics, image processing, system design and many other fields. By transforming the data the problem may be simpler, more tractable or more efficiently solved and for many applications (e.g. speech processing) the data may be much more easily understood in the transform domain. Therefore fast algorithms for implementing transforms are vital for any powerful computer. This paper describes the implementation of a Fast Fourier Transform on a 64-node INTEL hypercube and shows how the hypercube architecture may be efficiently used. Usually the FFT is only a part of the solution process and the data on the hypercube has to be arranged in a certain manner for the efficient solution of the whole problem. A common way is for the data to be distributed according to a Gray code, so that neighbouring points in the domain are in neighbouring processors. We present a number of results on Gray codes which characterise a certain family of Gray codes, and show that Fast Fourier Transforms on data distributed among processors according to a Gray code can also be efficiently implemented on the hypercube.

Molecular dynamics of a model polymer on a hypercube parallel computer

Abstract In this paper, we discuss the implementation and solution of molecular dynamics polymer models on the Intel iPSC Hypercube parallel computer. We first describe a model problem whose inherent parallelism can be exploited effectively and which is therefore amenable to parallel solution. We next discuss the salient features of the hypercube programs that were used to solve the model problem. Finally, we present results which demonstrate that the efficiencies of the solutions approach 100% as the number of atoms in the polymer and the number of hypercube processors are increased for the problem in question. The results demonstrate that parallel solutions of polymer problems using a hypercube architecture offer potentially significant savings over sequential solutions.

Matrix Operations on a Multicomputer System with Switchable Main Memory Modules and Dynamic Control

This paper presents an analysis and evaluation of the performance of a multicomputer system (SM3) in supporting two basic matrix operations, namely multiplication and inversion. The system supports the efficient execution of the above mentioned operations by 1) achieving a high-bandwidth data transfer among computers by switching main memory modules, 2) supporting network partitioning, 3) employing a hardware communication and synchronization scheme, 4) using a distributed control technique, and 5) providing means to dynamically transfer control. Timing equations are derived and evaluated in an attempt to analyze the performance. Different cases which arise due to the relative sizes of memory modules and matrices during matrix multiplication are analyzed. The cases of partial and maximal pivoting during inversion are also analyzed. The SM3 system is compared quantitatively and qualitatively to a hypercube architecture.

Communication efficient basic linear algebra computations on hypercube architectures

This paper presents a few algorithms for embedding loops and multidimensional arrays in hypercubes with emphasis on proximity preserving embeddings. A proximity preserving embedding minimizes the need for communication bandwidth in computations requiring nearest neighbor communication. Two storage schemes for “large” problems on “small” machines are suggested and analyzed, and algorithms for matrix transpose, multiplying matrices, factoring matrices, and solving triangular linear systems are presented. A few complete binary tree embeddings are described and analyzed. The data movement in the matrix algorithms is analyzed and it is shown that in the majority of cases the directed routing paths intersect only at nodes of the hypercube allowing for a maximum degree of pipelining.