Hypercube Architecture Research Articles

Communication-efficient matrix multiplication on hypercubes

In this paper we present an efficient dense matrix multiplication algorithm for distributed memory computers with a hypercube topology. The proposed algorithm performs better than all previously proposed algorithms for a wide range of matrix sizes and number of processors, especially for large matrices. We analyze the performance of the algorithms for two types of hypercube architectures, one in which each node can use (to send and receive) at most one communication link at a time and the other in which each node can use all communication links simultaneously.

Scheduling divisible jobs on hypercubes†

In this work a problem of finding an optimal distribution of a divisible computational job among a set of processors is considered. In the model of parallel computer systems two important factors must be taken into account: speeds of processors and speeds of communications links. With regard to this, we propose a deterministic approach finding an optimal distribution of the job's load on a hypercube of processors. The method used allows also the determination of performance bounds on the hypercube architecture.

Graphics in parallel computation for rendering 3D modelled scenes

To design objects or entire scenes in real time with free-form surfaces makes a shifting process to parallel architectures absolutely necessary. This migration has advantages in the computation phase but penalizes in the visualization phase. The present paper takes as an example a hidden-line sequential algorithm for parametric surfaces and proposes an optimized parallel version for a hypercube architecture provided with the capability to make graphic requests in parallel. Considerations of a general type result as well as the need to introduce a new metrics evaluation of the performances that keeps count of the graphic visualization phase.

SCALABLE MULTIFOLDED HYPERCUBES FOR VERSATILE PARALLEL COMPUTERS

This paper introduces the family of scalable multifolded hypercube (SMH) architectures for parallel computers. Scalability and versatility at resonable cost are the major characteristics of these architectures. SMHs perform comparable to generalized hypercubes for important classes of algorithms that use regular communication patterns. In addition, they often achieve better performance than the popular direct binary hypercubes because they can emulate efficiently a powerful family of multifolded direct binary hypercubes. Extensive comparison of cost with binary and generalized hypercubes is also included. The hardware cost of SMH's is shown to be even lower than that of fat trees. Therefore, SMH's are viable candidates for the construction of versatile parallel computers.

A RECURRENCE-FREE VARIANT OF STRASSEN'S ALGORITHM ON HYPERCUBE∗

In this paper a non-recursive Strassen's matrix multiplication algorithm is presented. This new algorithm is suitable to run on parallel environments. Two computational schemes have been worked out exploiting different parallel approaches on hypercube architecture. A comparative analysis is reported. The experiments have been carried out on an nCUBE-2 supercomputer, housed at CNUCE in Pisa, Express parallel operating system.

Ring-connected networks and their relationship to cubical ring connected cycles and dynamic redundancy networks

Reviews a 1-fault-tolerant (1-ft) hypercube model with degree 2r: the ring-connected network (RCN), which has the lowest degree among all 1-ft, one-spare node, r-dimensional hypercube architectures yet discovered. Then, we propose a constant-time reconfiguration algorithm via an add-and-modulo automorphism. Furthermore, by introducing the equivalence from hypercubes to cube-connected cycles (CCCs) and to butterflies (BFs), we find that there is also a corresponding equivalence from RCNs to cubical ring-connected cycles (CRCCs) and to dynamic redundancy networks (DRNs). From this fact, we find that once a symmetric fault-tolerant structure has been discovered for one of the three models, then it can be applied directly to the other hypercubic networks. Applying the technique, we find a degree-6, 1-ft Benes network. We think that more attention should be paid to the strong relationship between hypercubes, CCCs and BFs. Finally, from this equivalence relationship we propose three new bounded-degree k-ft models: k-ft CCCs, k-ft BFs and k-ft Benes networks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel computation of impact dynamics

This paper discusses a parallel algorithm and data structures for implementing multimaterial, two-step Eulerian finite difference solution schemes on hypercube architectures. Selected problems in impact dynamics have been modeled on the Connection Machine model CM5, and the results are compared with computational results reported in the literature, as well as direct comparison with experimental data.

High-speed computation of the EM algorithm for PET image reconstruction

The PET image reconstruction based on the EM algorithm has several attractive advantages over the conventional convolution backprojection algorithms. However, two major drawbacks have impeded the routine use of the EM algorithm, namely, the long computational time due to slow convergence and the large memory required for the storage of the image, projection data and the probability matrix. Here, the authors attempt to solve these two problems by parallelizing the EM algorithm on a multiprocessor system. They have implemented an extended hypercube (EH) architecture for the high-speed computation of the EM algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs). The authors discuss and compare the performance of the EM algorithm on a 386/387 machine, CD 4360 mainframe, and on the EH system. The results show that the computational speed performance of an EH(3,1) using DSP chips as PEs executing the EM image reconstruction algorithm is about 130 times better than that of the CD 4360 mainframe. The EH topology is expandable with more number of PEs.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A massively parallel knowledge-base server using a hypercube multiprocessor

In this paper we study the parallel implementation of a traditional frame based knowledge representation system for a general purpose massively parallel hypercube architecture (such as the Connection Machine CM-2). We show that, using a widely available parallel system (instead of a special purpose architecture), it is possible to provide multiple users with efficient shared access to a large scale knowledge-base. Parallel algorithms are presented for answering multiple inference, assert and retract queries on both single and multiple inheritance hierarchies. In addition to theoretical time complexity analysis, empirical results obtained from extensive testing of a prototype implementation are presented.

Scalable Load Balancing Techniques for Parallel Computers

In this paper we analyze the scalability of a number of load balancing algorithms which can be applied to problems that have the following characteristics: the work done by a processor can be partitioned into independent work pieces; the work pieces are of highly variable sizes; and it is not possible (or very difficult) to estimate the size of total work at a given processor. Such problems require a load balancing scheme that distributes the work dynamically among different processors. Our goal here is to determine the most scalable load balancing schemes for different architectures such as hypercube, mesh, and network of workstations. For each of these architectures, we establish lower bounds on the scalability of any possible load balancing scheme. We present the scalability analysis of a number of load balancing schemes that have not been analyzed before. This gives us valuable insights into their relative performance for different problem and architectural characteristics. For each of these architectures, we are able to determine near optimal load balancing schemes. Results obtained from implementation of these schemes in the context of the Tautology Verification problem on the Ncube/2 (a trademark of the Ncube Corporation) multicomputer are used to validate our theoretical results for the hypercube architecture. These results also demonstrate the accuracy and viability of our framework for scalability analysis.

Improved lower bounds on the reliability of hypercube architectures

The hypercube topology, also known as the Boolean n-cube, has recently been used for multiprocessing systems. The paper considers two structural-reliability models, namely, terminal reliability (TR) and network reliability (NR), for the hypercube. Terminal (network) reliability is defined as the probability that there exists a working path connecting two (all) nodes. There are no known polynomial time algorithms for exact computation of TR or NR for the hypercube. Thus, lower-bound computation is a better alternative, because it is more efficient computationally, and the system will be at least as reliable as the bound. The paper presents algorithms to compute lower bounds on TR and NR for the hypercube considering node and/or link failures. These algorithms provide tighter bounds for both TR and NR than known results and run in time polynomial in the cube dimension n, specifically, within time O(n/sup 2/). >

Performance of hypercube architecture with shared memory

The performance of hypercube architectures depends on the topology of the problem being solved. Specifically, they are unsuitable for knowledge-based applications where global data access is very often required. In this work, a new architecture is proposed that can be used in such applications. The proposed architecture uses both the shared memory and the distributed memories. In this architecture, shared memory is connected to the basic hypercubes using multistage interconnection networks (MINs). In this analysis, the Omega network is considered. When global memory and distributed memories are used, multiple copies of shared data deteriorate the system performance because of data invalidation traffic in the network, and the coherency implementation overhead. Maintaining single copies of the shared data can eliminate the invalidation traffic and the coherency related activities. However, the single copies are to be dynamically moved using a data movement policy to serve the memory references. Analytical m...

2-D FFT algorithm by matrix factorization in a 2-D space

A new 2-D FFT algorithm is described. This algorithm applies a 2-D matrix factorization technique in a 2-D space and offers a way to do 2-D FFT in both dimensions simultaneously. The computation is greatly reduced compared to traditional algorithms. This will improve the realization of a 2-D FFT on any kind of computer. However its good parallelism will especially benefit an implementation on a computer with hypercube architecture. A good arrangement of parallel processors will save a great deal of running time. Furthermore this algorithm can be extended toM-D cases forM>2.

An Efficient Algorithm for Gray-to-Binary Permutation on Hypercubes

Both Gray code and binary code are frequently used in mapping arrays into hypercube architectures. While the former is preferred when communication between adjacent array elements is needed, the latter is preferred for FFT-type communication. When different phases of computations have different types of communication patterns, the need arises to remap the data. We give a nearly optimal algorithm for permuting data from a Gray code mapping to a binary code mapping on a hypercube with communication restricted to one input and one output channel per node at a time. Our algorithm improves over the best previously known algorithm ( J. Parallel Distrib. Comput. 4, 2 (Apr. 1987), 133-172) by nearly a factor of two and is optimal to within a factor of n( n − 1) with respect to data transfer time on an n-cube. The expected speedup is confirmed by measurements on an Intel iPSCI2 hypercube.

Rearrangeable Circuit-Switched Hypercube Architectures for Routing Permutations

Rearrangeable hypercube architectures and routing algorithms are developed to realize arbitrary permutations in circuit switching. We prove that if each connection between two neighboring nodes consists of two pairs of links (two full-duplex communication lines), the hypercube can handle two arbitrary permutations simultaneously. We also prove that a hypercube is rearrangeable if one additional pair of links is provided in any one dimension of connections.

Fault-tolerance analysis of hypercube systems using Petri net theory

Studies of performance disregarding reliability or reliability ignoring performance do not give a complete picture of the capability of parallel/distributed systems. However, a combined study of performance and reliability (performability) is becoming increasingly important in evaluating the behavior of such systems. In this article, we propose a technique to model and analyze the performability of parallel and distributed architectures using generalized stochastic Petri nets (GSPNs). This technique consists of 1. 1) a GSPN performance model, 2. 2) a GSPN reliability model, and 3. 3) a method for combining a Markov reliability model with the metrics of the performance model. We illustrate use of the proposed technique by first modeling and analyzing the performance of an Intel personal super computer (iPSC) /2 hypercube system under the workload of a concurrent matrix multiplication algorithm. Next, a reliability model based on a subcube reliability approach in the presence of multiple faults with and without repair (or coverage) is modeled and analyzed. Finally, various performability measures for the hypercube architecture are presented. To refine the performability model, a parametric sensitivity analysis is presented.

Mutual Exclusion on a Hypercube

We present a decentralized, symmetric mutual exclusion algorithm that is tailored to the hypercube architecture. Our algorithm has better time complexity than a suitable hypercube adaptation of Maekawa′s O(√ N) Mutual Exclusion algorithm. We show that, in the presence of contention, our algorithm has a shorter Blocking Delay than Maekawa′s algorithm. In the absence of contention, our algorithm achieves optimal Round-trip Delay under both the n-port and the one-port communication models.

Performance Evaluation of a Parallel I/O Subsystem for Hypercube Multicomputers

Though input/output (I/O) from mass storage continues to be a bottleneck in current generation distributed-memory multicomputers, few studies have been conducted on the system-level impact of an independent I/O network and distributed file system for such machines. This paper quantifies the improvement in performance obtained in a hypercube multicomputer by providing a separate network that serves multiple I/O nodes operating under a distributed file system. First, the concept of balanced architectures is used to show that for a general purpose multicomputer with N processing elements, the I/O subsystem should scale as N/log N. Analytical and simulation studies are performed on a hypercube architecture that is augmented by an independent I/O network that achieves this scale factor. For wormhole routing, a significant improvement in latency can be obtained for both small inter-processor messages and much larger I/O transactions, provided the bandwidth of a channel in the I/O network is slightly higher than that of a PE-PE channel. Moreover, performance becomes relatively insensitive to data locality, and thus to the file allocation policy, when this extra bandwidth is available. Simulation results are presented for a 128-node hypercube, and are validated by an analytical model.

Fault-tolerant meshes and hypercubes with minimal numbers of spares

This paper presents several techniques for tolerating faults in d-dimensional mesh and hypercube architectures. The approach consists of adding spare processors and communication links so that the resulting architecture will contain a fault-free mesh or hypercube in the presence of faults. The authors optimize the cost of the fault-tolerant architecture by adding exactly k spare processors (while tolerating up to k processor and/or link faults) and minimizing the maximum number of links per processor. For example, when the desired architecture is a d-dimensional mesh and k=1, they present a fault-tolerant architecture that has the same maximum degree as the desired architecture (namely, 2d) and has only one spare processor. They also present efficient layouts for fault-tolerant two- and three-dimensional meshes, and show how multiplexers and buses can be used to reduce the degree of fault-tolerant architectures. Finally, they give constructions for fault-tolerant tori, eight-connected meshes, and hexagonal meshes. >

A RECONFIGURATION TECHNIQUE FOR FAULT TOLERANCE IN A HYPERCUBE

The hypercube architecture is a popular topology for many parallel processing applications. For continued operation of the hypercube multiprocessors after the failure of one or more i-subcubes and/or links, fault tolerance by reconfiguration is an important problem. This paper considers the reconfiguration issue and presents an algebraic technique to analyze the problem extending the concepts in [9]. The technique uses algebraic operators to identify the maximum dimensional fault-free subcube, and thus helps in achieving graceful degradation of the system. We analyze the complexity of our algorithm and show that it is efficient as compared to previous algorithms [1, 8, 14].