Hypercube Architecture Research Articles

HyperCube: Implicit Field Representations of Voxelized 3D Models (Student Abstract)

Implicit field representations offer an effective way of generating 3D object shapes. They leverage an implicit decoder (IM-NET) trained to take a 3D point coordinate concatenated with a shape encoding and to output a value indicating whether the point is outside the shape. This approach enables the efficient rendering of visually plausible objects but also has some significant limitations, resulting in a cumbersome training procedure and empty spaces within the rendered mesh. In this paper, we introduce a new HyperCube architecture based on interval arithmetic that enables direct processing of 3D voxels, trained using a hypernetwork paradigm to enforce model convergence. The code is available at https://github.com/mproszewska/hypercube.

Dynamic Scheduling Algorithm for Variants of Hypercube Interconnection Networks

Objectives: Topropose analgorithm for better performance interms of scheduling and the network usage is economical. Method/Statistical Analysis: The dynamic task scheduling algorithm has been proposed for scheduling the load on numerous cube based multiprocessor interconnection networks. Especially the efficiency of the proposed algorithm is examined in terms of performance parameters for instance Load Imbalance Factor’s as well as Execution Time for cube based multiprocessor networks; Nevertheless, a comparison is created with other standard scheduling algorithm. Findings:The comparative simulation study shows that the proposed algorithm gives better performance in terms of task scheduling on various cube based multiprocessor networks. Application: The study in such a direction implies that the variety of processors in folded hypercube has been decreased thus minimizing the cost as well as intricacy of the network without reducing the efficiency of the network. Therefore, a combination of scalable folded hypercube architecture and efficient proposed algorithm is a better organization model that supports variety of informatics applications.

Linear Crossed Cube (LCQ): A New Interconnection Network Topology for Massively Parallel System

Scalability and Complexity are crucial performance parameters in the design of Interconnection networks for multiprocessor system. This paper proposed and analyzed a new scalable interconnection network topology named as Linear Crossed Cube (LCQ). LCQ designed is based on the principle of hypercube architecture however, it improves some of the drawbacks of hypercube such as complex extensibility and its VLSI Layout. It inherits most of the desirable properties of hypercube type architectures; the most notably are small diameter and symmetry. LCQ has linear extension at each level of the extension while preserving all the desired topological properties. To evaluate the performance of proposed LCQ, standard scheduling algorithms are being implemented on it. The performance parameters such as Load Imbalance Factor (LIF) and balancing time are evaluated on the proposed LCQ as well as on other similar multiprocessor architectures. To compare the performance of proposed LCQ, standard scheduling scheme is also implemented on other similar multiprocessor architectures. The comparative simulation study shows that the proposed network can be considered as low-cost multiprocessor architecture for parallel system when appropriate scheduling algorithm is implemented onto it.

Incomplete crossed hypercubes

In this paper, a new interconnection network called the incomplete crossed hypercube is proposed for connecting processors of parallel computing systems. The incomplete crossed hypercube architecture denoted by CI n?m n is made by combining two complete crossed hypercubes CQ n and CQ n?m for 1?m?n. Several topological properties of CI n?m n are analyzed. In particular, accurate mean internode distance formulas of both CQ n and CI n?m n are given. Compared with the incomplete enhanced hypercube EI n?m n , CI n?m n has shorter mean internode distance for large n. An optimal routing algorithm for CI n?m n is also described which guarantees the generation of a shortest path from a node to another in CI n?m n .

STAR-CUBE: A Special Purpose Interconnection Network for Signal Processing

Both Hypercube and star graph networks possess desirable properties like regularity, vertex and edge symmetric, maximally fault-tolerant etc, though, some of the attractive features of one are not found in the other. In this paper, we propose and study a composite architecture, which is a combination of these two architectures and call it Star-Cube. The most important characteristic of the proposed star-cube network is that, it can be incremented in smaller steps. This is an advantage for FFT implementation as an architecture with reasonable number of nodes can be made out of this star-cube graph that will give more processor utilization than either star-graph or Hypercube architecture individually. It provides some of the desirable properties of both the networks such as reduced diameter and degree. The degree and diameter of the proposed network falls in-between its individual constituents that make it suitable for Fast Fourier Transform (FFT) type of processing. The proposed Star-Cube network has simple routing algorithms amenable to networks with faults. Other parameters such as average distance, number of links, fault-tolerance, etc, are computed. To show its performance, a Fast Fourier Transform algorithm is considered for implementation in this hybrid network where a hierarchical ranking scheme is adopted for assigning node addresses. We estimate the speedup and efficiency for the Star-cube graph. It is observed that our proposed star-cube interconnection network gives reasonable speedup as compared to hypercube and star graph as FFT processor.

What designers of bus and network architectures should know about hypercubes

We quantify why, as designers, we should prefer clique-based hypercubes (K-cubes) over traditional hypercubes based on cycles (C-cubes). Reaping fresh analytic results, we find that K-cubes minimize the wirecount and, simultaneously, the latency of hypercube architectures that tolerate failure of any f nodes. Refining the graph model of Hayes (1976), we pose the feasibility of configuration as a problem in multivariate optimization: What (f+1)-connected n-vertex graphs with fewest edges [n(f+1)/2] minimize the maximum a) radius or b) diameter of subgraphs (i.e., quorums) induced by deleting up to f vertices? We solve (1) for f that is superlogarithmic but sublinear in n and, in the process, prove: 1) the fault tolerance of K-cubes is proportionally greater than that of C-cubes; 2) quorums formed from K-cubes have a diameter that is asymptotically convergent to the Moore Bound on radius; 3) under any conditions of scaling, by contrast, C-cubes diverge from the Moore Bound. Thus, K-cubes are optimal, while C-cubes are suboptimal. Our exposition furthermore: 4) counterexamples, corrects, and generalizes a mistaken claim by Armstrong and Gray (1981) concerning binary cubes; 5) proves that K-cubes and certain of their quorums are the only graphs which can be labeled such that the edge distance between any two vertices equals the Hamming distance between their labels; and 6) extends our results to K-cube-connected cycles and edges. We illustrate and motivate our work with applications to the synthesis of multicomputer architectures for deep space missions.

A parallel algorithm of texture analysis for liquid crystal investigation

Observation by means of the polarised light microscope plays a fundamental role in recognising typical patterns and detecting defects in the liquid crystal cells. The digital image processing greatly improves the experimental work allowing both quantitative and qualitative analysis. On the other hand, the high computation time required by image investigation methods restricts their application. We present a parallel version of an algorithm for pattern analysis and its fulfilment on a hypercube architecture, that reduces the computation time linearly with the number of used processors.

Parallel conjugate gradient performance for least-squares finite elements and transport problems

In this study we consider parallel conjugate gradient solution of sparse systems arising from the least-squares mixed finite element method. Of particular interest are transport problems involving convection. The least-squares approach leads to a symmetric positive system and the conjugate gradient scheme is directly applicable. The scheme is applied to both the convection–diffusion equation and to the stationary Navier–Stokes equations. Here we demonstrate parallel solution and performance studies for a representative MIMD parallel computer with hypercube architecture. © 1998 John Wiley & Sons, Ltd.

KH-map: A new way of representing the hypercube structure

The hypercube structure is an attractive and powerful topology for interconnecting processing elements in a multiprocessor system since it allows simple deadlock-free routing and broadcasting. In a hypercube architecture, one has to visualize multidimensional objects to develop efficient algorithms or to analyze system behavior. However, human beings are habituated to at most three-dimensional objects. In this paper, we propose a novel two-dimensional representation of the hypercube structure. The proposed representation is used to design routing and broadcasting algorithms. Finally, a comparison of the proposed representation with the conventional hypercube representation is elucidated.

Fault-tolerant message routing in the extended hypercube

In real-time computing applications, it is important to have parallel computing systems that not only exhibit high performance but also continue to perform reliably under faulty conditions. The hypercube is one of the most popular and robust network topologies used for building distributed memory message passing multiprocessor systems. However, the hypercube does not have a constant building block and it is difficult to build hypercubes of large dimensions on account of the logarithmic degree of connectivity. The extended hypercube architecture exhibits such good properties as constant degree of node, low diameter and a constant basic building block. In addition it has a hierarchical, recursive and highly scalable structure. The extended hypercube is also robust to link faults. However the extended hypercube suffers from poor fault-tolerance to node faults as it has articulation points. In this paper we present a fault-tolerant variation of the extended hypercube, the extended hypercube with symmetrical connections. The latter topology retains all the positive features of the former and in addition exhibits improved fault-tolerant characteristics. We design efficient fault-tolerant routing algorithms for the extended hypercube architectures and report simulation results.

O(log logN) Time Algorithms for Hamiltonian Suffix and Min-Max-Pair Heap Operations on the Hypercube

This paper deals with a fast implementation of a heap data structure on a hypercube-connected, synchronous, distributed-memory multicomputer. In particular, we present a communication-efficient mapping of a min-max-pair heap on the hypercube architecture in which the load on each processor's local memory is balanced and propose cost-optimal parallel algorithms which requireO((logN)/p+ logp) time to perform single insertion, deletemin, and deletemax operations on a min-max-pair heap of sizeN, wherepis the number of processors. Our implementation is based on an embedding of complete binary trees in the hypercube and an efficient parallel solution to a special kind of suffix computation, that we call theHamiltonian suffix, along a Hamiltonian path in the hypercube. The binary tree underlying the heap data structure is, however, not altered by the mapping process.

Parallel discrete invariant embedding algorithm for singular pertubation problems

In this paper, Parallel Discrete Invariant Embedding algorithm is given for solving singularly perturbed boundary value problems. This algorithm is presented for both unlimited and limited processors using hypercube architecture.

High-speed parallel implementation of a modified PBR algorithm on DSP-based EH topology

Algebraic Reconstruction Technique (ART) is an age-old method used for solving the problem of three-dimensional (3-D) reconstruction from projections in electron microscopy and radiology. In medical applications, direct 3-D reconstruction is at the forefront of investigation. The simultaneous iterative reconstruction technique (SIRT) is an ART-type algorithm with the potential of generating in a few iterations tomographic images of a quality comparable to that of convolution backprojection (CBP) methods. Pixel-based reconstruction (PBR) is similar to SIRT reconstruction, and it has been shown that PBR algorithms give better quality pictures compared to those produced by SIRT algorithms. In this work, we propose a few modifications to the PBR algorithms. The modified algorithms are shown to give better quality pictures compared to PBR algorithms. The PBR algorithm and the modified PBR algorithms are highly compute intensive, Not many attempts have been made to reconstruct objects in the true 3-D sense because of the high computational overhead. In this study, we have developed parallel two-dimensional (2-D) and 3-D reconstruction algorithms based on modified PBR. We attempt to solve the two problems encountered by the PBR and modified PBR algorithms, i.e., the long computational time and the large memory requirements, by parallelizing the algorithm on a multiprocessor system. We investigate the possible task and data partitioning schemes by exploiting the potential parallelism in the PBR algorithm subject to minimizing the memory requirement. We have implemented an extended hypercube (EH) architecture for the high-speed execution of the 3-D reconstruction algorithm using the commercially available fast floating point digital signal processor (DSP) chips as the processing elements (PEs) and dual-port random access memories (DPR) as channels between the PEs. We discuss and compare the performances of the PBR algorithm on an IBM 6000 RISC workstation, on a Silicon Graphics Indigo 2 workstation, and on an EH system. The results show that an EH(3,1) using DSP chips as PEs executes the modified PBR algorithm about 100 times faster than an LBM 6000 RISC workstation. We have executed the algorithms on a 4-node IBM SP2 parallel computer. The results show that execution time of the algorithm on an EH(3,1) is better than that of a 4-node IBM SP2 system. The speed-up of an EH(3,1) system with eight PEs and one network controller is approximately 7.85.

Simulation Study of the Performance of a Cluster-Based Hypercube Multicomputer

In this paper, discrete-event simulation is used to evaluate the performance of a cluster-based hypercube architecture running parallel simplex and parallel Gaussian elimination algorithms. The cluster-based hypercube architecture enhances the performance of the nodes of the existing hypercube architecture systems by incorporating in each node, a cluster of n execution processors connected through a small cross-bar switch with n memory modules. The memory modules in each node are shared by the processors within the node. The simulations were developed for both the cluster-based hypercube architecture and the Intel Personal Supercomputer (iPSC/860, a conventional hypercube), and the results obtained were compared. The simulation results show a response time performance improvement of up to 30% in favor of the cluster-based hypercube architecture. We also observe that for increased link delays, the performance gap increases significantly in favor of the cluster-based hypercube architecture.

Implementation of parallel FFT algorithms on distributed memory machines with a minimum overhead of communication

We present in this paper methods for the many mono-dimensional and multi-dimensional FFT algorithms which minimize the communication overhead. We describe the implementation of these algorithms on a hypercube architecture. Moreover, we derive these implementations onto mesh and torus topologies by using emulation results of hypercube communications on these topologies. We compute optimal sizes of blocks in order to obtain a maximal overlap of communications by computations. Experimental results on Intel iPSC/860 and Paragon, IBM SP1 and Cray T3D machines are given, which confirm the theoretical analysis.

The Flexible Hypercube: A New Fault-Tolerant Architecture for Parallel Computing

This paper presents the new Flexible Hypercube architecture. The Flexible Hypercube is a fault-tolerant network topology that can be constructed for an arbitrary number of nodes and is incrementally expandable. This topology maintains the strong features of the Hypercube while overcoming deficiencies in expandability. It is shown to have strong node connectivity, a small diameter, and to be tolerant of faults. The Flexible Hypercube is a suitable architecture for the design of both tightly coupled parallel systems and distributed systems. Efficient fault-free and fault-tolerant algorithms for message routing and broadcasting are presented for the architecture. The fault-free algorithm guarantees successful routing inO(logN) time, whereNis the number of nodes in the system, and the fault-tolerant algorithm guarantees routing to functioning nodes if a route exists. The fault-free and fault-tolerant broadcasting algorithms have time complexityO(logN), and the fault-tolerant algorithm guarantees success if no two faulty nodes are adjacent and no functioning node is adjacent to two faults.

Optimal and load balanced mapping of parallel priority queues in hypercubes

We efficiently map a priority queue on the hypercube architecture in a load balanced manner, with no additional communication overhead, and present optimal parallel algorithms for performing insert and deletemin operations. Two implementations for such operations are proposed on the single port hypercube model. In a b-bandwidth, n-item priority queue in which every node contains b items in sorted order, the first implementation achieves optimal speed up of O(min{log n, b log n/log b+log log n}) for inserting b presorted items or deleting b smallest items, where b=O(n/sup 1/c/) with c>1. In particular, single insertion and deletion operations are cost optimal and require O(log n/p+log p) time using O(log n/log log n) processors. The second implementation is more scalable since it uses a larger number of processors, and attains a "nearly" optimal speedup on the single hypercube. Namely, the insertion of log n presorted items or the deletion of the log n smallest items is accomplished in O(log log n/sup 2/) time using O(log/sup 2/ n/log log n) processors. Finally, on the slightly more powerful pipelined hypercube model, the second implementation performs log n operations in O(log log n) time using O(log/sup 2/ n/log log n) processors, thus achieving an optimal speed up. To the best of our knowledge, our algorithms are the first implementations of b-bandwidth distributed priority queues, which are load balanced and yet guarantee optimal speed ups.

Parallel Preprocessing Algorithms for Document Image Analysis

This paper presents the parallel implementation of sequential algorithms for skew estimation, connected components generation and smearing on a hypercube architecture. These algorithms have been tested on PARAM CAMPUS (a 16-node parallel machine) and the test results have been provided.

Augmented binary hypercube: a new architecture for processor management

Augmented Binary Hypercube (AH) architecture consists of the binary hypercube processor nodes (PNs) and a hierarchy of management nodes (MNs). Several distributed algorithms maintain subcube information at the MNs to realize fault tolerant, fragmentation free processor allocation and load balancing. For efficient implementation of AH, we map MNs onto PNs, define and prove infeasibility of ideal mappings. We propose easily implementable nonoptimal mappings, having negligible overheads on performance. Extensive simulation studies and performance analysis conclude that these algorithms realize significantly better average job completion time and higher processor utilization, as compared to the best sequential allocation schemes and parallel implementation of Free List. AH algorithms can be tuned or adapt to the job and system characteristics, and resource management traffic.

Parallel Computing of Physical Maps— A Comparative Study in SIMD and MIMD Parallelism

Ordering clones from a genomic library into physical maps of whole chromosomes presents a central computational problem in genetics. Chromosome reconstruction via clone ordering is usually isomorphic to the NP-complete Optimal Linear Arrangement problem. Parallel SIMD and MIMD algorithms for simulated annealing based on Markov chain distribution are proposed and applied to the problem of chromosome reconstruction via clone ordering. Perturbation methods and problem-specific annealing heuristics are proposed and described. The SIMD algorithms are implemented on a 2048 processor MasPar MP-2 system which is an SIMD 2-D toroidal mesh architecture whereas the MIMD algorithms are implemented on an 8 processor Intel iPSC/860 which is an MIMD hypercube architecture. A comparative analysis of the various SIMD and MIMD algorithms is presented in which the convergence, speedup, and scalability characteristics of the various algorithms are analyzed and discussed. On a fine-grained, massively parallel SIMD architecture with a low synchronization overhead such as the MasPar MP-2, a parallel simulated annealing algorithm based on multiple periodically interacting searches performs the best. For a coarse-grained MIMD architecture with high synchronization overhead such as the Intel iPSC/860, a parallel simulated annealing algorithm based on multiple independent searches yields the best results. In either case, distribution of clonal data across multiple processors is shown to exacerbate the tendency of the parallel simulated annealing algorithm to get trapped in a local optimum.