Hybrid Processors Research Articles

Robust hybrid beamforming designs for full-duplex OFDM millimeter wave systems with imperfect channel estimates

In this paper, robust hybrid beamforming designs are developed for full-duplex millimeter wave multiple-input multiple-output orthogonal frequency division multiplexing (OFDM) systems. A zero-space projection based method is proposed to attenuate the self-interference. The imperfect channel estimations are considered to design the robust full digital beamformers. Then, the hybrid processors are solved via an alternating algorithm. The simulation results show that the proposed design prevails the existing designs.

Robust hybrid beamforming in full-duplex broadband mmWave relay systems

In this paper, the robust hybrid beamforming scheme in full-duplex (FD) millimeter-wave (mmWave) relay systems is designed under imperfect channel estimates. The inherent characteristic of mmWave signals, i.e., the large available bandwidth, is considered in the design, and the orthogonal frequency division multiplexing (OFDM) technique is utilized to overcome the multipath fading. A self-interference cancellation module is inserted at the relay to attenuate the self-interference, which is the main challenge of the FD mode. A decomposition algorithm for mmWave OFDM relay systems is proposed to obtain the hybrid processors with analog-digital-analog structures and closed-form least-squared-based solutions. Numerical results show that the proposed design provides significant improvements by comparing with existing designs.

MmWave relay systems with robust hybrid transceiver designs under correlated channel estimation errors

In this paper, we incorporate mmWave systems with relay techniques to propose a hybrid transceiver design approach. The existing researches of hybrid transceiver designs mostly rely on accurate channel state information acquisitions. However, it is hard to avoid estimation errors in practice, which motivates us to propose a robust design based on imperfect channel estimations. We first design the fully digital processors and then decompose them into hybrid ones. An alternating algorithm is proposed to solve the fully digital processors by utilizing the relationship between the maximization of the upper bound of the averaged mutual information and the weighted minimum mean squared error problem. A decomposition algorithm with closed-form solutions is also proposed to obtain hybrid processors with analog-digital-analog structure at the relay terminal. Compared with related works, the proposed decomposition algorithm outperforms existing decomposition methods under imperfect CSI condition and the proposed hybrid design sacrifices certain complexity to achieve obvious performance improvements, which are illustrated by numerical simulations.

Robust Hybrid Precoding/Combining Designs for Full-Duplex Millimeter Wave Relay Systems

In this article, we propose hybrid precoding/combining designs for full-duplex amplify-and-forward millimeter wave relay systems. The imperfect channel estimations induced by applicable estimation techniques are considered to develop robust fully digital transceivers. A zero-space self-interference (SI) cancellation method is proposed to attenuate the SI. An alternating method with closed-form solutions is utilized to solve the hybrid processors. Simulation results show that the proposed design is close to the fully digital solutions and prevails the existing designs.

Robust Hybrid Beamforming in Millimeter Wave Systems With Closed-Form Least-Square Solutions

Robust hybrid beamforming is developed for millimeter wave multiple-input multiple-output (MIMO) systems. The channel state information (CSI) with correlated estimation errors is used for averaging the mutual information formulation. It is proved that the robust hybrid beamforming scheme can be solved via an Euclidean distance minimization problem as the design with the perfect CSI assumption. An alternating method is proposed to solve the hybrid processors with closed-form least-square solutions in each iteration. Simulation results show that the proposed beamforming scheme prevails existing hybrid beamforming designs.

Prospects for creating a laser nanolithography system for tasks of diffractive optics and nanophotonics

This paper considers the basic concepts of constructing an advanced direct laser writing nanolithographic system dedicated to a high-resolution synthesis of large-sized planar elements of diffractive optics and nanophotonics. The issues of the rational implementation of optical, mechanical and electronic units of the system are solved together with considering the functional structure for a precise computer control of the mentioned units. The proposed design of the opto-mechanical unit aims to reduce significantly the distortions of fabrication of the optical elements due to the use of a new symmetrical two-channel construction and a differential laser interferometer for the radial positioning of a focused laser beam. A complex of issues on constructing a long-working distance superresolving focusing system are also considered alongside. The complex modernization of the nanolithographic system software and hardware complex based on system-on-chip (SoC) using hybrid processors (FPGA+ARM) is considered, which will make the system more universal and portable to various IT platforms.

PowerChop

On-core microarchitectural structures consume significant portions of a processor's power budget. However, depending on application characteristics, those structures do not always provide (much) performance benefit. While timeout-based power gating techniques have been leveraged for underutilized cores and inactive functional units, these techniques have not directly translated to high-activity units such as vector processing units, complex branch predictors, and caches. The performance benefit provided by these units does not necessarily correspond with unit activity, but instead is a function of application characteristics. This work introduces P ower C hop , a novel technique that leverages the unique capabilities of HW/SW co-designed hybrid processors to enact unit-level power management at the application phase level. P ower C hop adds two small additional hardware units to facilitate phase identification and triggering different power states, enabling the software layer to cheaply track, predict and take advantage of varying unit criticality across application phases by powering gating units that are not needed for performant execution. Through detailed experimentation, we find that P ower C hop significantly decreases power consumption, reducing the leakage power of a hybrid server processor by 9% on average (up to 33%) and a hybrid mobile processor by 19% (up to 40%) while introducing just 2% slowdown.

Improved hearing in noise using new signal processing algorithms with the Cochlear™ Nucleus® 6 sound processor

ObjectiveTo demonstrate the performance benefit of the Automatic Scene Classifier (SCAN) algorithm available in the Nucleus® 6 (CP900 series) sound processor over the default processing algorithms of the previous generation Nucleus 5 (CP810) and Freedom® Hybrid™ sound processors. MethodsEighty-two cochlear implant recipients (40 Nucleus 5 processor users and 42 Freedom Hybrid processor users) listened to and repeated AzBio sentences in noise with their current processor and with the Nucleus 6 processor. ResultsThe SCAN algorithm when enabled yielded statistically significant non-inferior and superior performance when compared to the Nucleus 5 and Freedom Hybrid sound processors programmed with ASC + ADRO®. ConclusionThe results of these studies demonstrate the superior performance and clinical utility of the SCAN algorithm in the Nucleus 6 processor over the Nucleus 5 and Freedom Hybrid processors.

Hybrid Cache Designs for Reliable Hybrid High and Ultra-Low Voltage Operation

Geometry scaling of semiconductor devices enables the design of ultra-low-cost (e.g., below 1 USD) battery-powered resource-constrained ubiquitous devices for environment, urban life, and body monitoring. These sensor-based devices require high performance to react in front of infrequent particular events as well as extreme energy efficiency in order to extend battery lifetime during most of the time when low performance is required. In addition, they require real-time guarantees. The most suitable technological solution for these devices consists of using hybrid processors able to operate at: (i) high voltage to provide high performance and (ii) near-/subthreshold voltage to provide ultra-low energy consumption. However, the most efficient SRAM memories for each voltage level differ and trading off different SRAM designs is mandatory. This is particularly true for cache memories, which occupy most of the processor's area. In this article, we propose new, simple, single-Vcc-domain hybrid L1 cache architectures suitable for reliable hybrid high and ultra-low voltage operation. In particular, the cache is designed by combining heterogeneous SRAM cell types: some of the cache ways are optimized to satisfy high-performance requirements during high voltage operation, whereas the rest of the ways provide ultra-low energy consumption and reliability during near-/subthreshold voltage operation. We analyze the performance, energy, and power impact of the proposed cache designs when using them to implement L1 caches in a processor. Experimental results show that our hybrid caches can efficiently and reliably operate across a wide range of voltages, consuming little energy at near-/subthreshold voltage as well as providing high performance at high voltage without decreasing reliability levels to provide strong performance guarantees, as required for our target market.

Hybrid Dataflow/von-Neumann Architectures

General purpose hybrid dataflow/von-Neumann architectures are gaining attraction as effective parallel platforms. Although different implementations differ in the way they merge the conceptually different computational models, they all follow similar principles: they harness the parallelism and data synchronization inherent to the dataflow model, yet maintain the programmability of the von-Neumann model. In this paper, we classify hybrid dataflow/von-Neumann models according to two different taxonomies: one based on the execution model used for inter- and intrablock execution, and the other based on the integration level of both control and dataflow execution models. The paper reviews the basic concepts of von-Neumann and dataflow computing models, highlights their inherent advantages and limitations, and motivates the exploration of a synergistic hybrid computing model. Finally, we compare a representative set of recent general purpose hybrid dataflow/von-Neumann architectures, discuss their different approaches, and explore the evolution of these hybrid processors.

Leveraging hardware message passing for efficient thread synchronization

As the level of parallelism in manycore processors keeps increasing, providing efficient mechanisms for thread synchronization in concurrent programs is becoming a major concern. On cache-coherent shared-memory processors, synchronization efficiency is ultimately limited by the performance of the underlying cache coherence protocol. This paper studies how hardware support for message passing can improve synchronization performance. Considering the ubiquitous problem of mutual exclusion, we adapt two state-of-the-art solutions used on shared-memory processors, namely the server approach and the combining approach, to leverage the potential of hardware message passing. We propose HybComb, a novel combining algorithm that uses both message passing and shared memory features of emerging hybrid processors. We also introduce MP-Server, a straightforward adaptation of the server approach to hardware message passing. Evaluation on Tilera's TILE-Gx processor shows that MP-Server can execute contended critical sections with unprecedented throughput, as stalls related to cache coherence are removed from the critical path. HybComb can achieve comparable performance, while avoiding the need to dedicate server cores. Consequently, our queue and stack implementations, based on MP-Server and HybComb, largely outperform their most efficient pure-shared-memory counterparts.

BlockChop

Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative optimization. As we move to a multicore hybrid design, fine grained conflicts for shared data can violate the atomicity requirement of these blocks and lead to expensive squashes and rollbacks. However, as these atomic regions differ from those used in checkpointing and transactional memory systems, the extent of this potentially prohibitive problem remains unclear, and mechanisms to mitigate these squashes dynamically may be critical to enable a highly per-formant multicore hybrid design. In this work, we investigate how multithreaded applications, both benchmark and commercial workloads, are affected by squashes, and present dynamic mechanisms for mitigating these squashes in hybrid processors. While the current wisdom is that there is not a significant number of squashes for smaller atomic regions, we observe this is not the case for many multithreaded workloads. With region sizes of just 200--500 instructions, we observe a performance degradation ranging from 10% to more than 50% for workloads with a mixture of shared reads and writes. By harnessing the unique flexibility provided by the software subsystem of hybrid processor design, we present BlockChop , a framework for dynamically mitigating squashes on multicore hybrid processors. We present a range of squash handling mechanisms leveraging retrials, interpretation, and retranslation, and find that BlockChop is quite effective. Over the current response to exceptions and squashes in a hybrid design, we are able to improve the performance of benchmark and commercial workloads by 1.4x and 1.2x on average for large and small region sizes respectively.

Design and implementation of a hybrid sub-band acoustic echo canceller (AEC)

An efficient method is presented for implementing an acoustic echo canceller (AEC) that makes use of hybrid sub-band approach. The hybrid system is comprised of a fixed processor and an adaptive filter in each sub-band. The AEC aims at reducing the echo resulting from the acoustic feedback in loudspeaker-enclosure-microphone (LEM) systems such as teleconferencing and hands-free systems. In order to cancel the acoustical echo efficiently, various processing architectures including fixed filters, hybrid processors, and sub-band structure are investigated. A double-talk detector is incorporated into the proposed AEC to prevent the adaptive filter from diverging in double-talk situations. A de-correlation filter is also used alongside sub-band processing in order to enhance the performance and efficiency of AEC. All algorithms are implemented and verified on the platform of a fixed-point digital signal processor (DSP). The AECs are evaluated in terms of cancellation performance and computation complexity. In addition, listening tests are conducted to assess the subjective performance of the AECs. From the results, the proposed hybrid sub-band AEC was found to be the most effective among all methods in terms of echo reduction and timbral quality.