Hybrid Number System Research Articles

Hybrinomials Related to Hyper-Fibonacci and Hyper-Lucas Numbers

Hybrid number system is a generalization of complex, hyperbolic and dual numbers. Hybrid numbers and hybrid polynomials have been the subject of much research in recent years. In this paper, hybrinomials related to hyper-Fibonacci and hyper-Lucas numbers are defined. Then some algebraic properties of newly defined hybrinomials are examined such as the recurrence relations and summation formulas. Also, the relation between hybrinomials related to hyper-Fibonacci and hyper-Lucas numbers is given. Additionally, hybrid hyper-Fibonacci and hybrid hyper-Lucas numbers are defined by using the hybrinomials related to hyper-Fibonacci and hyper-Lucas numbers.

Multicomponent hybrid numbers: On algebraic properties and matrix representations of hybrid-hyperbolic numbers

In this study, the hybrid-hyperbolic numbers are introduced. This number system is a more general form of the hybrid number system, which is an interesting number system, as well as a number system that includes multicomponent number systems (i.e., complex-hyperbolic, dual-hyperbolic and bihyperbolic numbers). In this paper, we give algebraic properties of hybrid-hyperbolic numbers. In addition, 2 × 2 and 4 × 4 hyperbolic matrix representations of hybrid-hyperbolic numbers are given and some properties of them are examined.

Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System

The world of 3D graphic computing has undergone a revolution in the recent past, making devices more computationally intensive, providing high-end imaging to the user. The OpenGL ES Standard documents the requirements of graphic processing unit. A prime feature of this standard is a special function unit (SFU), which performs all the required mathematical computations on the vertex information corresponding to the image. This paper presents a low-cost, high-performance SFU architecture with improved speed and reduced area. Hybrid number system is employed here in order to reduce the complexity of operations by suitably switching between logarithmic number system (LNS) and binary number system (BNS). In this work, reduction of area and a higher operating frequency are achieved with almost the same power consumption as that of the existing implementations.

Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications

Low Complexity Logarithmic and Anti-Logarithmic Converters for Hybrid Number System Processors and DSP Applications

Power and Area-Efficient Unified Computation of Vector and Elementary Functions for Handheld 3D Graphics Systems

A unified computation method of vector and elementary functions is proposed for handheld 3D graphics systems. It unifies vector operations like vector multiply, multiply-and-add, divide, divide-by-square-root, and dot product and elementary functions like trigonometric, inverse trigonometric, hyperbolic, inverse hyperbolic, power (xy with two variables), and logarithm to an arbitrary base into a single four-way arithmetic platform. A number system called the fixed-point hybrid number system (FXP-HNS), which combines the fixed-point number system (FXP) and the logarithmic number system (LNS), is proposed for the power and area-efficient unification. Power and area-efficient logarithmic and antilogarithmic conversion schemes are also proposed for the data conversions between fixed-point and logarithmic numbers in the FXP-HNS and achieve 0.41 percent and 0.08 percent maximum conversion errors, respectively. The unified arithmetic unit based on the proposed schemes is presented with less than 6.3 percent operation error. Its fully pipelined architecture achieves single-cycle throughput with maximum four-cycle latency for all of the supported operations. Comparison results show that the proposed arithmetic unit achieves 30 percent power and 10.9 percent area reductions and runs two times faster than the previous approach.

The efficient implementation and analysis of a hybrid number system processor

A hybrid number system processor designed with the antilogarithm programmable logic array (PLA) is described. In the hybrid number system, linear interpolation is used to achieve accurate conversions between floating-point (FLP) and logarithmic number system (LNS) numbers. Originally, a multiplier was used to do the interpolation. Here, the antilogarithm PLA is shown to have smaller silicon area, comparable overall performance, and structured design. The basic arithmetic operations and processor architecture are explained for performing addition, subtraction, multiplication, division, and square root. The conversion errors are analyzed mathematically. The Taylor series approximation is used as the framework for analysis of the conversion errors of logarithm, antilogarithm, multiplication/division, and addition/subtraction operations. The analyses indicate that the Taylor series truncation results in very small error when the ROM size is properly chosen for the desired precision. Consequently, the finite width truncation becomes the major source of conversion errors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 10 ns hybrid number system data execution unit for digital signal processing systems

A high-performance data execution unit suitable for computation-intensive digital signal processing systems is described. This unit uses the hybrid number system approach to speed up the basic arithmetic operations while remaining compatible with a standard IEEE 32-b floating-point format. However, all the arithmetic operations are performed in the 32 b logarithmic number system (LNS) domain. This chip is designed using a 3.4 V 0.8 mu m CMOS technology with double-layer metallization. Conversion algorithms, chip architecture, design methodology, and major circuit components are discussed. A macrocell design methodology is adopted in order to achieve high-performance custom design circuits with the convenience of an automatic layout system. Computer simulations indicate that all the 32 b floating-point arithmetic operations (multiplication, division, squaring, and square root) can be executed in 10 ns. Extension of this unit into a 64 b double-precision floating-point system and multiply-accumulation applications are also presented.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A hybrid number system processor with geometric and complex arithmetic capabilities

The architecture, design, and performance of a hybrid number system processor are described. The processor performs multiplication, division, square root, and square in the logarithmic number system (LNS) domain. However, the input, output, addition, and subtraction are all executed in the 32-b IEEE standard floating-point number system. With the LNS multiplier and pipelined architecture, the processor is able to perform the geometric and complex arithmetic very effectively. The processor is also shown to compare well to an existing 32-b floating-point DSP (digital signal processor) chip. For the same level of CMOS technology, the performance ratios between the hybrid number system and the floating-point processor are shown to be 6.4:1 and 8:1 for division and square root, respectively; for the complex FFT (fast Fourier transform) algorithm, the ratio is around 2:1. >