Hybrid Memory Research Articles

Resistive switching memory device with metal‐oxide quantum dots on a graphene layer

We demonstrate a one diode–one resistor (1D–1R) type resistive switching memory device consisting of single layered metal‐oxide quantum dots (QDs) and a vertically inserted graphene layer between the SiO2 layers on an n+‐Si substrate. Mono‐layered graphene on the bottom SiO2 layer with a thickness of 50 nm was capped by a 5 nm thick SiO2 top barrier layer deposited by using an ultra‐high vacuum sputter. The In2O3 QDs layer embedded in the 50 nm thick biphenyltetracarboxylic dianhydride‐phenylenediamine polymer layer was formed by a curing process using polyamic acid at 400 °C for 1 h. The current values of the high and low resistance states for this 1D–1R device were measured to be about 3.32 × 10−9 and 5.54 × 10−9 A at a read bias of 1 V, respectively. The ratio of each resistance after applying sweeping bias from +8 to −8 V and from −8 to +8 V appeared to be about 0.59 at 1 V. This resistance switching could have originated from the migration of the O−2 ions by the redox chemical reaction in the polyimide and carrier charging effect of the QDs. This hybrid memory structure with In2O3 QDs and graphene layer has a strong possibility for application in next generation nonvolatile memory devices.

You look familiar, but I don't care: Lure rejection in hybrid visual and memory search is not based on familiarity.

In "hybrid" search tasks, observers hold multiple possible targets in memory while searching for those targets among distractor items in visual displays. Wolfe (2012) found that, if the target set is held constant over a block of trials, reaction times (RTs) in such tasks were a linear function of the number of items in the visual display and a linear function of the log of the number of items held in memory. However, in such tasks, the targets can become far more familiar than the distractors. Does this "familiarity"- operationalized here as the frequency and recency with which an item has appeared-influence performance in hybrid tasks In Experiment 1, we compared searches where distractors appeared with the same frequency as the targets to searches where all distractors were novel. Distractor familiarity did not have any reliable effect on search. In Experiment 2, most distractors were novel but some critical distractors were as common as the targets while others were 4× more common. Familiar distractors did not produce false alarm errors, though they did slightly increase RTs. In Experiment 3, observers successfully searched for the new, unfamiliar item among distractors that, in many cases, had been seen only once before. We conclude that when the memory set is held constant for many trials, item familiarity alone does not cause observers to mistakenly confuse target with distractors.

Data Allocation for Hybrid Memory With Genetic Algorithm

The gradually widening speed disparity between CPU and memory has become an overwhelming bottleneck for the development of chip multiprocessor systems. In addition, increasing penalties caused by frequent on-chip memory accesses have raised critical challenges in delivering high memory access performance with tight power and latency budgets. To overcome the daunting memory wall and energy wall issues, this paper focuses on proposing a new heterogeneous scratchpad memory architecture, which is configured from SRAM, MRAM, and Z-RAM. Based on this architecture, we propose a genetic algorithm to perform data allocation to different memory units, therefore, reducing memory access cost in terms of power consumption and latency. Extensive and experiments are performed to show the merits of the heterogeneous scratchpad architecture over the traditional pure memory system and the effectiveness of the proposed algorithms.

Who Is Censoring Whom? An Enquiry into the Right to Be Forgotten and Censorship

The 'right to be forgotten' has been labelled as censorship and disastrous for the freedom of expression. In this paper, we will claim that effecting the right to be forgotten with regard to search results is a 'censorship' on the level of the retrieval of information. We will however also claim it is the least heavy yet most effective means to get an overall minimum amount of censorship, while additionally enabling people to evolve beyond their past opinions. We will show that in applying something like a 'right to be forgotten,' it is not a question of just 'censoring' search engines, but that seen from a broader perspective we -- as society -- will inevitably have to choose between three types of 'censorship': (1) censorship of original sources, that is on the level of information storage; (2) censorship on the level in which information is encoded in the first place; or (3) censorship on the level of information retrieval. These three levels on which 'censorship' can take place are the three basic elements of the memory process; whether biological, electronic, or hybrid with the use of mnemonic technologies. Applying censorship as a means of 'forgetting' in the collective hybrid memory of the Web enables us to counter -- at least partially -- a possible suppressing functioning of the Web as a 'Panonticon over Time.'

Design challenges in Interposer based 3-D Memory Logic Interface

Further improvements in system performance are often limited by the achievable bandwidth between processor and memory. In this paper we look at interposer-based and stacked solutions to integrate processor and 3D memory into a high performance system. The comparison is made for different technological decisions, design problems faced for choosing a certain 3D memory type from Wide IO/1–2, High bandwidth memory (HBM) and Hybrid Memory Cube (HMC). Logic die size, metal layers and material of interposer affected by routing requirements of memory systems are discussed.

The rise and fall of hybrid visual and memory search

In hybrid search, observers search through arrays of visually presented items for any of a set of targets held in memory; think of looking on a store shelf for items on your grocery list, searching luggage x-rays for potential banned items, or chest x-rays for signs of cancer. As the size of the memory sets used in hybrid search increased, descriptions of the RT by set size function moved from linear (Shiffrin & Schneider, 1977) to logarithmic (Wolfe, 2012). In order to study hybrid search at larger set sizes, with greater resolution, and as a function of expertise, I utilized the Airport Scanner (Kedlin Co., www.airportscannergame.com) dataset (see Mitroff and Biggs 2014). Airport Scanner is a game for mobile devices, which simulates searching through baggage x-rays for threats under time constraints. Players move through five ranks as they acquire game expertise, from Trainee to Elite. Critically, new items are added to the list of potential threats as the game progresses. Eliminating trainees to reduce potential learning effects, I analyzed only trials (bags) with a single target. This left 3,491,664 trials from 18,595 players. Memory set size(potential threats) ranged from 3 to 155 items. Visual set size had no influence on performance. For set sizes from 6-12, the logarithmic relationship held. However, across the full range of set sizes, at all expertise levels, reaction time was best described as a quadratic, rather than logarithmic, function of set size. For the low expertise groups, the curve opened upward, while at high expertise, it opened downward. These data suggest that encoding and retrieval strategies in hybrid search change in a complex fashion as the size of the memory set increases, and as observers gain more expertise with the task. Models developed for small set sizes may not generalize to realistically large set sizes. Meeting abstract presented at VSS 2015. Language: en

Exploiting Page Write Pattern for Power Management of Hybrid DRAM/PRAM Memory System.

The main memory has become a power bottleneck for computer systems. To reduce the energy dissipation of main memory, the non-volatile phase-change RAM (PRAM) has emerged as one of the promising memories due to its high density and low standby power. But PRAM has its intrinsic disadvantages of long write latency and high write energy. Hence, the hybrid DRAM/PRAM main memory is proposed to provide the advantage of low standby power of PRAM as well as high performance and low access power of DRAM. Data management, such as migrating frequently accessed data from PRAM to DRAM, is widely employed by past work to achieve the benefits of both DRAM and PRAM. But the past work is oblivious to the data migration energy overhead, which is considerable as confirmed by our study. In this work, we studied the page write access pattern of pages within and across applications and observed that two pattern widely exist, namely write-average and write-cluster. We then propose an adaptive page migration strategy (APMS) that migrates data of a page based on its write pattern to reduce the migration energy in DRAM/PRAM hybrid memory system. Our APMS exploits the write pattern of a page and determines the amount of data that should be migrated against the existing page-level data migration strategy. Experiments were conducted to verify the validity of the strategy. The results show that APMS can reduce the energy consumption of most applications with negligible performance impact and energy overhead.

Hybrid Main Memory for High Bandwidth Multi-Core System

In the hybrid main memory sub-system which consists of DRAM and phase change RAM (PRAM), DRAM is often used as a cache. Such a configuration of DRAM cache and PRAM main memory has two problems. First, it requires high bandwidth of data movement between DRAM and PRAM due to the large granularity (i.e., DRAM row) of caching. Second, the memory bandwidth of PRAM is not fully utilized since it can be accessed only by the DRAM cache thereby limiting the memory bandwidth of hybrid main memory to that of DRAM cache. In this paper, we propose a novel architecture where both DRAM and PRAM can be accessed in parallel for higher memory performance. We analyze that the performance and fairness of hybrid memory sub-system is limited by the stall time at the data queue of memory controller. In order to resolve this problem, we propose caching data selectively in a way to reduce stall time thereby reducing memory access latency and improving fairness. Our experimental results show significant improvements in performance (by an average of 21 percent), fairness (by 2.1 times), and energy consumption (by 10 percent) compared with the best of the existing methods in a multi-core system which consists of multiple CPUs and GPU.

Safe and efficient hybrid memory management for Java

Java uses automatic memory management, usually implemented as a garbage-collected heap. That lifts the burden of manually allocating and deallocating memory, but it can incur significant runtime overhead and increase the memory footprint of applications. We propose a hybrid memory management scheme that utilizes region-based memory management to deallocate objects automatically on region exits. Static program analysis detects allocation sites that are safe for region allocation, i.e., the static analysis proves that the objects allocated at such a site are not reachable after the region exit. A regular garbage-collected heap is used for objects that are not region allocatable. The region allocation exploits the temporal locality of object allocation. Our analysis uses coarse-grain source code annotations to disambiguate objects with non-overlapping lifetimes, and maps them to different memory scopes. Region-allocated memory does not require garbage collection as the regions are simply deallocated when they go out of scope. The region allocation technique is backed by a garbage collector that manages memory that is not region allocated. We provide a detailed description of the analysis, provide experimental results showing that as much as 78% of the memory is region allocatable and discuss how our hybrid memory management system can be implemented efficiently with respect to both space and time.

Coherence protocol for transparent management of scratchpad memories in shared memory manycore architectures

The increasing number of cores in manycore architectures causes important power and scalability problems in the memory subsystem. One solution is to introduce scratchpad memories alongside the cache hierarchy, forming a hybrid memory system. Scratchpad memories are more power-efficient than caches and they do not generate coherence traffic, but they suffer from poor programmability. A good way to hide the programmability difficulties to the programmer is to give the compiler the responsibility of generating code to manage the scratchpad memories. Unfortunately, compilers do not succeed in generating this code in the presence of random memory accesses with unknown aliasing hazards. This paper proposes a coherence protocol for the hybrid memory system that allows the compiler to always generate code to manage the scratchpad memories. In coordination with the compiler, memory accesses that may access stale copies of data are identified and diverted to the valid copy of the data. The proposal allows the architecture to be exposed to the programmer as a shared memory manycore, maintaining the programming simplicity of shared memory models and preserving backwards compatibility. In a 64-core manycore, the coherence protocol adds overheads of 4% in performance, 8% in network traffic and 9% in energy consumption to enable the usage of the hybrid memory system that, compared to a cache-based system, achieves a speedup of 1.14x and reduces on-chip network traffic and energy consumption by 29% and 17%, respectively.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

Universal Magnetic Hall Circuit Based on Paired Spin Heterostructures

The merit of advanced hybrid memory and logic devices not only lies in their high performance and superior functionalities but also their capability to establish a complete computational system, including full memory and logic functionalities. In this paper, a novel, ultrahigh‐performance device concept for hybrid memory and logic applications is presented, which relies on spin‐based magnetic Hall measurements. Employing a pair of spintronic heterostructures, the new system shows flexible functionality as both a robust memory element and a complex logic device. The building blocks of this universal magneto‐Hall circuit are experimentally demonstrated, based on the paired heterostructures. Combined with a new type of circuit, this design paves the way for robust room‐temperature spintronics.

Searching for the right word: Hybrid visual and memory search for words.

In "hybrid search" (Wolfe Psychological Science, 23(7), 698-703, 2012), observers search through visual space for any of multiple targets held in memory. With photorealistic objects as the stimuli, response times (RTs) increase linearly with the visual set size and logarithmically with the memory set size, even when over 100 items are committed to memory. It is well-established that pictures of objects are particularly easy to memorize (Brady, Konkle, Alvarez, & Oliva Proceedings of the National Academy of Sciences, 105, 14325-14329, 2008). Would hybrid-search performance be similar if the targets were words or phrases, in which word order can be important, so that the processes of memorization might be different? In Experiment 1, observers memorized 2, 4, 8, or 16 words in four different blocks. After passing a memory test, confirming their memorization of the list, the observers searched for these words in visual displays containing two to 16 words. Replicating Wolfe (Psychological Science, 23(7), 698-703, 2012), the RTs increased linearly with the visual set size and logarithmically with the length of the word list. The word lists of Experiment 1 were random. In Experiment 2, words were drawn from phrases that observers reported knowing by heart (e.g., "London Bridge is falling down"). Observers were asked to provide four phrases, ranging in length from two words to no less than 20 words (range 21-86). All words longer than two characters from the phrase, constituted the target list. Distractor words were matched for length and frequency. Even with these strongly ordered lists, the results again replicated the curvilinear function of memory set size seen in hybrid search. One might expect to find serial position effects, perhaps reducing the RTs for the first (primacy) and/or the last (recency) members of a list (Atkinson & Shiffrin, 1968; Murdock Journal of Experimental Psychology, 64, 482-488, 1962). Surprisingly, we showed no reliable effects of word order. Thus, in "London Bridge is falling down," "London" and "down" were found no faster than "falling."

Temperature-Aware Data Allocation for Embedded Systems with Cache and Scratchpad Memory

The hybrid memory architecture that contains both on-chip cache and scratchpad memory (SPM) has been widely used in embedded systems. In this article, we explore this hybrid memory architecture by jointly optimizing time performance and temperature for embedded systems with loops. Our basic idea is to adaptively adjust the workload distribution between cache and SPM based on the current temperature. For a problem in which the workload can be estimated a priori, we present a nonlinear programming formulation to optimally minimize the total execution time of a loop under the constraints of SPM size and temperature. To solve a problem in which the workload is not known a priori, we propose a temperature-aware adaptive loop scheduling algorithm called TALS to dynamically allocate data to cache and SPM at runtime. The experimental results show that our algorithms can effectively achieve both performance and temperature optimization for embedded systems with cache and SPM.

Active Memory Cube: A processing-in-memory architecture for exascale systems

Many studies point to the difficulty of scaling existing computer architectures to meet the needs of an exascale system (i.e., capable of executing $10^{18} $ floating-point operations per second), consuming no more than 20 MW in power, by around the year 2020. This paper outlines a new architecture, the Active Memory Cube, which reduces the energy of computation significantly by performing computation in the memory module, rather than moving data through large memory hierarchies to the processor core. The architecture leverages a commercially demonstrated 3D memory stack called the Hybrid Memory Cube, placing sophisticated computational elements on the logic layer below its stack of dynamic random-access memory (DRAM) dies. The paper also describes an Active Memory Cube tuned to the requirements of a scientific exascale system. The computational elements have a vector architecture and are capable of performing a comprehensive set of floating-point and integer instructions, predicated operations, and gather-scatter accesses across memory in the Cube. The paper outlines the software infrastructure used to develop applications and to evaluate the architecture, and describes results of experiments on application kernels, along with performance and power projections.

Runtime Thermal Management for 3-D Chip-Multiprocessors With Hybrid SRAM/MRAM L2 Cache

Nonvolatile memory such as magnetic RAM (MRAM) offers high cell density and low leakage power while suffering from long write latency and high write energy, compared with SRAM. 3-D integration technology using through-silicon vias enables stacking disparate memory technologies (e.g., SRAM and MRAM) together onto chip-multiprocessors (CMPs). The use of hybrid memories as an on-chip cache can take advantage of the best characteristics that each technology offers. However, the inherent high power density and heat removal limitation in 3-D integrated circuits may incur temperature-related problems. In this paper, we propose a runtime thermal management method for CMPs with the 3-D stacked hybrid SRAM/MRAM L2 cache. The proposed method combines dynamic cache management such as resource allocation, way-based power gating, and data migration with dynamic voltage and frequency scaling of processing cores in a temperature- and energy-aware manner. Experimental results show that the proposed runtime method with the 3-D stacked hybrid L2 cache offers up to 107.37% (55.28% on average) performance improvement and 88.47% (47.65% on average) energy efficiency improvement compared with existing thermal management methods with 3-D stacked SRAM-based L2 cache.

Preparing non-volatile resistive switching memories by tuning the content of Au@air@TiO2-h yolk-shell microspheres in a poly(3-hexylthiophene) layer.

Crystalline hybrid microspheres, encapsulating a Au nanocore in the hollow cavity of a hairy semiconductor TiO2 shell (Au@air@TiO2-h microspheres) were prepared using template-assisted synthesis methods. The as-prepared microspheres are dispersed into a poly(3-hexylthiophene) (P3HT) matrix and used as a memory active layer. The electrical rewritable memory effects of Al/[Au@air@TiO2-h + P3HT]/ITO sandwich devices can be effectively and exactly controlled by tuning the microsphere content in the electroactive layer. To clarify the switching mechanism, different components in the device, such as P3HT and the microspheres, have been investigated. And it was determined that the switching mechanism can be attributed to the formation and rupture of oxygen vacancy filaments. These results suggest that the Au@air@TiO2-h microspheres are potentially capable of high density data storage. In addition, this finding could provide important guidelines for the reproducibility of nanocomposite-based memory devices and is helpful to demonstrate the switching mechanism of these devices.

Childhood-home-injury-situation Simulation Adaptable to an Individual Environment Based on Child Physical Model and Injury Semantic Structure Database

Most accidents involving children below the age of five occur within their homes. Since it is important to maintain a safe home environment for children, it is imperative to be able to predict what kinds of accidents may occur in a particular environment, and then to find ways to improve that environment. However, the various and scattered statistical data sources and scientific knowledge related to accident prediction have not been structured for integrative utilization. In this paper, the authors report on the development of a new simulation technology that can be used to predict the kinds of accidents that may occur in a particular environment by means of a hybrid memory- and model-based approach. The system consists of a graph-structuralized accident database created from large-scale accident data (which enables the memory-based approach), and a development behavior model which describes the statistical relationship between a body interaction abilities and the age of children.

Hardware–Software Coherence Protocol for the Coexistence of Caches and Local Memories

Cache coherence protocols limit the scalability of multicore and manycore architectures and are responsible for an important amount of the power consumed in the chip. A good way to alleviate these problems is to introduce a local memory alongside the cache hierarchy, forming a hybrid memory system. Local memories are more power-efficient than caches and do not generate coherence traffic, but they suffer from poor programmability. When non-predictable memory access patterns are found, compilers do not succeed in generating code because of the incoherence between the two storages. This paper proposes a coherence protocol for hybrid memory systems that allows the compiler to generate code even in the presence of memory aliasing problems. Coherence is ensured by a software/hardware co-design where the compiler identifies potentially incoherent memory accesses and the hardware diverts them to the correct copy of the data. The coherence protocol introduces overheads of 0.26% in execution time and of 2.03% in energy consumption to enable the usage of the hybrid memory system, which outperforms cache-based systems by an speedup of 38% and an energy reduction of 27%.

MTJ-based hybrid storage cells for “normally-off and instant-on” computing

Besides increasing a computing throughput, multi-core processor architectures bring increased capacity of SRAM-based cache memory. As a result, cache memory now occupies large proportion of recent processor chips, becoming a major source of the leakage power consumption. The power gating technique applied on a SRAM cache is not efficient since it is paid by data loss. In this paper, we present two hybrid memory cells that combine a conventional volatile CMOS part with Magnetic Tunnel Junctions (MTJs) able to store a data bit in a non-volatile way. Being inherently non-volatile, these hybrid cells enable instantaneous power off and thus complete reduction of the leakage power. Moreover, given that the data bit can be stored in local MTJs and not in distant storage memories, these cells also offer instantaneous and efficient data retrieval. To demonstrate their functionality, the cells are designed using 28 nm FD-SOI technology for the CMOS part and 45 nm round spin transfer torque MTJs (STT-MTJs) with perpendicular magnetization anisotropy. We report the measured performances of the cells in terms of required silicon area, robustness, read/write speed and energy consumption.