Hybrid Memory Research Articles

Effect of the Oxygen Composition Control of HfOx Films on Threshold and Memory Switching Characteristics for Hybrid Memory Applications

AbstractConsidering a high‐density vertical X‐point memory array, the film thickness of an active device for the selector and memory needs to be scaled down. Here, the authors propose an AgTe/HfOx‐based hybrid memory device with a film thickness of less than 10 nm by adopting a bilayer (HfO1.8/HfO2) film using precise composition control. Non‐volatile switching characteristics can be obtained by considering the formation of stable nanoscale Ag filaments in the nanoporous region in non‐stoichiometric HfO1.8 deposited via sputtering. By contrast, volatile switching characteristics are achieved by an unstable atomic‐scale Ag path in stoichiometric HfO2 deposited via plasma‐enhanced atomic layer deposition. Based on density functional theory calculations, it is confirmed that the stoichiometry of the HfOx film is the key parameter that controls the switching characteristics. The bilayer (HfO1.8/HfO2) device exhibits excellent hybrid memory characteristics, such as distinct read margin (>1.5 V), high ON/OFF ratio (>106), and extremely low OFF current (≈pA), for vertical X‐point memory applications.

Software Hint-Driven Data Management for Hybrid Memory in Mobile Systems

Hybrid memory systems, comprised of emerging non-volatile memory (NVM) and DRAM, have been proposed to address the growing memory demand of current mobile applications. Recently emerging NVM technologies, such as phase-change memories (PCM), memristor, and 3D XPoint, have higher capacity density, minimal static power consumption and lower cost per GB. However, NVM has longer access latency and limited write endurance as opposed to DRAM. The different characteristics of distinct memory classes render a new challenge for memory system design. Ideally, pages should be placed or migrated between the two types of memories according to the data objects’ access properties. Prior system software approaches exploit the program information from OS but at the cost of high software latency incurred by related kernel processes. Hardware approaches can avoid these latencies, however, hardware’s vision is constrained to a short time window of recent memory requests, due to the limited on-chip resources. In this work, we propose OpenMem: a hardware-software cooperative approach that combines the execution time advantages of pure hardware approaches with the data object properties in a global scope. First, we built a hardware-based memory manager unit (HMMU) that can learn the short-term access patterns by online profiling, and execute data migration efficiently. Then, we built a heap memory manager for the heterogeneous memory systems that allows the programmer to directly customize each data object’s allocation to a favorable memory device within the presumed object life cycle. With the programmer’s hints guiding the data placement at allocation time, data objects with similar properties will be congregated to reduce unnecessary page migrations. We implemented the whole system on the FPGA board with embedded ARM processors. In testing under a set of benchmark applications from SPEC 2017 and PARSEC, experimental results show that OpenMem reduces 44.6% energy consumption with only a 16% performance degradation compared to the all-DRAM memory system. The amount of writes to the NVM is reduced by 14% versus the HMMU-only, extending the NVM device lifetime.

An Energy-Efficient DRAM Cache Architecture for Mobile Platforms With PCM-Based Main Memory

A long battery life is a first-class design objective for mobile devices, and main memory accounts for a major portion of total energy consumption. Moreover, the energy consumption from memory is expected to increase further with ever-growing demands for bandwidth and capacity. A hybrid memory system with both DRAM and PCM can be an attractive solution to provide additional capacity and reduce standby energy. Although providing much greater density than DRAM, PCM has longer access latency and limited write endurance to make it challenging to architect it for main memory. To address this challenge, this article introduces CAMP, a novel DRAM c ache a rchitecture for m obile platforms with P CM-based main memory. A DRAM cache in this environment is required to filter most of the writes to PCM to increase its lifetime, and deliver highest efficiency even for a relatively small-sized DRAM cache that mobile platforms can afford. To address this CAMP divides DRAM space into two regions: a page cache for exploiting spatial locality in a bandwidth-efficient manner and a dirty block buffer for maximally filtering writes. CAMP improves the performance and energy-delay-product by 29.2% and 45.2%, respectively, over the baseline PCM-oblivious DRAM cache, while increasing PCM lifetime by 2.7×. And CAMP also improves the performance and energy-delay-product by 29.3% and 41.5%, respectively, over the state-of-the-art design with dirty block buffer, while increasing PCM lifetime by 2.5×.

A Simplified Tantalum Oxide Memristor Model, Parameters Estimation and Application in Memory Crossbars

In this paper, an improved and simplified modification of a tantalum oxide memristor model is presented. The proposed model is applied and analyzed in hybrid and passive memory crossbars in LTSPICE environment and is based on the standard Ta2O5 memristor model proposed by Hewlett–Packard. The discussed modified model has several main enhancements—inclusion of a simplified window function, improvement of its effectiveness by the use of a simple expression for the i–v relationship, and replacement of the classical Heaviside step function with a differentiable and flat step-like function. The optimal values of coefficients of the tantalum oxide memristor model are derived by comparison of experimental current–voltage relationships and by using a procedure for parameter estimation. A simplified LTSPICE library model, correspondent to the analyzed tantalum oxide memristor, is created in accordance with the considered mathematical model. The improved and altered Ta2O5 memristor model is tested and simulated in hybrid and passive memory crossbars for a state near to a hard-switching operation. After a comparison of several of the best existing memristor models, the main pros of the proposed memristor model are highlighted—its improved implementation, better operating rate, and good switching properties.

Unsupervised Cross-Domain Person Re-Identification Method Based on Attention Block and Refined Clustering

Most unsupervised cross-domain person re-identification methods based on clustering suffer from a lack of feature discrimination and clustering generates pseudo-labels noise, leading to a decrease in accuracy. To solve these problems, this paper proposes an unsupervised cross-domain person re-identification method based on attention block and refined clustering. Firstly, ResNet50 is selected as the backbone network, coordinate attention and triple attention are concatenated and embedded in ResNet50 to extract fine-grained features, perform feature aggregation, and mine fine-grained information. Secondly, a refined clustering strategy is proposed to achieve a coarse-to-fine clustering process by designing the measurement standards for clustering, determining its reliability, and eliminating noisy samples. Finally, the hybrid memory bank dynamically stores cluster centers and continues to update them with iterations, adapting to changes in clusters and performing invariant learning. The experimental results show that the new method designed in the paper improves the accuracy of rank-1 and mAP by 0.4% and 2.4%, respectively, on the target domain Market-1501 dataset, and improves the accuracy of rank-1 and mAP by 0.4% and 1.1%, respectively, on the target domain DukeMTMC-ReID dataset, compared with other typical methods.

ALAMNI: Adaptive LookAside Memory based Near-Memory Inference Engine for Eliminating Multiplications in Real-Time

The CNN algorithm seeks high performance and energy efficiency in real-time inference. The costly off-chip memory accesses put additional burdens on CNN's execution. Towards avoiding off-chip accesses, we propose ALAMNI, a novel near-memory architecture that expedites the CNNs in the logic layer of the Hybrid Memory Cube. We exploit intra- and inter-vault parallelism to accelerate the highly parallel CNN operations. The proposed ALAMNI replaces costly multiplications of CNNs with lookaside memory (LAM) based searches. The proposed ALAMNI policy is effective on unseen data as it discards the data pre-profiling overhead by an adaptive LAM update policy. The ALAMNI controller keeps the most frequent triplets of weight (W), activation (A), and multiplication result (M), <W, A, M>, in the LAM to eliminate redundant computations. As an optimization, we incorporate a bitmasking concept to raise the hit rate of LAMs and further amortize computations. We also present a study on the relation between the amount of bitmasking and the loss of classification accuracy of the popular ConvNets. We keep the bitmasking as a reconfigurable feature of the ALAMNI units to achieve desired classification accuracy. Experimental results show substantial improvement in the system's performance and energy efficiency compared to the baseline and state-of-the-art.

Application-Oriented Data Migration to Accelerate In-Memory Database on Hybrid Memory.

With the advantage of faster data access than traditional disks, in-memory database systems, such as Redis and Memcached, have been widely applied in data centers and embedded systems. The performance of in-memory database greatly depends on the access speed of memory. With the requirement of high bandwidth and low energy, die-stacked memory (e.g., High Bandwidth Memory (HBM)) has been developed to extend the channel number and width. However, the capacity of die-stacked memory is limited due to the interposer challenge. Thus, hybrid memory system with traditional Dynamic Random Access Memory (DRAM) and die-stacked memory emerges. Existing works have proposed to place and manage data on hybrid memory architecture in the view of hardware. This paper considers to manage in-memory database data in hybrid memory in the view of application. We first perform a preliminary study on the hotness distribution of client requests on Redis. From the results, we observe that most requests happen on a small portion of data objects in in-memory database. Then, we propose the Application-oriented Data Migration called ADM to accelerate in-memory database on hybrid memory. We design a hotness management method and two migration policies to migrate data into or out of HBM. We take Redis under comprehensive benchmarks as a case study for the proposed method. Through the experimental results, it is verified that our proposed method can effectively gain performance improvement and reduce energy consumption compared with existing Redis database.

Polymerized hybrid Hf-based hydroquinone/Al2O3 bilayer structure by molecular/atomic layer deposition for non-volatile resistive random access memory

In this work, we fabricated the Pt/Hf-based hydroquinone (Hf-HQ)/Al2O3/TiN/Si bilayer hybrid memory by molecular layer deposition/atomic layer deposition. The hybrid memory units exhibit electroforming-free bipolar resistive switching (RS) characteristics with tiny fluctuation of operation voltages within 0.2 V, ON/OFF ratio above 102, and good endurance/retention properties. Meanwhile, the multi-state data storage capability is confirmed in hybrid devices. The RS mechanism based on conducting filaments has been proposed. The favorable linkage and rupture of the conducting filament prefer to occur at the interface of the hybrid Hf-HQ layer and Al2O3 layer, resulting in the brilliant performances. Furthermore, flexible hybrid memory devices fabricated on bendable mica show comparable RS behaviors to the Si-based ones at the bending radius of 7.5 mm, indicative of great potential in flexible multilevel resistive random access memory applications.

An Efficient Sorting Algorithm for Non-Volatile Memory

Non-volatile memory (NVM) has emerged as an alternative of the next-generation memory due to its non-volatility, byte addressability, high storage-density, and low-energy consumption. However, NVM also has some limitations, e.g. asymmetric read and write latency. Therefore, at present, it is not realistic to completely replace DRAM with NVM in computer systems. A more feasible scheme is to adopt the hybrid memory architecture composed of NVM and DRAM. Following the assumption of hybrid memory architecture, in this paper, we propose an NVM-friendly sorting algorithm called NVMSorting. Particularly, we introduce a new concept called Natural Run to improve the existing MONTRES algorithm. Further, we apply the proposed NVMSorting to database join algorithms to improve the performance of the existing sort-merge join. To verify the performance of our proposal, we implement six existing sorting algorithms as baselines, including the MONTRES algorithm, and conduct comparative experiments on real Intel Optane DC persistent memory. The results show that NVMSorting outperforms other sorting algorithms in terms of execution time and NVM writes. In addition, the results of the join experiment show that the NVMSorting algorithm achieves the highest performance among all schemes. Especially, in the partially ordered data, the execution time of NVMSorting is 2.9%, 2.7%, and 4.2% less than MONTRES, external sort, and quick sort, respectively. Also, the amount of NVM writes of the NVMSorting is 26.1%, 43.6%, 96.2% less than MONTRES, external sort, and quick sort, respectively.

Unified Holistic Memory Management Supporting Multiple Big Data Processing Frameworks over Hybrid Memories

To process real-world datasets, modern data-parallel systems often require extremely large amounts of memory, which are both costly and energy inefficient. Emerging non-volatile memory (NVM) technologies offer high capacity compared to DRAM and low energy compared to SSDs. Hence, NVMs have the potential to fundamentally change the dichotomy between DRAM and durable storage in Big Data processing. However, most Big Data applications are written in managed languages and executed on top of a managed runtime that already performs various dimensions of memory management. Supporting hybrid physical memories adds a new dimension, creating unique challenges in data replacement. This article proposes Panthera, a semantics-aware, fully automated memory management technique for Big Data processing over hybrid memories. Panthera analyzes user programs on a Big Data system to infer their coarse-grained access patterns, which are then passed to the Panthera runtime for efficient data placement and migration. For Big Data applications, the coarse-grained data division information is accurate enough to guide the GC for data layout, which hardly incurs overhead in data monitoring and moving. We implemented Panthera in OpenJDK and Apache Spark. Based on Big Data applications’ memory access pattern, we also implemented a new profiling-guided optimization strategy, which is transparent to applications. With this optimization, our extensive evaluation demonstrates that Panthera reduces energy by 32–53% at less than 1% time overhead on average. To show Panthera’s applicability, we extend it to QuickCached, a pure Java implementation of Memcached. Our evaluation results show that Panthera reduces energy by 28.7% at 5.2% time overhead on average.

Highly Available Packet Buffer Design With Hybrid Nonvolatile Memory

Internet routers/switches are vulnerable to system failures which require a power reset. Tremendous efforts are made to guarantee the high availability of the systems. A recent work shows that a phase change memory (PCM)-based routing lookup table can achieve high availability in the destination lookup of routers/switches. However, a packet buffer in routers/switches cannot benefit from the lookup table approach because it requires a much larger and higher-bandwidth memory system and its memory traffic is equally divided into reads and writes, while routing table accesses are mostly read-dominant. PCM can provide high availability even when the system undergoes a power reset but exhibits unacceptable write bandwidth. In this work, we propose a magnetic RAM (MRAM)/PCM-based hybrid memory packet buffer and a packet mapping method. A small MRAM combined with a large PCM can outperform the dynamic random access memory (DRAM)-based packet buffer by 28.5% or 22.4% on average for internet-mix packet traffic when optimizing only bandwidth or both bandwidth and lifetime. The proposed adaptive packet mapping method maps small packets less than a predetermined packet size threshold to MRAM for maximizing PCM bandwidth as small packets degrade row buffer locality in PCM. In addition, the mapping method dynamically changes the packet size threshold to capture the working set of packet buffering, which significantly improves PCM lifetime.

PFHA: A Novel Page Migration Algorithm for Hybrid Memory Embedded Systems

Phase change memory (PCM) and DRAM-based hybrid main memory have emerged as one of the most promising technology for the future embedded systems. Previous research works have focused on page migration strategies to fully exploit the advantages of DRAM and PCM to achieve higher performance and energy efficiency. However, the ability to predict the pages’ future behavior in these strategies could be further improved and most strategies do not consider how to reduce the DRAM energy consumption to further decrease the hybrid system energy. In this article, we propose a novel dynamic hardware migration strategy named periodical frequency hot-region aware page replacement algorithm (PFHA), which utilizes the relation of periodical read and write access frequencies to predict the hotness of a certain page. Meanwhile, PFHA innovatively initiates write hot page self-migration within DRAM to establish a concentrate DRAM write hot region to reduce the DRAM energy. Experiment results confirm that the proposed technique is able to make most of the write hot pages absorbed by DRAM. Meanwhile, it decreases the PCM average access time to a great extent and gets preferable energy consumption.

HEART: H ybrid Memory and E nergy- A ware R eal- T ime Scheduling for Multi-Processor Systems

Dynamic power management (DPM) reduces the power consumption of a computing system when it idles, by switching the system into a low power state for hibernation. When all processors in the system share the same component, e.g., a shared memory, powering off this component during hibernation is only possible when all processors idle at the same time. For a real-time system, the schedulability property has to be guaranteed on every processor, especially if idle intervals are considered to be actively introduced. In this work, we consider real-time systems with hybrid shared-memory architectures, which consist of shared volatile memory (VM) and non-volatile memory (NVM). Energy-efficient execution is achieved by applying DPM to turn off all memories during the hibernation mode. Towards this, we first explore the hybrid memory architectures and suggest a task model, which features configurable hibernation overheads. We propose a multi-processor procrastination algorithm (HEART), based on partitioned earliest-deadline-first (pEDF) scheduling. Our algorithm facilitates reducing the energy consumption by actively enlarging the hibernation time. It enforces all processors to idle simultaneously without violating the schedulability condition, such that the system can enter the hibernation state, where shared memories are turned off. Throughout extensive evaluation of HEART, we demonstrate (1) the increase in potential hibernation time, respectively the decrease in energy consumption, and (2) that our algorithm is not only more general but also has better performance than the state of the art with respect to energy efficiency in most cases.

Heterogeneity-aware Multicore Synchronization for Intermittent Systems

Intermittent systems enable batteryless devices to operate through energy harvesting by leveraging the complementary characteristics of volatile (VM) and non-volatile memory (NVM). Unfortunately, alternate and frequent accesses to heterogeneous memories for accumulative execution across power cycles can significantly hinder computation progress. The progress impediment is mainly due to more CPU time being wasted for slow NVM accesses than for fast VM accesses. This paper explores how to leverage heterogeneous cores to mitigate the progress impediment caused by heterogeneous memories. In particular, a delegable and adaptive synchronization protocol is proposed to allow memory accesses to be delegated between cores and to dynamically adapt to diverse memory access latency. Moreover, our design guarantees task serializability across multiple cores and maintains data consistency despite frequent power failures. We integrated our design into FreeRTOS running on a Cypress device featuring heterogeneous dual cores and hybrid memories. Experimental results show that, compared to recent approaches that assume single-core intermittent systems, our design can improve computation progress at least 1.8x and even up to 33.9x by leveraging core heterogeneity.

Postmortem accurate IR-level state recovery for deployed concurrent programs

Debugging failures of deployed concurrent software is important for quality assurance. However, such failures are difficult to debug because their behavior is non-deterministic and limited information can be obtained with conventional means. Reverse debuggers such as REPT [11] assists with debugging by recovering data values before the failure. This is achieved by using a hardware-tracer to log control-flow information, then using the information and a conventional coredump to recover data values via reverse-execution at machine-level. REPT's algorithm for data value recovery is reliable and fast. But the implementation cost is high because of its dependence on architecture. Applying REPT to more abstract IR (Intermediate Representation) level instructions to counter this yielded limited results with low accuracy compared to the original x86_64 implementation. The main reason for this is that the stack layout is abstracted at IR-level. In this paper, we present STRAB (State Recovery at Abstract-level), a collection of our proposed methods to solve these problems. STRAB works in two phases. First, the data values in the coredump are lifted from machine-level to IR-level using rich debug information (DWARF3) and a novel technique we call mid-recovery lifting, the latter helping to recover more heap data values at IR-level. Second, our novel hybrid memory location resolution reduces the accuracy loss due to the abstracted stack layout at IR-level. Experimental results on a variety of real-world concurrent programs show that STRAB has significantly higher accuracy compared to REPT at IR-level (+40% on average) with only minor slowdowns (x2.7 on average), while also achieving architecture-independence.

Hybrid memory characteristics of NbOx threshold switching devices

By exploiting NbOx, we demonstrate its hybrid memory characteristics, indicating that resistive switching is unified with selector behavior. First, we identify that the 50-nm-thick amorphous NbOx inherently shows volatile threshold switching (TS). To enable memory switching (MS) in NbOx, device environments are configured that can supply oxygen vacancies or cations constituting a conductive filament (CF). In the Al/NbOx/TiN stack, oxygen vacancies can be internally generated from an interfacial oxide layer formed by the chemical reaction between a highly reactive Al electrode and NbOx, which is confirmed via multiple physical analyses. When the effect of the extrinsic vacancies becomes comparable to the intrinsic properties of the NbOx, the hybrid memory characteristics are observed. While the TS prevents leakage current, the MS is driven by oxygen vacancy CF, allowing multilevel cell operation. Furthermore, hybrid switching can be obtained using the Cu/NbOx/TiN stack. However, the effect of a Cu CF is dominant, because the Cu electrode can externally provide ions infinitely in this case; therefore, hybrid memory behavior is achieved after MS is performed.

HMvisor: dynamic hybrid memory management for virtual machines

HMvisor: dynamic hybrid memory management for virtual machines

RETRACTED ARTICLE: Application of big data platform and embedded intelligent system in teaching assistant work of Jinke resources

This paper constructs a teaching resource sharing system based on big data platform technology, which provides a useful solution for the preservation and sharing of a large number of teaching resources at present and in the future, and accelerates the use of teaching resources and data, making accurate analysis and search become possible. While maintaining the stability of the system, we will improve the security and scalability of the big data platform system, and upgrade education and education informatization to a new level to support big data technology. This article details the software optimization of real-time embedded intelligent system based on non-volatile hybrid memory. This article introduces the main model and problem definition, the pulse-based distance accumulation (PBDA) algorithm proposed in the auxiliary case analysis and the detailed introduction of the auxiliary probability-based data allocation algorithm. The online golden course resources part of online and offline hybrid education, that is, the establishment of online public courses, has been recorded in schools at all levels, but there is no relatively complete warranty policy for offline golden course resources. The offline classroom teaching part is a particularly important part of the university’s mixed teaching, and this part is the embodiment of classroom teaching. The use of data can provide accurate decision-making for training, thereby providing teachers with personalized training and overall training support, and can more reasonably make teaching assistant work a demand of the times. However, the accumulation of data volume does not indicate the value of data. The current results are not satisfactory. One of the reasons is that data quality must be improved, and improving the quality of education data through data governance is one of the focuses of the education industry.

Relation-Based Deep Attention Network with Hybrid Memory for One-Shot Person Re-Identification.

One-shot person Re-identification, which owns one labeled sample among numerous unlabeled data for each identity, is proposed to tackle the problem of the shortage of labeled data. Considering the scenarios without sufficient labeled data, it is very challenging to keep abreast of the performance of the supervised task in which sufficient labeled samples are available. In this paper, we propose a relation-based attention network with hybrid memory, which can make full use of the global information to pay attention to the identity features for model training with the relation-based attention network. Importantly, our specially designed network architecture effectively reduces the interference of environmental noise. Moreover, we propose a hybrid memory to train the one-shot data and unlabeled data in a unified framework, which notably contributes to the performance of person Re-identification. In particular, our designed one-shot feature update mode effectively alleviates the problem of overfitting, which is caused by the lack of supervised information during the training process. Compared with state-of-the-art unsupervised and one-shot algorithms for person Re-identification, our method achieves considerable improvements of 6.7%, 4.6%, and 11.5% on Market-1501, DukeMTMC-reID, and MSMT17 datasets, respectively, and becomes the new state-of-the-art method for one-shot person Re-identification.

Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration

CMOS compatible spin-transfer-torque magnetic random access memory (STT-MRAM) has demonstrated promising developments as the next-generation embedded non-volatile memory (eNVM). In this survey, we provide the state-of-the-art multi-modes reconfigurable techniques for energy-efficient STT-MRAM implementation. We resort to the bottom-up design approach with a twofold aim: 1) summarizing related work from bit-cell to circuit and system levels with conventional and emerging memories. 2) analyzing the present research status of multi-modes reconfigurable techniques in MRAM, which consist of tunable bit-cell configuration, in-memory computing and hybrid memory system. Experimental comparisons show that both reconfiguration and in-MRAM computing obtain extra design freedom. Nonvolatile data accessing cost can be well-alleviated, and thereby improving energy efficiency of MRAM.