Hybrid Field Programmable Gate Array Research Articles

HopliteML: Evolving Application Customized FPGA NoCs with Adaptable Routers and Regulators

We can overcome the pessimism in worst-case routing latency analysis of timing-predictable Network-on-Chip (NoC) workloads by single-digit factors through the use of a hybrid field-programmable gate array (FPGA)–optimized NoC and workload-adapted regulation. Timing-predictable FPGA-optimized NoCs such as HopliteBuf integrate stall-free FIFOs that are sized using offline static analysis of a user-supplied flow pattern and rates. For certain bursty traffic and flow configurations, static analysis delivers very large, sometimes infeasible, FIFO size bounds and large worst-case latency bounds. Alternatively, backpressure-based NoCs such as HopliteBP can operate with lower latencies for certain bursty flows. However, they suffer from severe pessimism in the analysis due to the effect of pipelining of packets and interleaving of flows at switch ports. As we show in this article, a hybrid FPGA NoC that seamlessly composes both design styles on a per-switch basis delivers the best of both worlds, with improved feasibility (bounded operation) and tighter latency bounds. We select the NoC switch configuration through a novel evolutionary algorithm based on Maximum Likelihood Estimation (MLE). For synthetic ( RANDOM , LOCAL ) and real-world ( SpMV , Graph ) workloads, we demonstrate ≈2–3× improvements in feasibility and ≈1–6.8× in worst-case latency while requiring an LUT cost only ≈1–1.5× larger than the cheapest HopliteBuf solution. We also deploy and verify our NoC (PL) and MLE framework (PS) on a Pynq-Z1 to adapt and reconfigure NoC switches dynamically. We can further improve a workload’s routability by learning to surgically tune regulation rates for each traffic trace to maximize available routing bandwidth. We capture critical dependency between traces by modelling the regulation space as a multivariate Gaussian distribution and learn the distribution’s parameters using Covariance Matrix Adaptation Evolution Strategy (CMA-ES). We also propose nested learning, which learns switch configurations and regulation rates in tandem. Compared with stand-alone switch learning, this symbiotic nested learning helps achieve ≈ 1.5× lower cost constrained latency, ≈ 3.1× faster individual rates, and ≈ 1.4× faster mean rates. We also evaluate improvements to vanilla NoCs’ routing using only stand-alone rate learning (no switch learning), with ≈ 1.6× lower latency across synthetic and real-world benchmarks.

Design a Hybrid FPGA Architecture for Visible Digital Image Watermarking in Spatial and Frequency Domain

Hybrid field programmable gate array (FPGA) implementation is proposed to improve the performance of visible image watermarking systems. The visible watermarking process is implemented as pixel by pixel operation under a spatial domain or vector operation in the frequency domain. The proposed approach is mainly designed for watermarking the images taken from digital cameras of various sizes. The padding technique is used for unequal sizes of the watermark image and original host image. The architecture data path consists of eight and six stages of pipeline capable of watermarking on the pixel-based operation and vector-based operation, respectively. The dual image watermarking architecture data path consists of a 13-stage pipeline. Pipeline and parallelism mechanisms are used to improve throughput. To improve the performance in discrete cosine transform operations at the frequency domain, the shift-add technique replaces the conventional multipliers. The clock gating technique is employed to reduce the power by preventing unnecessary switching in a path. Hardware implementation of the algorithm is tested in Intel Cyclone FPGA with the device of EP4CGX22CF19C6, with which the throughput achieved is 1.27[Formula: see text]Gbits/s with a total area utilization of 35[Formula: see text]digital signal processing (DSP) blocks, 378 look-up tables (LUTs) and 486 registers.

Utilization of FPGA for Onboard Inference of Landmark Localization in CNN-Based Spacecraft Pose Estimation

In the recent past, research on the utilization of deep learning algorithms for space applications has been widespread. One of the areas where such algorithms are gaining attention is in spacecraft pose estimation, which is a fundamental requirement in many spacecraft rendezvous and navigation operations. Nevertheless, the application of such algorithms in space operations faces unique challenges compared to application in terrestrial operations. In the latter, they are facilitated by powerful computers, servers, and shared resources, such as cloud services. However, these resources are limited in space environment and spacecrafts. Hence, to take advantage of these algorithms, an on-board inferencing that is power- and cost-effective is required. This paper investigates the use of a hybrid Field Programmable Gate Array (FPGA) and Systems-on-Chip (SoC) device for efficient onboard inferencing of the Convolutional Neural Network (CNN) part of such pose estimation methods. In this study, Xilinx’s Zynq UltraScale+ MPSoC device is used and proposed as an effective onboard-inferencing solution. The performance of the onboard and computer inferencing is compared, and the effectiveness of the hybrid FPGA-CPU architecture is verified. The FPGA-based inference has comparable accuracy to the PC-based inference with an average RMS error difference of less than 0.55. Two CNN models that are based on encoder-decoder architecture have been investigated in this study and three approaches demonstrated for landmarks localization.

Optimized co-scheduling of mixed-precision neural network accelerator for real-time multitasking applications

Abstract Neural networks are increasingly applied into real-time and embedded Artificial Intelligent (AI) systems like autonomous driving system. Such resource-constrained systems cannot support the execution of neural network based tasks due to their high execution overheads on general processors. Hence, we are approaching to design real-time AI applications on embedded systems with CPU and FPGA (Field Programmable Gate Array) coprocessors. We use dedicated FPGA to accelerate the neural network job and utilize CPU to process the rest jobs of real-time multitasking applications. We devise an Idle-Aware Earliest Deadline First policy to co-schedule the AI applications on hybrid CPU and FPGA coprocessors. Since the implementation of neural network job on FPGA accelerator with different precision configuration will result in different execution time and accuracy, we are also interested in the design optimization of real-time AI applications running on mixed-precision neural network accelerator, with the purpose of maximizing the accuracy related rewards of all applications subject to real-time related constraints. We address the problem as a multi-stage decision procedure, and propose an efficient dynamic programming approach with two pruning policies to reduce the intermediate searching states. Extensive experiments and real-life case evaluations demonstrate the efficiency of the proposed approaches.

Design and Demonstration of an Adiabatic-Quantum-Flux-Parametron Field-Programmable Gate Array Using Josephson-CMOS Hybrid Memories

Adiabatic quantum-flux-parametron (AQFP) logic is a promising technology for future energy-efficient high-performance information processing systems. Its static power is zero because of ac flux bias, and its dynamic power is considerably reduced, thanks to the adiabatic switching of the junctions. The lack of high-density memories in the AQFP logic, however, makes it challenging to realize large-scale information processing systems with the use of pure AQFP circuits. We have been developing a Josephson-CMOS hybrid memory to overcome the memory bottleneck in AQFP digital systems. By utilizing the high sensitivity of the AQFP gate, the output current from CMOS memories can be significantly decreased resulting in the reduction of the power consumption. In this article, we designed and fabricated a low-power area-efficient AQFP-CMOS hybrid field-programmable gate array (FPGA), where a CMOS memory is utilized as a rewritable read-only memory to control the AQFP circuits. The AQFP circuit for the AQFP-CMOS hybrid FPGA is composed of logic blocks, switch blocks, and connection blocks, which are clocked by four-phase excitation currents. The AQFP-CMOS hybrid FPGA is fabricated by using the AIST 10 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> Nb high-speed standard process and the Rohm 0.18 μm CMOS process. The area and power consumption of the two-by-two AQFP logic-cell system are estimated to be approximately 6.56 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 12.4 nW at 5 GHz operations, respectively. The power consumption of the CMOS memory was estimated to be 1.02 μW assuming the CMOS source voltage of 3 mV. We demonstrated the operation of the AQFP-CMOS hybrid FPGA at low speed by combining the AQFP logic and the CMOS memory.

Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays

The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 $\mu \text{m}$ , on-resistance of 200 $\text{k}\Omega$ , and a via pitch of 0.4 $\mu \text{m}$ , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to $15\times$ improvement in energy efficiency.

Exploring the Effect of LUT Size on the Area and Power Consumption of a Novel Memristor-Transistor Hybrid FPGA Architecture

Field-programmable gate arrays (FPGAs) have come a long way from being used as glue logic to complete system solution. This is mainly because of their generalized reconfigurable nature, low non-recurring engineering (NRE) cost, and rapid time to market. However, their advantages come at the cost of larger area and higher power consumption eventually making them unsuitable for area and power critical applications. In this work, we propose a novel memristor-transistor hybrid FPGA architecture. Memristor-transistor-based building blocks of FPGA architecture are designed and simulated using HSPICE in this work. Results show that hybrid blocks on average take 30.3 % less area and consume 64.3 % less power compared to transistor-only blocks. Hybrid blocks are combined together to construct logic blocks [i.e., look-up tables (LUTs) and configurable logic blocks] and routing switches of hybrid FPGA architecture. Furthermore, a generalized exploration environment is developed to explore the effect of LUT size on the area and power consumption of memristor-transistor hybrid FPGA architecture. For experimental purpose, sixteen largest MCNC benchmarks are used and LUT size is varied from three to seven. Experimental results show that LUT-4 gives the best area and power results for memristor-transistor hybrid FPGA architecture.

Optimizing Floating Point Units in Hybrid FPGAs

This paper introduces a methodology to optimize coarse-grained floating point units (FPUs) in a hybrid field-programmable gate array (FPGA), where the FPU consists of a number of interconnected floating point adders/subtracters (FAs), multipliers (FMs), and wordblocks (WBs). The wordblocks include registers and lookup tables (LUTs) which can implement fixed point operations efficiently. We employ common subgraph extraction to determine the best mix of blocks within an FPU and study the area, speed and utilization tradeoff over a set of floating point benchmark circuits. We then explore the system impact of FPU density and flexibility in terms of area, speed, and routing resources. Finally, we derive an optimized coarse-grained FPU by considering both architectural and system-level issues. This proposed methodology can be used to evaluate a variety of FPU architecture optimizations. The results for the selected FPU architecture optimization show that although high density FPUs are slower, they have the advantages of improved area, area-delay product, and throughput.

A Circuit and Architecture Codesign Approach for a Hybrid CMOS–STTRAM Nonvolatile FPGA

Research efforts to develop a novel memory technology that combines the desired traits of nonvolatility, high endurance, high speed, and low power have resulted in the emergence of spin-torque transfer RAM (STTRAM) as a promising next-generation universal memory. Although industrial efforts have been made to design efficient embedded memory arrays using STTRAM, the prospect of developing a nonvolatile field-programmable gate array (FPGA) framework with STTRAM exploiting its high integration density remains largely unexplored. In this paper, we propose a novel CMOS-STTRAM hybrid FPGA framework, identify the key design challenges, and propose optimization techniques at circuit, architecture, and application mapping levels. We show that intrinsic properties of STTRAM that distinguish it from conventional static RAM (SRAM), such as asymmetric readout power, where a cell storing “0” has 5× less read power than a cell storing “1”, can be leveraged to skew lookup table contents for FPGA power reduction. We also argue that the proposed framework should operate on static voltage-sensing-based logic evaluation. We identify static power dissipation during logic evaluation and read noise margin as key design concerns and present an optimized resistor-divider design for voltage sensing to reduce static power and noise margin. Finally, we investigate the effectiveness of Shannon-decomposition-based supply gating to reduce static power. Simulation results show improvement of 44.39% in logic area and 22.28% in delay of a configurable logic block (CLB) and average improvement of 16.1% dynamic power over a conventional CMOS FPGA design for a set of benchmark circuits.

Low-power hybrid complementary metal-oxide-semiconductor-nano-electro-mechanical systems field programmable gate array: circuit level analysis and defect-aware mapping

Conventional programmable fabric implemented in nanoscale complementary metal-oxide-semiconductor (CMOS) technologies suffer from large leakage power dissipation and volatility of the storage cells, which require reconfiguration at each power-on. In this study, the authors present a hybrid field programmable gate array design approach that can leverage on carbon nanotube (CNT)-based nano-electro-mechanical systems (NEMS) switches to implement memory elements leading to significant saving in static power dissipation. Besides, because of the non-volatile nature of the CNT-NEMS switches, the proposed framework eliminates the requirement of reconfiguration on start-up. To implement the programmable interconnects, the authors propose two alternative structures leveraging on non-volatile CNT-NEMS switches. To overcome the high defect density of a nano-fabric, the authors also propose a novel application mapping technique that can take advantage of certain defects modelled as stuck-at faults in the lookup tables (LUTs), thus considerably improving the yield. Simulations show that the proposed CMOS-NEMS LUT-based circuits can achieve an average reduction of 90% in leakage power at iso-performance, compared to the conventional CMOS-based LUT circuits. The proposed defect-aware mapping achieves an average improvement of 87% in the number of mapped functions over conventional mapping for 10% defect rate.