HW Platforms Research Articles

Performance modeling of heterogeneous HW platforms

The push towards automated and connected driving functionalities mandates the use of heterogeneous hardware platforms in order to provide the required computational resources. For these platforms, established methods for performance modeling in industry are no longer effective or adequate. In this paper, we explore the detailed problem of mapping a prototypical autonomous driving application on a Nvidia Tegra X2 platform while considering different constraints of the application, including end-to-end latencies of event chains spanning CPU and GPU boundaries. With the given use-case and platform, we propose modeling concepts in Amalthea, capturing the architectural aspects of heterogeneous platforms and also the execution structure of the application. These models can be fed into appropriate tools to predict performance properties. We proposed the above problem in the Workshop on Analysis Tools and Methodologies for Embedded and Real-time Systems (WATERS) Industrial Challenge 2019 and in response, academicians came up with different solutions. In this paper, we evaluate these different solutions and summarize all approaches. The lesson learned from this challenge is then used to improve on the simplifying assumptions we made in our original formulation and discuss future modeling extensions.

Resource-Constrained Machine Learning for ADAS: A Systematic Review

The advent of machine learning (ML) methods for the industry has opened new possibilities in the automotive domain, especially for Advanced Driver Assistance Systems (ADAS). These methods mainly focus on specific problems ranging from traffic sign and light recognition to pedestrian detection. In most cases, the computational resources and power budget found in ADAS systems are constrained while most machine learning methods are computationally intensive. The usual solution consists in adapting the ML models to comply with the memory and real-time (RT) requirements for inference. Some models are easily adapted to resource-constrained hardware, such as Support Vector Machines, while others, like Neural Networks, need more complex processes to fit into the desired hardware. The ADAS hardware (HW platforms) are diverse, from complex MPSoC CPUs down to classical MCUs, DPSs and application-specific FPGAs and ASICs or specific GPU platforms (such as the NVIDIA families Tegra or Jetson). Therefore, there is a tradeoff between the complexity of the ML model implemented and the selected platform that impacts the performance metrics: function results, energy consumption and speed (latency and throughput). In this paper, a survey in the form of systematic review is conducted to analyze the scope of the published research works that embed ML models into resource-constrained implementations for ADAS applications and what are the achievements regarding the ML performance, energy and speed trade-off.

Recommendations for using Simulated Annealing in task mapping

A Multiprocessor System-on-Chip (MPSoC) may contain hundreds of processing elements (PEs) and thousands of tasks but design productivity is lagging the evolution of HW platforms. One problem is application task mapping, which tries to find a placement of tasks onto PEs which optimizes several criteria such as application runtime, intertask communication, memory usage, energy consumption, real-time constraints, as well as area in case that PE selection or buffer sizing are combined with the mapping procedure. Among optimization algorithms for the task mapping, we focus in this paper on Simulated Annealing (SA) heuristics. We present a literature survey and 5 general recommendations for reporting heuristics that should allow disciplined comparisons and reproduction by other researchers. Most importantly, we present our findings about SA parameter selection and 7 guidelines for obtaining a good trade-off made between solution quality and algorithm's execution time. Notably, SA is compared against global optimum. Thorough experiments were performed with 2---8 PEs, 11---32 tasks, 10 graphs per system, and 1000 independent runs, totaling over 500 CPU days of computation. Results show that SA offers 4---6 orders of magnitude reduction is optimization time compared to brute force while achieving high quality solutions. In fact, the globally optimum solution was achieved with a 1.6--90 % probability when problem size is around 1e9---4e9 possibilities. There is approx. 90 % probability for finding a solution that is at most 18 % worse than optimum.

An integer linear programming model for mapping applications on hybrid systems

An integer linear programming (ILP) model for mapping applications on HW platforms that consist of µPs, ASICs and FPGAs is proposed. The introduced model solves the assignment and scheduling problems taking into consideration the time required to reconfigure the FPGAs. Specifically, the type of the tasks that are executed on the FPGAs is taken into account, so that tasks which perform the same function are scheduled consecutively. In that way the number of the FPGAs' reconfigurations is reduced and the performance is improved. Also, the configuration of the FPGAs is hidden because it happens, if it is possible, in the time intervals that the FPGAs are idle. Thus, the execution time of the task mapped on the FPGA does not increase due to reconfiguration time and performance is improved. Moreover, the memory requirements for storing the program and configuration codes of the tasks that are executed on µPs and FPGAs are taken into consideration. In addition, resource conflicts due to tasks/data transfers whose execution times are overlapped in time and are assigned on the same resource (PE/bus) are addressed. Finally, resource sharing is supported. The above features are validated by a series of experiments including a real-application example, the M-JPEG encoder. Also, the complexity of the model is studied in terms of the number of the generated constraints and variables and time required for solving it.