Huffman Decoding Research Articles

GPU implementations of deflate encoding and decoding

SummaryDeflate coding is a very popular lossless data compression method used in zlib, gzip (GNU zip), and zip, which performs the LZSS compression algorithm with Huffman coding. Deflate encoding and decoding involve sequential operations and their parallel acceleration using a GPU is quite hard. The main purpose of this paper is to present GPU implementations for encoding and decoding of Deflate coding. For efficient GPU implementations of Deflate coding, we have used multiple small hash tables for finding matching subsequences in the dictionary by multiple threads in parallel and applied the Single Kernel Soft Synchronization (SKSS) technique to fully utilize GPU computing resources. We have also adopted Huffman coding with gap arrays to accelerate parallel Huffman decoding. We have evaluated the performance of our GPU implementations using an NVIDIA A100 GPU and compared them with parallel/sequential Deflate encoding and decoding on the Intel X86 multicore CPUs using multiple threads/a single thread. Our GPU implementation of Deflate decoding is 1.66x–8.33x faster than the multiple thread implementation and 4.13x–36.56x faster than the single thread implementation.

Energy-efficient canonical Huffman decoders on many-core processor arrays and FPGAs

Data compression is essential to reduce high storage and communication costs for a wide range of systems and applications. Canonical Huffman coding plays a pivotal role for several compression standards. This paper presents bit-parallel static and dynamic canonical Huffman decoder implementations using an optimized lookup table approach on a fine-grain many-core processor array and an Intel FPGA. The decoder implementation results are compared with an Intel i7-4850HQ and a massively parallel Nvidia GT 750M GPU executing the corpus benchmarks: Calgary, Canterbury, Artificial, and Large. The many-core implementations achieve a scaled throughput per chip area that is 891× and 7× greater on average than the i7 and GT 750M respectively. Moreover, the many-core implementations result in a scaled energy efficiency (compressed bits decoded per energy) that is 149.5×, 3.9×, and 2.5× greater on average than the i7, GT 750M, and Intel FPGA respectively. In addition, the optimized lookup-table-based static canonical Huffman decoder on the Intel FPGA yields performance and energy efficiency improvements of 2.1× and 3.68× respectively on average compared to a dynamic canonical Huffman decoder at a 17% cost in compression ratio.

A Real-Time Deep Learning OFDM Receiver

Machine learning in the physical layer of communication systems holds the potential to improve performance and simplify design methodology. Many algorithms have been proposed; however, the model complexity is often unfeasible for real-time deployment. The real-time processing capability of these systems has not been proven yet. In this work, we propose a novel, less complex, fully connected neural network to perform channel estimation and signal detection in an orthogonal frequency division multiplexing system. The memory requirement, which is often the bottleneck for fully connected neural networks, is reduced by ≈ 27 times by applying known compression techniques in a three-step training process. Extensive experiments were performed for pruning and quantizing the weights of the neural network detector. Additionally, Huffman encoding was used on the weights to further reduce memory requirements. Based on this approach, we propose the first field-programmable gate array based, real-time capable neural network accelerator, specifically designed to accelerate the orthogonal frequency division multiplexing detector workload. The accelerator is synthesized for a Xilinx RFSoC field-programmable gate array, uses small-batch processing to increase throughput, efficiently supports branching neural networks, and implements superscalar Huffman decoders.

N-ary Huffman Encoding using High-Degree Trees - A Performance Comparison

In this paper we implement an n-ary Huffman Encoding and Decoding application using different degrees of tree structures. Our goal is to compare the performance of the algorithm in terms of compression ratio, decompression speed and weighted path length when using higher degree trees, compared to the 2-ary Huffman Code. The Huffman tree degrees that we compare are 2-ary, 3-ary, 4-ary, 5-ary, 6-ary, 7-ary, 8-ary and 16-mal. We also present the impact that branch prediction has on the performance of the n-ary Huffman Decoding.

Lossless Decompression Accelerator for Embedded Processor with GUI.

The development of the mobile industry brings about the demand for high-performance embedded systems in order to meet the requirement of user-centered application. Because of the limitation of memory resource, employing compressed data is efficient for an embedded system. However, the workload for data decompression causes an extreme bottleneck to the embedded processor. One of the ways to alleviate the bottleneck is to integrate a hardware accelerator along with the processor, constructing a system-on-chip (SoC) for the embedded system. In this paper, we propose a lossless decompression accelerator for an embedded processor, which supports LZ77 decompression and static Huffman decoding for an inflate algorithm. The accelerator is implemented on a field programmable gate array (FPGA) to verify the functional suitability and fabricated in a Samsung 65 nm complementary metal oxide semiconductor (CMOS) process. The performance of the accelerator is evaluated by the Canterbury corpus benchmark and achieved throughput up to 20.7 MB/s at 50 MHz system clock frequency.

Performance Optimization for Relative-Error-Bounded Lossy Compression on Scientific Data

Scientific simulations in high-performance computing (HPC) environments generate vast volume of data, which may cause a severe I/O bottleneck at runtime and a huge burden on storage space for postanalysis. Unlike traditional data reduction schemes such as deduplication or lossless compression, not only can error-controlled lossy compression significantly reduce the data size but it also holds the promise to satisfy user demand on error control. Pointwise relative error bounds (i.e., compression errors depends on the data values) are widely used by many scientific applications with lossy compression since error control can adapt to the error bound in the dataset automatically. Pointwise relative-error-bounded compression is complicated and time consuming. We develop efficient precomputation-based mechanisms based on the SZ lossy compression framework. Our mechanisms can avoid costly logarithmic transformation and identify quantization factor values via a fast table lookup, greatly accelerating the relative-error-bounded compression with excellent compression ratios. In addition, we reduce traversing operations for Huffman decoding, significantly accelerating the decompression process in SZ. Experiments with eight well-known real-world scientific simulation datasets show that our solution can improve the compression and decompression rates (i.e., the speed) by about 40 and 80 p, respectively, in most of cases, making our designed lossy compression strategy the best-in-class solution in most cases.

Combining SIMD and Many/Multi-core Parallelism for Finite-state Machines with Enumerative Speculation

Finite-state Machine (FSM) is the key kernel behind many popular applications, including regular expression matching, text tokenization, and Huffman decoding. Parallelizing FSMs is extremely difficult because of the strong dependencies and unpredictable memory accesses. Previous efforts have largely focused on multi-core parallelization and used different approaches, including speculative and enumerative execution, both of which have been effective but also have limitations. With increasing width and improving flexibility in SIMD instruction sets, this article focuses on combining SIMD and many/multi-core parallelism for FSMs. We have developed a novel strategy, called enumerative speculation . Instead of speculating on a single state as in speculative execution or enumerating all possible states as in enumerative execution, our strategy speculates transitions from several possible states, reducing the prediction overheads of speculation approach and the large amount of redundant work in the enumerative approach. A simple lookback approach produces a set of guessed states to achieve high speculation success rates in our enumerative speculation. In addition, to enable continued scalability of enumerative speculation with a large number of threads, we have developed a parallel merge method. We evaluate our method with four popular FSM applications: Huffman decoding, regular expression matching, HTML tokenization, and Div7. We obtain up to 2.5× speedup using SIMD on 1 core and up to 95× combining SIMD with 60 cores of an Intel Xeon Phi. On a single core, we outperform the best single-state speculative execution version by an average of 1.6×, and in combining SIMD and many-core parallelism, outperform enumerative execution by an average of 2×. Finally, when evaluate on a GPU, we show that our parallel merge implementations are 2.02--6.74× more efficient than corresponding sequential merge implementations and achieve better scalability on an Nvidia V100 GPU.

Compression Method in JPEG Standard

Data compression is to minimize the communication and storage. The bandwidth and storage required for a given communication system. Data compression is obviated by wideband technologies such as optical fiber communication networks, packet radio and optical storage disk. Images can generate data in such high volumes that any transmission media can be quickly overwhelmed. Personal computers and workstations has led to an increasing demand to store images in compressed from on magnetic or optical disks. The massive efforts taking place today to adopt national and international standards for signal compression. Example is the JPEG (Joint Photographic Experts Group) standard for image compression. Compression in the image from RGB in JPEG standard converted to YCbCr. Each Y, Cb, Cr divided in block 8×8 pixel. The image 8×8 pixel then transformed use DCT. Image from DCT quantized yield DC and AC component. DC component processed use DPCM (Differential Pulse Code Modulation) use Huffman table yield AC bit stream. Merge DC component and AC component yield JPEG bit stream. To get image from JPEG bit stream first use Huffman decoding. From Huffman decoding dequantized. Then transform use IDCT. Image from IDCT merge block 8×8 pixel. From block 8×8 pixel transformed YCbCr to RGB. Then get the image. Process compression is consist of lossy compression and lossless compression. Lossy compression is compression with change of data but not change meaning of information in there. Lossless compression is compression not to change data.

An Architecture for Asymmetric Numeral Systems Entropy Decoder - A Comparison with a Canonical Huffman Decoder

This paper proposes two decoder hardware architectures for the tabled asymmetric numeral systems (tANS) compression algorithm, a software implementation of which is used by Apple and Facebook due to its efficiency. To the best of our knowledge, hardware architectures for the highly efficient tANs algorithm are investigated by the authors so far uniquely. The tANS decoder hardware architectures have been compared to a novel Huffman decoder hardware architecture because the Huffman coding is known as one of the fastest coding techniques in hardware and software. For the proposed architectures, the decoding throughput is highly dependent on the compression ratio of data. Experimental results show that the proposed tANS architecture outperforms the tANS software decoder and can achieve the throughput up to 200MB/s using current FPGA technology. Compared to canonical Huffman decoder the proposed hardware architecture provides up to four times higher decoding throughput.

Time Optimization for Lossy Decompression of the LISA Sensor Data on LAPAN A3 Satellite Using a Grouping Method of HUFFMAN Code Bit Number

The LAPAN-A3 satellite provides compressed multispectral data from LISA sensor using real-time lossy compression. The compression of the multispectral data of radiometric resolution 12bit/pixel is built from the Fourier transform and the use of Huffman decoder 514 binary length code. A problem arised in the data extraction process, that decompression performance is very slow because the search method of code value in Hufman table was done sequentially from one bit to the next bit in one block of data along 4000 pixels. The data extraction time for one scene in 12 minutes acquisition duration (one full path) takes up to 20 hours. This paper proposes a method of improving the LISA real-time lossy data decompression algorithm using the grouping method of bit code on the Huffman decoding algorithm and using pointer for reading data in the buffer memory. Using this method, the searching process of bit code for all characters in the Huffman decoder algorithm is done regularly, so the search processing time is significantly reduced. The performance test used 6 data samples. The result showed that extraction time has an average of 14 times faster. The lossy compression ratio is still in accordance with the design specification of LISA sensor that is less than 4 times and the appearance of the special character is very small i.e. less than 0.5%.

Combining SIMD and Many/Multi-core Parallelism for Finite State Machines with Enumerative Speculation

Finite State Machine (FSM) is the key kernel behind many popular applications, including regular expression matching, text tokenization, and Huffman decoding. Parallelizing FSMs is extremely difficult because of the strong dependencies and unpredictable memory accesses. Previous efforts have largely focused on multi-core parallelization, and used different approaches, including {\em speculative} and {\em enumerative} execution, both of which have been effective but also have limitations. With increasing width and improving flexibility in SIMD instruction sets, this paper focuses on combining SIMD and multi/many-core parallelism for FSMs. We have developed a novel strategy, called {\em enumerative speculation}. Instead of speculating on a single state as in speculative execution or enumerating all possible states as in enumerative execution, our strategy speculates transitions from several possible states, reducing the prediction overheads of speculation approach and the large amount of redundant work in the enumerative approach. A simple lookback approach produces a set of guessed states to achieve high speculation success rates in our enumerative speculation. We evaluate our method with four popular FSM applications: Huffman decoding, regular expression matching, HTML tokenization, and Div7. We obtain up to 2.5x speedup using SIMD on one core and up to 95x combining SIMD with 60 cores of an Intel Xeon Phi. On a single core, we outperform the best single-state speculative execution version by an average of 1.6x, and in combining SIMD and many-core parallelism, outperform enumerative execution by an average of 2x.

Fast and Parallel AAC Decoder Architecture for a Digital Radio Mondiale 30 Receiver

An embedded real-time indexing engine for live radio stations requires a high-speed parallel advanced audio coding (AAC) decoder architecture to decode hundreds of compressed audio streams broadcast in the digital radio mondiale band. Several AAC hardware core units must be integrated into a single chip and synchronized with a global controller to achieve such high performance. This paper proposes a new parallel AAC decoder architecture to address this challenge. The proposed architecture includes multiple AAC decoder core units, each of which achieves a speed-up by a factor of 2 compared with the existing AAC decoder core units while using optimal logic resources. The proposed architecture overcomes several challenges faced by existing architectures. The Huffman decoder module decodes one word per clock cycle regardless of word length, and a smaller lookup table size is achieved for the inverse quantization module. The inverse modified discrete cosine transform architecture is fully pipelined, and the resource sharing technique is used to reduce the logic area. An initial prototype is implemented on an FPGA platform.

A 0.5 V 54 Ultra-Low-Power Object Matching Processor for Micro Air Vehicle Navigation

An ultra-low-power object matching processor is proposed for the autonomous micro air vehicle (MAV) navigation systems. For the ultra-low power consumption, it adopts four low-power features: 1) a 4-point scale-invariant generalized Hough transform (4P-SIGHT) to reduce the computational cost by 51%, 2) a feature streaming pipeline (FSP) to lower the operating frequency by 40%, 3) a Huffman and delta decoder (HDD) to reduce the memory readouts by 35.3%, and 4) a small-area and wide-operating-range 10-transistor level shifter (10T-LS) for the near-threshold voltage (NTV) operation. The proposed 2.0 $\text{mm}^{2}$ object matching processor is fabricated using 65 nm CMOS technology and it consumes only 54 $\mu\text{W}$ at 5 MHz operating frequency and 0.5 V supply voltage while processing QVGA resolution video in 30 fps. It is successfully applied to the MAV and shows 93.5% recognition accuracy for the autonomous navigation. It provides 9.35 $\times$ better energy efficiency than previous state-of-the-art object matching processors.

Research on FPGA Prototype Simulation in MP3 Audio Decoder Design

By further study of MP3 audio decoding algorithms, this paper analyzed the system structure of MP3 decoder and discusses the mapping of each module from algorithm to logic structure. Aiming at hardware implementation, it pro- poses the improved searching method for MP3 audio encoder, based on the features of Huffman decoding. It also adopts the intellectual property core of MP3 comprehensive filter groups and fast IMDCT algorithms. In inverse quantization module the compensated factor is used to make magnitude upgrade of SNR, without multiplications. We use coprocessor to design special instruction set and arithmetic unit by the analysis of fast IMDCT algorithm. It rewrites original C lan- guage and adopts unified DCT-based transforming core algorithm to compute the IMDCT of MP3. It can provide parallel work of IMDCT and LEON3 processor to make accelerated effects.

Transformed HCT for parallel Huffman decoding

SummaryThis paper proposes a novel and generic Huffman code table (HCT) transform and a simple parallel Huffman decoding method. Codes of the original HCT are left‐aligned, reordered in value, and partitioned into sub‐bands. Two kinds of modification to the codes are introduced in order to reduce the number of sub‐bands. The Huffman decoder can be implemented with a minimized size of single LUT, and the parallel decoding can be completed easily, at a constant rate of up to one code per cycle. An example of MP3 decoder and AAC decoder has been designed to demonstrate the efficiency of the proposed method. Copyright © 2014 John Wiley & Sons, Ltd.

Data-parallel finite-state machines

A finite-state machine (FSM) is an important abstraction for solving several problems, including regular-expression matching, tokenizing text, and Huffman decoding. FSM computations typically involve data-dependent iterations with unpredictable memory-access patterns making them difficult to parallelize. This paper describes a parallel algorithm for FSMs that breaks dependences across iterations by efficiently enumerating transitions from all possible states on each input symbol. This allows the algorithm to utilize various sources of data parallelism available on modern hardware, including vector instructions and multiple processors/cores. For instance, on benchmarks from three FSM applications: regular expressions, Huffman decoding, and HTML tokenization, the parallel algorithm achieves up to a 3x speedup over optimized sequential baselines on a single core, and linear speedups up to 21x on 8 cores.

Data-parallel finite-state machines

A finite-state machine (FSM) is an important abstraction for solving several problems, including regular-expression matching, tokenizing text, and Huffman decoding. FSM computations typically involve data-dependent iterations with unpredictable memory-access patterns making them difficult to parallelize. This paper describes a parallel algorithm for FSMs that breaks dependences across iterations by efficiently enumerating transitions from all possible states on each input symbol. This allows the algorithm to utilize various sources of data parallelism available on modern hardware, including vector instructions and multiple processors/cores. For instance, on benchmarks from three FSM applications: regular expressions, Huffman decoding, and HTML tokenization, the parallel algorithm achieves up to a 3x speedup over optimized sequential baselines on a single core, and linear speedups up to 21x on 8 cores.

A Case for a Value-Aware Cache

Replication of values causes poor utilization of on-chip cache memory resources. This paper addresses the question: How much cache resources can be theoretically and practically saved if value replication is eliminated? We introduce the concept of value-aware caches and show that a sixteen times smaller value-aware cache can yield the same miss rate as a conventional cache. We then make a case for a value-aware cache design using Huffman-based compression. Since the value set is rather stable across the execution of an application, one can afford to reconstruct the coding tree in software. The decompression latency is kept short by our proposed novel pipelined Huffman decoder that uses canonical codewords. While the (loose) upper-bound compression factor is 5.2×, we show that, by eliminating cache-block alignment restrictions, it is possible to achieve a compression factor of 3.4× for practical designs.

Wavelet transform and Huffman coding based electrocardiogram compression algorithm: Application to telecardiology

We present in this work an algorithm for electrocardiogram (ECG) signal compression aimed to its transmission via telecommunication channel. Basically, the proposed ECG compression algorithm is articulated on the use of wavelet transform, leading to low/high frequency components separation, high order statistics based thresholding, using level adjusted kurtosis value, to denoise the ECG signal, and next a linear predictive coding filter is applied to the wavelet coefficients producing a lower variance signal. This latter one will be coded using the Huffman encoding yielding an optimal coding length in terms of average value of bits per sample. At the receiver end point, with the assumption of an ideal communication channel, the inverse processes are carried out namely the Huffman decoding, inverse linear predictive coding filter and inverse discrete wavelet transform leading to the estimated version of the ECG signal. The proposed ECG compression algorithm is tested upon a set of ECG records extracted from the MIT-BIH Arrhythmia Data Base including different cardiac anomalies as well as the normal ECG signal. The obtained results are evaluated in terms of compression ratio and mean square error which are, respectively, around 1:8 and 7%. Besides the numerical evaluation, the visual perception demonstrates the high quality of ECG signal restitution where the different ECG waves are recovered correctly.

Novel binary tree Huffman decoding algorithm and field programmable gate array implementation for terrestrial-digital multimedia broadcasting mobile handheld

Recent mobile devices, which adopted Eureka-147, terrestrial-digital multimedia broadcasting (T-DMB) systems, are developed as integrated circuit. As a result, the space of memory expands hardly on mobile handheld. Therefore most mobile handheld must operate a lot of application on limited memory. To solve the problem, most of the mobile devices use some kind of compression algorithms to overcome the memory shortage. Among such algorithms, Huffman algorithm is most widely used. In this study, the authors present a novel binary tree expression of the Huffman decoding algorithm which reduces the memory use approximately by 50% and increases the decoding speed up to 30%. The authors experiment the decoding speed on an evaluation kit (SMDK 6400), which is a T-DMB mobile handheld with an advanced risk machine processor. Later to enhance the decoding speed, the authors present an optimum Huffman decoder based on hardware implementation.