Hot Spots In Microprocessors Research Articles

Thermoelectric active cooling for transient hot spots in microprocessors

Modern microprocessor performance is limited by local hot spots induced at high frequency by busy integrated circuit elements such as the clock generator. Locally embedded thermoelectric devices (TEDs) are proposed to perform active cooling whereby thermoelectric effects enhance passive cooling by the Fourier law in removing heat from the hot spot to colder regions. To mitigate transient heating events and improve temperature stability, we propose a novel analytical solution that describes the temperature response of a periodically heated hot spot that is actively cooled by a TED driven electrically at the same frequency. The analytical solution that we present is validated by experimental data from frequency domain thermal reflectance (FDTR) measurements made directly on an actively cooled Si thermoelectric device where the pump laser replicates the transient hot spot. We herein demonstrate a practical method to actively cancel the transient temperature variations on circuit elements with TEDs. This result opens a new path to optimize the design of cooling systems for transient localized hot spots in integrated circuits.

A simplified approach to hotspot alleviation in microprocessors

Hotspots in microprocessors arise due to non-uniform utilization of the underlying integrated circuits during chip operation. Conventional liquid cooling using microchannels leads to undercooling of the hotspot areas and overcooling of the background area of the chip resulting in excessive temperature gradients across the chip which adversely affects the chip performance and reliability. This problem becomes even more acute in multi-core processors where most of the processing power is concentrated in specific regions of the chip called as cores. We present a one-dimensional, semi-empirical approach for quick design of a microchannel heat sink for targeted, energy efficient liquid cooling of hotspots in microprocessors. Our approach enables targeted manipulation of the local cooling capacity in the microchannel heat sink, which in turn minimizes the chip temperature gradient. The method is formulated to design a heat sink for an arbitrary chip power map and hence can be readily utilized for different chip architectures. It involves optimization of microchannel widths and flow rate distribution for various zones of the power map under the operational constraints of maximum pressure drop limit for the heat sink. Additionally, it ensures that the coolant flows uninterrupted through its entire travel length consisting of microchannels of varying widths. The resulting design estimate significantly reduces the effort involved in designing hotspot-targeted heat sinks.

Computational and Experimental Investigation of Thermal Coupling Between Superlattice Coolers

Thermal coupling between superlattice coolers (SLCs) in an array adversely affects performance of an each individual cooler compared with an isolated device. Here, we have developed an electrothermal model to study this coupling between SLCs and how it is affected by geometric parameters such as separation between the superlattice structure and a ground electrode, and operating parameters such as the convective heat transfer coefficient and the activation current applied for driving the SLC. Complementary to the modeling efforts, we have also experimentally studied thermal coupling between SLCs in a microfabricated array under various conditions. Simulation results are critically compared against the experimental data and yield the conclusions of importance for an optimized design of the hybrid microfluidic SLC cooling scheme for thermal management of multiple clustered hotspots in microprocessors. We have observed more than 60% reduction in cooler performance, when placed within the few characteristic diameters of the ground electrode, due to thermal coupling effect. Thermal properties of the working fluid have even more pronounced effect on the thermal coupling between the coolers.

Miniaturized BJT-Based Thermal Sensor for Microprocessors in 32- and 22-nm Technologies

A thermal sensor is proposed for microprocessors, which compares the BJT voltage to a reference by converting both voltages to frequency and dividing the frequencies to result in a digital number. The sensor has an rms resolution of ±0.2C and an area of 0.02 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at the 32-nm process node and 0.006 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> at 22 nm, including all digital processing circuitry. The conversion rate is between 2-20 kS/s, which enables it to capture fast transients on the CPU. It consumes 3.8/1.4 mW at 32/22 nm from an unregulated 1.4-V supply. The combination of speed, low power, and area make this sensor appropriate to measure hot-spots in microprocessors.

3D Compact Model of Packaged Thermoelectric Coolers

Hotspots on a microelectronic package can severely hurt the performance and long-term reliability of the chip. Thermoelectric coolers (TECs) can provide site-specific and on-demand cooling of hot spots in microprocessors. We develop a 3D compact model for fast and accurate modeling of a TEC device integrated inside an electronic package. A 1D compact model of a TEC is first built in SPICE and validated for steady-state and transient behavior against a finite-volume model. The 1D compact model of the TEC is then incorporated into a 3D compact model of a prototype electronic package. The results from the compact model for the packaged TEC are in good agreement with a finite-volume based model, which confirms the compact model's ability to accurately model the TEC's interaction with the package. Analysis of packaged TECs using this 3D compact model shows that (i) moving TECs closer to the chip results in faster response time and an increase in maximum cooling, (ii) high thermal contact resistance within the thermoelectric cooler significantly degrades performance of the device, and (iii) higher convective heat transfer coefficients (HTC) at the heat spreader surface increase steady-state cooling but decrease maximum transient cooling.

Thermoreflectance imaging of sub 100 ns pulsed cooling in high-speed thermoelectric microcoolers

Miniaturized thin film thermoelectric coolers have received considerable attention as potential means to locally address hot spots in microprocessors. Given the highly dynamic workload in complex integrated circuits, the need arises for a thorough understanding of the high-speed thermal behavior of microcoolers. Although some prior work on transient Peltier cooling in pulsed operation is available, these studies mostly focus on theoretical modeling and typically deal with relatively large modules with time constants well into the millisecond range. In this paper, we present an extensive experimental characterization of 30×30 μm2 high-speed coplanar SiGe superlattice microcoolers subjected to 300 ns wide current pulses at ≈ 300 kHz repetition rate. Using thermoreflectance imaging microscopy, we obtain 2D maps of the transient surface temperature and constituent Peltier and Joule components over the 50–750 ns time range with submicron spatial and 50 ns temporal resolutions. Net cooling of 1 K–1.5 K is achieved within 100–300 ns, well over an order of magnitude faster compared to previous reports on microcoolers in high-speed operation. We also point out ambiguities in separating Peltier and Joule signals during the device turn-off. Overall, our measurements provide substantial insight into ultrafast turn-on and turn-off dynamics in thin film thermoelectrics.

Array of Thermoelectric Coolers for On-Chip Thermal Management

Site-specific on-demand cooling of hot spots in microprocessors can reduce peak temperature and achieve a more uniform thermal profile on chip, thereby improve chip performance and increase the processor’s life time. An array of thermoelectric coolers (TECs) integrated inside an electronic package has the potential to provide such efficient cooling of hot spots on chip. This paper analyzes the potential of using multiple TECs for hot spot cooling to obtain favorable thermal profile on chip in an energy efficient way. Our computational analysis of an electronic package with multiple TECs shows a strong conductive coupling among active TECs during steady-state operation. Transient operation of TECs is capable of driving cold-side temperatures below steady-state values. Our analysis on TEC arrays using current pulses shows that the effect of TEC coupling on transient cooling is weak. Various pulse profiles have been studied to illustrate the effect of shape of current pulse on the operation of TECs considering crucial parameters such as total energy consumed in TECs peak temperature on the chip, temperature overshoot at the hot spot and settling time during pulsed cooling of hot spots. The square root pulse profile is found to be the most effective with maximum cooling and at half the energy expenditure in comparison to a constant current pulse. We analyze the operation of multiple TECs for cooling spatiotemporally varying hot spots. The analysis shows that the transient cooling using high amplitude current pulses is beneficial for short term infrequent hot spots, but high amplitude current pulse cannot be used for very frequent or long lasting hot spots.

Fighting fire with fire

Local thermal hot-spots in microprocessors lead to worst-case provisioning of global cooling resources, especially in large-scale systems where cooling power can be 50~100% of IT power. Further, the efficiency of cooling solutions degrade non-linearly with supply temperature. Recent advances in active cooling techniques have shown on-chip thermoelectric coolers (TECs) to be very efficient at selectively eliminating small hot-spots. Applying current to a superlattice TEC-film that is deposited between silicon and the heat spreader results in a Peltier effect, which spreads the heat and lowers the temperature of the hot-spot significantly and improves chip reliability . In this paper, we propose that hot-spot mitigation using thermoelectric coolers can be used as a power management mechanism to allow global coolers to be provisioned for a better worst case temperature leading to substantial savings in cooling power. In order to quantify the potential power savings from using TECs in data center servers, we present a detailed power model that integrates on-chip dynamic and leakage power sour-ces, heat diffusion through the entire chip, TEC and global cooler efficiencies, and all their mutual interactions. Our multi-scale analysis shows that, for a typical data center, TECs allow global coolers to operate at higher temperatures without degrading chip lifetime, and thus save ~27% cooling power on average while providing the same processor reliability as a data center running at 288K.

Multicore compilation strategies and challenges

To overcome challenges stemming from high power densities and thermal hot spots in microprocessors, multicore computing platforms have emerged as the ubiquitous computing platform from servers down through embedded systems. Unfortunately, providing multiple cores does not directly translate into increased performance or better energy efficiency for most applications. The burden is placed on software developers and tools to find and exploit coarse-grain parallelism to effectively make use of the abundance of computing resources provided by these systems. Concurrent applications are much more complex to develop than their single-threaded ancestors, thus software development tools will be critical to help programmers create both high performance and correct software. This article provides an overview of parallelism and compiler technology to help the community understand the software development challenges and opportunities for multicore signal processors.

Investigation of the Impact of Power Granularity on Chip Thermal Modeling Using White Noise Analysis

In this paper, we investigate the impact of the granularity of the power distribution for accurately predicting semiconductor chip temperature fields. Specifically, we calculate the transfer functions between power distributions and resulting temperature maps for various microprocessor packages and cooling conditions, which establish a minimum granularity required for accurate thermal analysis. The purpose of this paper is twofold: First, we like to provide some general guidelines for the impact of different power granularities on the global chip temperatures and second we intend to spike a broader discussion about to which extent small heating effects can affect chip temperatures for circuits under full operation. As such this work is not only beneficial for package and cooling solution engineering but is also important to circuit designers and computer architects in their battle against hotspots in microprocessors.

Enhancing Semiconductors with Diamond

ABSTRACTIn the continuing thrust to extend Moore's law, silicon is beginning to confront several issues that require innovative materials solutions to increase transistor and interconnect speeds while dealing with the increasing thermal loads of advanced microprocessors. The unsurpassed thermal and mechanical properties of diamond can be profitably exploited to enhance the performance characteristics of silicon based circuits. The discussion focuses primarily on the integration of diamond with silicon for the manufacture of silicon on diamond (SOD) wafers for spreading heat from hot spots in microprocessors. Other interesting property combinations are also presented as food for thought regarding other possible enhancements to silicon device performance. Recent data and prognosis for the future will be presented.