Hot Carrier Injection Mechanism Research Articles

Hot Electron-Driven Photocatalysis Using Sub-5 nm Gap Plasmonic Nanofinger Arrays.

Semiconductor photocatalysis has received increasing attention because of its potential to address problems related to the energy crisis and environmental issues. However, conventional semiconductor photocatalysts, such as TiO2 and ZnO, can only be activated by ultraviolet light due to their wide band gap. To extend the light absorption into the visible range, the localized surface plasmon resonance (LSPR) effect of noble metal nanoparticles (NPs) has been widely used. Noble metal NPs can couple incident visible light energy to strong LSPR, and the nonradiative decay of LSPR generates nonthermal hot carriers that can be injected into adjacent semiconductor material to enhance its photocatalytic activity. Here we demonstrate that nanoimprint-defined gap plasmonic nanofinger arrays can function as visible light-driven plasmonic photocatalysts. The sub-5 nm gaps between pairs of collapsed nanofingers can support ultra-strong plasmon resonance and thus boost the population of hot carriers. The semiconductor material is exactly placed at the hot spots, providing an efficient pathway for hot carrier injection from plasmonic metal to catalytic materials. This nanostructure thus exhibits high plasmon-enhanced photocatalytic activity under visible light. The hot carrier injection mechanism of this platform was systematically investigated. The plasmonic enhancement factor was calculated using the finite-difference time-domain (FDTD) method and was consistent with the measured improvement of the photocatalytic activity. This platform, benefiting from the precise controllable geometry, provides a deeper understanding of the mechanism of plasmonic photocatalysis.

Nanosheet-Compatible Complementary-Field Effect Transistor Logic Non-Volatile Memory Device

This study proposes a logic non-volatile memory (NVM) device based on the state-of-the-art gate-all-around (GAA) nanosheet process. By adopting a complementary FET structure, we not only reduce the layout footprint area but also demonstrate the compatibility with sub-3nm nanosheet CMOS technology. We simulated the device in TCAD for program and erase operations, considering both Fowler Nordheim tunneling and hot carrier injection mechanisms. The memory window is optimized by adjusting the device structure, such as tunneling and blocking oxide thicknesses, top- and bottom-channel width, and the floating gate length, resulting in a significant enhancement in the memory window. Finally, NAND/NOR type CFET logic NVM are demonstrated to reveal the possible applications of gate-all-around stacked junctionless nanosheet transistor towards embedded flash.

Large Photoresponsivity in the Amorphous‐TiO2/SrRuO3 Heterostructure

Thin‐film heterostructures are effective in enhancing the performance or triggering novel physical phenomena of optoelectronic applications. For example, the epitaxial heterostructures of ultraviolet‐light‐sensitive TiO2 with metallic SrRuO3 can acquire visible‐light functionalities using the hot carrier injection mechanism. Therefore, the TiO2/SrRuO3 heterostructure system has recently attracted increasing interest. Herein, the amorphous‐TiO2/SrRuO3 heterostructure is fabricated and compared to the epitaxial TiO2/SrRuO3. As opposed to the occurrence of the visible‐light photovoltaic effect in the epitaxial TiO2/SrRuO3, the amorphous‐TiO2/SrRuO3 heterostructure herein exhibits different optoelectronic functionality, specifically the photoresistor behavior. The amorphous‐TiO2/SrRuO3 heterostructure achieves a photoresponsivity of 6.56 A W−1 at 1 V. Such a performance is hardly obtained in typical oxide‐based photoresistors. The analyses of the crystalline and electronic structures show that it is due to the defect‐induced high electron doping in the amorphous TiO2 with hot carrier injection mechanism. This study discusses the correlation between the hot carrier injection and band diagram, which provides more degrees of freedom in designing potential optoelectronic devices.

Investigating the Plasmonic Hot-Carrier Injection Mechanism for CO2 Reduction Using Nanostructured Ag Catalysts

Converting CO2 into hydrocarbons or other liquid fuels and leveraging solar energy to do so are of great importance as an alternative energy source and as a potential pathway to slow climate change. However, CO2 reduction reactions suffer from high overpotentials and poor selectivity. Recently, localized surface plasmon resonance (LSPR) was suggested as a way to overcome these challenging barriers [1-3]. Nanostructured catalysts absorbing visible light at their plasmon frequency can excite hot carriers which can be transferred directly or indirectly into the molecular orbitals of adsorbates. This unique charge injection mechanism along with the ability to tune the plasmon frequency over a wide range of energies may allow plasmonic photocatalysts to unlock a new, unexplored CO2 reduction pathway resulting in increased selectivity and lower overpotentials. Silver (Ag) is a strong plasmonic material and well-known for selectively producing CO [4,5]. In the hopes of taking advantage of the plasmonic properties to make more reduced products on Ag, we have developed Ag nanopyramid arrays, resulting in strong plasmonic and catalytic behaviors. Photocurrent measurements were performed on the plasmonic nanopyramid catalysts in aqueousNaClO4 saturated with either CO2 or Ar. The photocurrent is greatly enhanced in the presence of CO2, and shows ‘resonant-like’ behavior at a specific potential (-1.1 V vs. RHE). In Ar-saturated electrolyte, the photocurrent was drastically reduced and no characteristic feature of photocurrent was observed. This result indicates that the hot carriers created by LSPR react specifically with CO2 molecules or other CO2 reduction intermediates. By measuring incident photon to current efficiency (IPCE), we find that the hot-carrier transfer mechanism can be modulated as a function of applied potentials. Further, we discuss the differences in product distributions measured with a gas chromatograph (GC) and high performance liquid chromatography (HPLC) under light illumination and in the dark.

New Hot-Carrier Injection Mechanism at Source Side in Nanoscale Floating-Body MOSFETs

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A new hot-carrier injection mechanism that depends on gate bias and body thickness in nanoscale floating-body MOSFETs has been identified using 2-D device simulation and hot-carrier degradation measurements. When gate voltage is sufficiently high and the body thickness is thin, the potential of the floating body is elevated due to the ohmic voltage drop at the source extension (SE), resulting in impact ionization at the SE. Hot-carrier stress with accelerated gate voltage may lead to a huge overestimation of lifetime in nanoscale floating-body MOSFETs. </para>

Device Scaling Effects on Substrate Enhanced Degradation in MOS Transistors

AbstractThis paper analyzes in detail the substrate enhanced gate current injection mechanism and the resulting hot-carrier degradation in n-channel MOS transistors and compares the results with conventional channel hot carrier injection mechanism. The degradation mechanism is studied for different values of substrate voltage over a wide range of channel length and oxide thickness. Stress and charge pumping measurements are carried out to study the degradation under identical bias (gate, drain, substrate) and gate current condition. The influence of device dimensions on the gate injection efficiency and hot carrier degradation is also studied. Results show that the degradation under negative substrate voltage operation is strongly dependent on the transverse electric field and spread of the interface trap profile. The possible mechanism responsible for such trends is discussed. It is also found that, under identical gate current (programming time in flash memory cells), the degradation is less for higher negative substrate bias, which is helpful in realizing fast and reliable flash memories.

Hot-carrier effects in submicrometre MOS VLSIs

Hot-carrier effects in submicrometre MOS VLSI circuits are described in terms of (a) the hot-carrier injection mechanisms, (b) the device degradation, (c) the hot-carrier resistant device structures and (d) the hot-carrier phenomena under a bias of less than 3 V. Two significant hot-carrier injection mechanisms are proposed which are different from those of the channel hot-electron (CHE) and substrate hot-electron (SHE) injection as previously reported by Ning et al. They are (i) drain avalanche hot-carrier (DAHC) and (ii) secondarily generated hot-electron (SGHE) injection. Based on an experimental comparison of gate currents due to these mechanisms it is shown that DAHC imposes the most severe constraint on VLSI design. In addition, hot-carrier resistant device structures, such as an As-P double diffused drain (DDD) and lightly doped drain (LDD), are also described as so called ‘drain engineering techniques’ to enhance reliability of MOS devices. Finally, in anticipation of a possible reduction in power supply voltages in the future, hot-carrier phenomena have been investigated at bias levels below 3 V, where hot carriers cannot obtain enough energy to surmount the Si-SiO2 barrier. The experimental results clearly show that device degradation due to hot-carrier injection occurs even at VD &lt; 3 V. Thus, hot carrier effects remain one of the most stringent limiting factors affecting submicrometre MOSFETs, even after the power supply voltage is reduced.

New hot-carrier injection and device degradation in submicron MOSFETs

New kinds of hot-carrier injection mechanisms, which are different from channel hot-electron and substrate hot-electron injection mechanisms already reported by Ning, et al., are presented. These are first drain avalanche hot-carrier (DAHC) injection and secondly substrate current induced hot-electron (SCHE) injection. DAHC injection is due to the emission of electrons and holes heated in the drain avalanche plasma. SCHE injection is caused by the emission of excess electrons originating from impact ionisation of substrate current. The authors have succeeded in directly observing these two injection phenomena by measuring gate current as low as of the order of 10−15 A for small size MOS devices having effective channel length below 1.0 μm and gate oxide thinner than 10nm. The measured gate currents due to both injection mechanisms are also modelled numerically using the CADDET, a 2-D analysis program. In addition, device degradation due to these new injections is clarified. Base on the experimendal results, it is shown that DAHC effect rather than channel hot-electron effect, is more responsible for hot carrier related device degradation. The SCHC is also found to cause significant threshold shift, even at the VD&lt;3V bias condition. thus, the presented injection phenomena prove to impose more Severe constraints on the submicron VLSI device design.