Hot-carrier Induced Device Degradation Research Articles

The Impact of Fin Number on Device Performance and Reliability for Multi-Fin Tri-Gate n- and p-Type FinFET

In this paper, the effect of carrier quantization on device characteristics and stress-induced device degradation for multifin high- ${\boldsymbol \kappa }$ /metal tri-gate n-type and p-type fin field-effect transistors (FinFETs) were investigated through electrical characterization and simulation. Carrier conduction in the steep Si fins of FinFETs is different for devices with different numbers of fins and affects device performance and reliability. For n-type FinFETs, devices with fewer fins inhibited the coupling effect between fins to exhibit superior device performance but underwent more severe hot carrier–induced device degradation. The coupling effect between fins reduced the equivalent electric field in the multifin devices and further inhibited impact ionization; thus, devices with more fins achieved superior reliability to single-fin devices after hot-carrier stress. For p-type FinFETs, a similar effect on performance was demonstrated but with lower sensitivity to hot-carrier stress-induced device degradation caused by lower hole mobility within the Si fin channel.

Investigation of characteristics and hot-carrier reliability of high-voltage MOS transistors with various doping concentrations in the drift region

The effect of doping concentration in the n− drift region on the characteristics and hot-carrier reliability in high-voltage n-type MOS transistors is investigated. Results show that a proper increase in the n− drift doping concentration improves device characteristics. In addition, a proper increase in the n− drift doping concentration reduces hot-carrier induced device degradation. Technology computer-aided design simulation results suggest that the impact of hot-carrier induced interface charge generation on device degradation is alleviated for a higher n− drift doping concentration. Such a result can explain the reduction in hot-carrier induced device degradation for the device with a higher doping concentration in the n− drift region.

소스 및 드레인 전극 재료에 따른 비정질 InGaZnO 박막 트랜지스터의 소자 열화

소스 및 드레인 전극 재료에 따른 비정질 InGaZnO 박막 트랜지스터의 소자 열화

Impact of back gate biases on hot carrier effects in multiple gate junctionless transistors

The impacts of back gate biases on hot carrier induced device degradation in multiple gate junctionless (JL) transistors have been investigated experimentally. The drain current was decreased after hot carrier stress without a polarity of back gate stress bias. The impacts of back gate bias on the drain current degradation are more significant in JL transistors than inversion mode (IM) transistors. When a positive back gate bias is applied, the interface coupling effect is more sensitive in JL transistors because the inversion channel is located at the centroid of the Si film in JL transistors but the back channel is located at the back interface in IM transistors. 3-dimensional device simulation was performed using ATLAS software to investigate the impact of negative VBS on hot carrier degradation in JL transistors.

Hot carrier degradation of InGaZnO thin film transistors under light illumination at the elevated temperature

The experimental investigations of hot carrier induced device degradation in IGZO thin film transistors under light illumination at elevated temperature have been performed. The degradations of threshold voltage and inverse subthreshold slope have been measured with stress time, stress temperature and light intensity. After hot carrier stress, the negative shift of transfer curves and the increased drain current are caused by the generation of a donor-like interface states at the interface between the channel region and the gate dielectric layer. The device degradation is increased with stress temperature and light intensity. Due to the positive temperature dependence of conduction current, the increased device degradation is attributed to the increased channel current at elevated temperature. The increased device degradation under light illumination is due to the increased channel current which is resulted from the photo-generated electron. The device degradation is the most significant at the stress condition of hot carrier stress combined with elevated temperature and light illumination.

Negative-bias-temperature-instability and hot carrier effects in nanowire junctionless p-channel multigate transistors

Negative-bias-temperature-instability (NBTI) and hot-carrier induced device degradation have been experimentally compared between accumulation mode (AM) p-channel multigate transistors (pMuGFETs) and junctionless (JL) pMuGFET. NBTI degradation is less significant in junctionless pMuGFETs than AM pMuGFETs. The threshold voltage shift is less significant in junctionless transistors than AM transistors. The device simulation shows that the peak of lateral electric field and the impact ionization rate of AM device are larger than those of junctionless devices.

NBTI and hot carrier effect of Schottky-barrier p-MOSFETs

The experimental investigation of NBTI and hot carrier induced device degradation in Pt-silicided Schottky-barrier p-MOSFETs has been performed. The investigations on the threshold voltage shifts, the degradation of inverse subthreshold slope, and the decrease of I ON / I OFF ratio have been carried out using the modulation of Schottky-barrier height and width. After NBTI and hot carrier stress, the decrease of I ON could be explained by the lower hole tunneling current through the more increased Schottky-barrier height and the increased I OFF could be explained by the increase of the amount of electron thermal emission and tunneling through thinner Schottky-barrier into the near drain. After hot carrier stress, it is observed that the threshold voltage shifts to more negative values for all stress gate voltages and the drain current is decreased. The device degradation is more significant as the stress gate voltage decreases.

NBTI and hot-carrier effects in accumulation-mode Pi-gate pMOSFETs

Negative bias temperature instability (NBTI) and hot-carrier induced device degradation in accumulation-mode Pi-gate pMOSFETs have been studied for different fin widths ranging from 20 to 40 nm. The NBTI induced device degradation is more significant in narrow devices. This result can be explained by enhanced diffusion of hydrogen at the corners in multiple-gate devices. Due to larger impact ionization, hot-carrier induced device degradation is more significant in wider devices. Finally, hot-carrier induced device degradation rate is highest under stress conditions where V GS = V TH.

Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs

The dependence of hot-carrier effects on silicon film thickness is investigated in nanometer-scale SOI pMOSFETs. The results of device simulation and experimental measurements shine light on controversial issues regarding the dependence of hot-carrier effects on the silicon film thickness. For a structure with raised source and drain, it is observed that the peak electric field near drain junction and the gate current increase as the silicon film thickness decreases, and thus that hot-carrier effect are increased. Therefore, hot-carrier induced device degradation in nanometer-scale MuGFETs with elevated source/drain structure should be seriously considered in device design and fabrication. The dependence of hot-carrier effects on silicon film thickness under different stress conditions involving the action of substrate bias and temperature are also discussed.

Reduced Hot Carrier Effects in Self-Aligned Ground-Plane FDSOI MOSFET’s

This paper reports the hot-carrier induced device degradation of fully depleted (FD) n-channel SOI MOSFETs with a self-aligned ground-plane electrode in the silicon substrate underneath the buried oxide. The ground-plane configuration is shown to reduce short-channel effects, BJT effects and hot-carrier effects. Based on measurements of hot-carrier degradation rate, it is predicted that the maximum allowable supply voltage of ground-plane FDSOI MOSFET is higher than that of FDSOI device without a ground plane.

Efficient Improvement of Hot Carrier-Induced Degradation for 0.1-<tex>$muhbox m$</tex>Indium-Halo nMOSFET

The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1-/spl mu/m nMOSFETs was investigated. We found that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation. The best results of device performance were obtained with post-annealing treatment performed at medium temperatures (e.g., 900/spl deg/C) for a longer time.

Effect of Mobile Charge on Hot-Carrier Degradation in Lateral Diffused MOSFET

Hot carrier-induced device degradation in n-type lateral diffused MOSFETs with mobile charges in gate oxide has been studied. Abnormal decrease-then-increase in V/sub th/ during hot-carrier stress was observed. The decrease was found to be caused by movement of mobile charges while the increase was the normally observed hot-electron degradation. The hot-electron degradation was drastically accelerated with the presence of mobile charges and easily recovered after baking or negative gate bias. The magnitude of degradation linearly increases with mobile charge density. The acceptable limits of mobile charge density have been estimated. The observed behaviors are very similar to positive charging processes found in other n-MOSFETs that were attributed to hot-hole effects, suggesting mobile charge induced degradation must be carefully excluded in hot-hole injection studies.

Temperature dependence of hot carrier induced MOSFET degradation at low gate bias

Abstract This paper reports a new experimental finding on the temperature dependence of the substrate current and hot carrier induced device degradation at low gate bias. It has been found that the substrate current increases and the drain current degradation is more significant for high operating temperature at low gate bias. It has been observed that the hot carrier induced performance degradation of a latch-type input buffer increases at the elevated temperature.

Hot carrier induced device degradation in RF-nMOSFET's

This study presents the hot carrier induced device degradation in 0.8 μm RF-nMOSFET's within the general framework of the degradation mechanism. It has been found that the device degradation model of a single-finger gate MOSFET could be applied for a multi-finger gate RF-nMOSFET. The reduction of the cut-off frequency and maximum frequency after stress can be explained by the decrease of transconductance and the increase of drain output conductance.

Hot Carrier Effects in Deep Submicron Nmosfets

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

Reliability of Submicron Mosfet's with Deposited Gate Oxides under F-N Injection and Hot-Carrier Stress

In this paper, submicron nMOSFET's with thin LPCVD gate oxides deposited using chemical reaction of dichlorosilane and nitrous oxide at 800 °C were evaluated. Fowler-Nordheim injection was performed to compare the resistance to electron trapping and interface-state generation of these LPCVD oxides to that of the thermally grown oxides at 850 °C. It was found that with an 850 °C 20-minute post-deposition nitrogen anneal, the LPCVD oxides exhibit comparable immunity to electron trapping as the thermal oxides. Transistor characteristics such as Δg m /g m , ΔI D /I D revealed to be similar for both oxides, but there was an order of magnitude higher ΔV t detected for the LPCVD oxide films (with/without anneal) than the thermal oxides. The mechanism responsible for the hot-carrier induced device degradation was also characterized in this study. It was found that the major source of hot-carrier damage was electron trapping for the thermal oxides and the N 2 - annealed LPCVD oxides; while for the as-deposited LPCVD oxides, both electron trapping and interface-state generation contributed to device degradation.