Hot-carrier Degradation Effects Research Articles

Influence of Hot Carrier Degradation on the Characteristics of a High-Voltage SOI Transistor with a Large Drift Region

The results of studying the effect of hot carrier degradation on the electrical characteristics of high-power laterally diffused metal oxide semiconductor (LDMOS) transistors made according to the silicon-on-insulator (SOI) technology, with a long drift region with topological norms of 0.5 microns, are discussed. The analysis of the degradation of hot carriers in high electric fields is based on the experimental results and the additional use of an analytical model. The physical origin of this mechanism is related to the formation of traps at the Si/SiO2 interface. With the help of numerical analysis and experiments, the electrical character-istics of SOI nLDMOS transistors are considered in a wide range of control voltages in order to study their effect on the safe operation zone and reliability of the device under conditions of the degradation of hot carriers. The results of these studies allow us to conclude that a 20% expansion of the safe operation zone is possible.

Impact of Hot-Carrier Degradation on Drain-Induced Barrier Lowering in Multifin SOI n-Channel FinFETs With Self-Heating

Application of high-frequency ac stress in the place of conventional dc stress is known to decrease the damage caused by self-heating (SH)-induced hot-carrier injection (HCI) in highly scaled MOSFET devices. However, the effect of hot-carrier degradation on short-channel performance is less explored. In this article, a detailed examination of the drain-induced barrier lowering (DIBL) under hot-carrier stress is presented for 14-nm silicon-on-insulator (SOI) n-channel FinFETs. In particular, the influence of SH-enhanced HCI on DIBL is thoroughly investigated for devices with different geometrical parameters including a number of fins, gate length, and so on at different ac stress frequencies. The change in dominant degrading mechanism from bulk oxide trapping to interface state generation under dc and ac stress is shown to affect DIBL severely. Interestingly, the effect of SH on DIBL is in contrast to that in ON-current degradation. Furthermore, time evolution of DIBL degradation for asynchronous stress waveforms is studied for accurate reliability analysis for short-channel devices.

A Kriging framework for the efficient exploitation of the nanoscale junctioless DG MOSFETs including source/drain extensions and hot carrier effect

Recently, the Junctionless Double Gate MOSFET with source/drain extensions has proved competitive performance measures due to the reduction of the series resistance between the metal contacts and source/drain regions. However, the precise modeling of different response functions is still an important issue especially at nanoscale level because of the inclusion of complex phenomena such as quantum transport mechanisms and hot carrier degradation effect. In this perspective, our aim in the presented work is to investigate the efficiency of a novel approach based on Kriging metamodeling and multi-objective particle swarm optimization for the exploitation of the considered device in terms of some analog/RF performances. Data generated by ATLAS-2D simulator, are used to establish Kriging metamodels for the Gain and Transconductance Generation Factor. It is highlighted that the obtained models can be used accurately in a multi-objective context to offer several Pareto optimal configurations. As a result, a wide range of biasing configurations is available to the designer depending on imposed constraints.

Degradation and annealing effects caused by oxygen in AlGaN/GaN high electron mobility transistors

Hot-carrier degradation and room-temperature annealing effects are investigated in unpassivated ammonia-rich AlGaN/GaN high electron mobility transistors. Devices exhibit a fast recovery when annealed after hot carrier stress with all pins grounded. The recovered peak transconductance can exceed the original value, an effect that is not observed in control passivated samples. Density functional theory calculations suggest that dehydrogenation of pre-existing ON-H defects in AlGaN plays a significant role in the observed hot carrier degradation, and the resulting bare ON can naturally account for the “super-recovery” in the peak transconductance.

An analytical two dimensional subthreshold behavior model to study the nanoscale GCGS DG Si MOSFET including interfacial trap effects

In order to pursue the miniaturization process as predicted by Moor’s law and go beyond actual reached lengths, more condensed efforts should be focused not only on looking for higher mobility materials but also on improving existing topologies of nanocircuit digital devices, which are the corner stone of currently used information storage supports. Therefore, the aim of this paper is to provide a quantitative analysis about the efficiency of our proposed structure Graded Channel Gate Stack Double Gate on Si MOSFET (GCGS DG Si MOSFET) in remedying the short channel and hot carrier degradation effects. The analysis is carried out by using an analytical 2-D subthreshold behavior model consolidated with numerical simulations (SILVACO), where the proposed structure shows an improvement and immunity against the hot carriers in terms of threshold voltage and swing factor. Moreover, the developed analytical models including the device immunity effect are compared with those of the conventional DG MOSFET, where a significant enhanced performance is predicted for the case of our proposed design. Consequently, it can be reasonably claimed that the (GCGS) DG Si MOSFET structure can alleviate the short channel and hot carrier degradation effects and further improves the device reliability for the nanoelectronic digital applications.

Two‐dimensional numerical analysis of nanoscale junctionless and conventional Double Gate MOSFETs including the effect of interfacial traps

AbstractThis paper deals with the immunity behavior of the junctionless DG MOSFET device against the hot carrier degradation effect. The junctionless device is highly privileged because of its easy fabrication procedure, homogeneity along the channel axe in addition to its promising electrical characteristics compared to the conventional DG MOSFET with PN junction at the source and the drain sides. As a result, we demonstrate that junctionless DG MOSFET can be a viable option to enhance the immunity performances of nanoscale CMOS‐based devices technology for nanoelectronics digital applications (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Continuous analytic I—V model for GS DG MOSFETs including hot-carrier degradation effects

We have studied the influence of hot-carrier degradation effects on the drain current of a gate-stack double-gate (GS DG) MOSFET device. Our analysis is carried out by using an accurate continuous current—voltage (I—V) model, derived based on both Poisson's and continuity equations without the need of charge-sheet approximation. The developed model offers the possibility to describe the entire range of different regions (subthreshold, linear and saturation) through a unique continuous expression. Therefore, the proposed approach can bring considerable enhancement at the level of multi-gate compact modeling including hot-carrier degradation effects.

An Explicit Continuous Analytical Model for Gate All Around (GAA) MOSFETs Including the Hot-Carrier Degradation Effects

In this paper, an explicit and continuous analytical model including interfacial hot-carrier effects is developed for a deep submicron Gate All Around (GAA) MOSFETs. Explicit analytical expressions of the surface potential, drain current and transconductance are given for all operating modes. Exploiting this new device model, we have found that the incorporation of a high-k layer, Gate Stack (GS), between oxide region and gate metal leads to drain current enhancement, improved transconductance parameter and enhanced interfacial hot-carrier immunity. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GS GAA MOSFET design can alleviate the critical problem and further improve the immunity of hot-carrier effects of GAA MOSFET-based circuits in the deep submicron working domain.

Drain current model for undoped Gate Stack Double Gate (GSDG) MOSFETs including the hot-carrier degradation effects

In this paper, analytical models of drain current and small signal parameters for undoped symmetric Gate Stack Double Gate (GSDG) MOSFETs including the interfacial hot-carrier degradation effects are presented. The models are used to study the device behavior with the interfacial traps densities. The proposed model has been implemented in the SPICE circuit simulator and the capabilities of the model have been explored by circuit simulation example. The developed approaches are verified and validated by the good agreement found with the 2D numerical simulations for wide range of device parameters and bias conditions. GSDG MOSFET design and the accurate proposed model can alleviate the critical problem and further improve the immunity of hot-carrier effects of DG MOSFET-based circuits after hot-carrier damage.

A two-dimensional analytical subthreshold behavior analysis including hot-carrier effect for nanoscale Gate Stack Gate All Around (GASGAA) MOSFETs

The Gate All Around (GAA) MOSFET is considered as one of the most promising devices for downscaling below 50 nm. By surrounding the channel completely, the gate gains increased electrostatic control of the channel and short-channel-effects (SCEs) can be drastically suppressed. However, challenges still remain to resolve the important issues particularly concerning hot-carrier reliability and accurate device models for nanoscale circuit designs. Hot-carrier effects have been the major issues in the long-term stability of subthreshold performances in a nanoscale MOS transistor. In this paper we present a two-dimensional analytical analysis of the subthreshold behavior, subthreshold current and subthreshold swing, including the interfacial hot-carrier effects. The calculated results of the proposed approach match well with those of the 2-D numerical device simulator. The present work provides valuable design insights in the performance of nanoscale CMOS-based devices including hot-carrier degradation effects.

Analytical analysis of nanoscale fully depleted Double-Gate MOSFETs including the hot-carrier degradation effects

Increased device degradation due to hot-carrier effects in nanoscale double-gate (DG) MOSFETs is investigated. We have studied the hot-carrier degradation effects on surface potential, threshold voltage and drain-induced barrier lowering (DIBL) of nanoscale DG MOSFETs. Exploiting this new device model, we have found that the degradation becomes worse when the channel length gets shorter and the minimum potential's position is affected by the hot-carrier induced localised interface charge density. DIBL effect is more pronounced in very short channel lengths (L less than 40 nm) in the presence of the hot-carrier effects. The results showed that the analytical model is in close agreement with the 2-D numerical simulation over a wide range of device parameters.

Analytical analysis of nanoscale multiple gate MOSFETs including effects of hot-carrier induced interface charges

As the channel length rapidly shrinks down to the nanoscale regime, the multiple gate MOSFETs structures have been considered as potential candidates for a CMOS device scaling due to its good short-channel-effects (SCEs) immunity. Therefore, in this work we investigate the scaling capability of Double Gate (DG) and Gate All Around (GAA) MOSFETs using an analytical analysis of the two dimensional Poisson equation in which the hot-carrier induced interface charge effects have been considered. Basing on this analysis, we have found that the degradation becomes more important when the channel length gets shorter, and the minimum surface potential position is affected by the hot-carrier induced localized interface charge density. Using this analysis, we have studied the scaling limits of DG and GAA MOSFETs and compared their performances including the hot-carrier effects. Our obtained results showed that the analytical analysis is in close agreement with the 2-D numerical simulation over a wide range of devices parameters. The proposed analytical approach may provide a theoretical basis and physical insights for multiple gate MOSFETs design including the hot-carrier degradation effects.

An analytical study of hot-carrier degradation effects in sub-micron MOS devices

In this present communication, we have studied the effect of hot-carrier degradation effects on surface potential, threshold voltage and DIBL of the sub-micron device. We have derived a more accurate model for the threshold voltage in the presence of hot carrier degradation effect. Our model includes a fitting parameter to take care of short channel effects. The validity of our model is verified by the MINIMOS simulator results. Our analysis predicts that the minimum potential position along the channel is not affected by the sign of the hot carrier induced localized interface charge density and always occurs in damage free region. DIBL effect is more pronounced in submicron devices in the presence of the hot carrier degradation effect.

Research on correlation of 1/fγ noise and hot carrier degradation in metal oxide semiconductor field effect transistor

Metal oxide semiconductor field effect transistor (MOSFET) in high-, mid- and low-gate stresses of hot carrier degradation effect and its 1/fγ noise feature are studied. Based on the formation theories of interface traps and oxide traps in Si-SiO2 and the MOSFET 1/fγ noise mechanism, the process of exchange carrier between the defect in gate oxide and the free-carrier in the channel is simulated by the duo-phonon emission model. A unified physical model for hot carrier effect, material defect, electrical parameter and noise was built. Also, a method characterizing the MOSFET anti-hot carrier abilities with noise parameter Sfγ is presented. The model is testified by the experiment, which is designed based on the relation between hot carrier and noise. Experimental results well confirm the developed model.

Analysis of hot-carrier degradation in a SOI LDMOS transistor with a steep retrograde drift doping profile

This paper reports the electrical performances of a RF SOI power LDMOS transistor with a retrograde doping profile in the entire drift region. A comparison between retrograde and conventional uniformly doped drift SOI power LDMOS transistors is provide by means of a numerical simulation analysis. The proposed structures exhibit better performances in terms of trapped electron distribution and transconductance degradation with no modification of the breakdown voltage capability. Simulation results show that, at a given bias conditions, the reduction of lateral electric field peak at the silicon surface due to the implementation of the retrograde doping profile accounts for the observed reduction of the hot carrier degradation effect.

Simple estimation of the effect of hot-carrier degradation on scaled nMOSFETs

The influence of parasitic charge at the Si–SiO2 interface on the characteristics of n-channel metal oxide semiconductor field effect transistors (nMOSFETs) scaled down to a feature size of 25 nm is studied. The results are that the impact of parasitic charge on threshold voltage and drain current degradation significantly decreases. Additionally, as the hot-electron injection current densities are lowered for scaled-down nMOS transistors, less charge build-up occurs. This opens the perspective to make use of alternative gate dielectrics even if they have a higher interface trap density. These materials offer the advantage of greater dielectric constants than silicon oxide, so that a physically thicker dielectric will limit the gate tunnelling current.

Time-Dependent Drain- and Source-Series Resistance of High-Voltage Lateral Diffused Metal–Oxide–Semiconductor Field-Effect Transistors during Hot-Carrier Stress

In this paper, a new reverse transconductance method for investigating the effect of hot-carrier degradation on high-voltage (HV) lateral diffused metal–oxide–semiconductor field-effect transistors (LDMOSFETs) is presented. This new method can extract asymmetric drain and source series resistance separately with only one single device. By using this extraction method in HV LDMOSFETs before and after the application of hot-carrier stress, drain series resistance is extracted and found to increase while source series resistance remains the same. In addition, the threshold voltage and subthreshold slope suffer no degradation after the application of hot-carrier stress. Therefore, it is suggested that the current degradation in HV LDMOSFETs after the application of hot-carrier stress is not due to the damage under the channel but is due to the drift region under the spacer oxide. This is confirmed by the simulation results of a two-dimensional (2D) simulator. In addition, the differences in hot-carrier degradation between HV LDMOSFETs and low-voltage lightly doped drain (LV LDD) MOSFETs are also discussed in detail.

Special mechanisms in thin-film SOI MOSFETs

The main special mechanisms that govern the operation of thin-film SOI MOSFETs are reviewed. The influence of the most important technological and electrical parameters, e.g. the film and buried oxide thicknesses, film and silicon substrate doping, channel length, substrate bias, and interface defects, is discussed. The electrical properties of fully depleted thin-film SOI MOS transistors are improved, especially the driving current and the subthreshold swing. We address the advantages of thin-film SOI devices in relation to scaling rules down to deep submicron transistors, as well as the main parasitic phenomena, e.g. the kink, latch, breakdown, self-heating and hot-carrier degradation effects. Finally, the low temperature properties and potential quantum effects are outlined.

UHV STM nanofabrication: progress, technology spin-offs, and challenges

A brief review of scanned probe nanofabrication is presented followed by an in-depth discussion of ultrahigh vacuum (UHV) scanning tunneling microscope (STM) nanofabrication on hydrogen passivated silicon surfaces. In this latter case the UHV STM functions as a nanolithography tool by selectively desorbing hydrogen from silicon surfaces. Patterns of clean Si, down to atomic dimensions, are achieved as well as detailed information about the H-desorption mechanisms. At higher sample voltages direct electron stimulated desorption occurs, whereas, at lower voltages, vibrational heating of the Si-H bond leads to desorption. The chemical contrast between clean and H-passivated silicon enables a wide variety of spatially selective nanoscale chemical reactions. Results are presented in which these templates are used for selective oxidation, nitridation, and metallization by chemical vapor deposition. An unexpected byproduct of this research was the discovery that deuterium is about two orders of magnitude more difficult to desorb from silicon than hydrogen. This served as the basis for the idea of treating CMOS transistors with deuterium to reduce their susceptibility to hot carrier degradation effects. Tests have now shown that the lifetimes of CMOS transistors increase by factors of 10 to 50 when deuterium treatment is substituted for the traditional hydrogen processing.

Dynamic hot carrier degradation effects in CMOS submicron transistors

Hot carrier degradation in submicron LDD CMOS transistors under dynamic operation is studied. Anomalous degradation modes are shown in p-channel transistors, and a simple model for their interpretation is presented. Correct characterization of hot carrier damage and its physical mechanisms are discussed.