Host Workstation Research Articles

Multiview Image Block Compressive Sensing with Joint Multiphase Decoding for Visual Sensor Network

In this article, a multiview image compression framework, which involves the use of Block-based Compressive Sensing (BCS) and Joint Multiphase Decoding (JMD), is proposed for a Visual Sensor Network (VSN). In the proposed framework, one of the sensor nodes is configured to serve as the reference node, the others as nonreference nodes. The images are encoded independently using the BCS to produce two observed measurements that are transmitted to the host workstation. In this case, the nonreference nodes always encoded the images (I NR ) at a lower subrate when compared with the images from the reference nodes (I R ). The idea is to improve the reconstruction of I NR using I R . After the two observed measurements are received by the host workstation, they are first decoded independently, then image registration is applied to align I R onto the same plane of I NR . The aligned I R is then fused with I NR , using wavelets to produce the projected image I P . Subsequently, the difference between the measurements of the I P and I NR is calculated. The difference is then decoded and added to I P to produce the final reconstructed I NR . The simulation results show that the proposed framework is able to improve the quality of I NR on average by 2dB to 3dB at lower subrates when compared with other Compressive Sensing (CS)--based multiview image compression frameworks.

Improving Efficiency of FPGA-in-the-Loop Verification Environment

The paper presents techniques being developed in order to improve verification efficiency in the FPGA-in-the-Loop environment. The verification speed-up in relation to typical software simulation within MATLAB® suite offered to the presented verification environment is in the range of 100s. The proposed verification environment enables engineers to verify their designs by co-simulation of high- level models with RTL logic. It allows for checking if the prepared VHDL or Verilog code matches the more abstract reference model. The introduced verification environment uses MATLAB® and Simulink® models, being the de facto modelling standard in the industry. The paper presents a solution which improves signal visibility of a design-under-test and accelerates simulation performance by moving DUT into an FPGA. The implemented original FPGA-based emulation platform offers an efficient interface channel to a host workstation and a GUI software with an embedded viewer for dynamic signal selection and observation. It may be applied to a broad range of simulation subjects.

A Coarse-Grain Hierarchical Technique for 2-Dimensional FFT on Configurable Parallel Computers

FPGAs (Field-Programmable Gate Arrays) have been widely used as coprocessors to boost the performance of data-intensive applications [1], [2]. However, there are several challenges to further boost FPGA performance: the communication overhead between the host workstation and the FPGAs can be substantial; large-scale applications cannot fit in a single FPGA because of its limited capacity; mapping an application algorithm to FPGAs still remains a daunting job in configurable system design. To circumvent these problems, we propose in this paper the FPGA-based Hierarchical-SIMD (H-SIMD) machine with its codesign of the Pyramidal Instruction Set Architecture (PISA). PISA comprises high-level instructions implemented as FPGA functions of coarse-grain SIMD (Single-Instruction, Multiple-Data) tasks to facilitate ease of program development, code portability across different H-SIMD implementations and high performance. We assume a multi-FPGA board where each FPGA is configured as a separate SIMD machine. Multiple FPGA chips can work in unison at a higher SIMD level, if needed, controlled by the host. Additionally, by using a memory switching scheme and the high-level PISA to partition applications into coarse-grain tasks, host-FPGA communication overheads can be hidden. We enlist the two-dimensional Fast Fourier Transform (2D FFT) to test the effectiveness of H-SIMD. The test results show sustained high performance for this problem. The H-SIMD machine even outperforms a Xeon processor for this problem.

A high performance reconfigurable hardware platform for digital pulse processing

This paper presents a new reconfigurable hardware platform which uses both digital signal processors (DSP) and field programmable gate arrays (FPGA) to attain high resolution and real-time processing in nuclear spectrometry experiments. The module was designed in order to provide a high digital pulse processing (DPP) yield with the capacity of being reconfigurable according to the experimental conditions and the desired data output. This allows unprecedented real time processing capabilities implemented in the FPGA such as pulse pileup correction through adaptive filtering and effective signal-to-noise ratio (SNR) control and optimization. The module uses a Virtex-II Pro FPGA (Xilinx) and a DSP from the TMS320C64xx family (Texas Instruments) and is implemented on a PCI board to be used in a host workstation. Special emphasis is given to the scalability of the module along with the potential capacity of being used as a portable stand-alone instrument. This reconfigurable hardware platform allows us to simultaneously benefit from the advantages of the hardware based digital spectrometers, namely, their high throughput, and of the flexibility of the software based configurations. Besides, this same platform can be used as a general purpose high-speed data acquisition and processing unit.

Electron-beam position monitoring and feedback control in Duke Free-Electron Laser Facility

This paper addresses data acquisition and feedback control of electron-beam positions in the Duke University Free-Electron Laser Facility. The control system consists of a distributed system of VME-based hardware and processors connected through a network to host workstations. The host workstations provide graphical data presentation to the user and are also used for high-level supervisory control. The electron-beam profile is controlled by electromagnetic forces generated by passing currents through the coils of correction magnets distributed around the ring. A desired control objective is to move the stored electron beam to specific locations in the vacuum chamber and to stabilize the orbit in the presence of disturbances. The technical details of implementing the data acquisition and control scheme and their integration with the existing control system modules are presented along with experimental results.

Distributed real-time control and data acquisition of free-electron laser beams

Implementation of a feedback control scheme and its associated user interface and data acquisition modules in a distributed real time computing environment are described. The distributed system consists of an ethernet network interconnecting real time processor modules to host workstations and other embedded controllers. The goal of the feedback control scheme is to maintain positions of the electron beam in the middle of the vacuum chamber in the presence of electromagnetic interference and noise. Technical details of implementing the data acquisition and control scheme and their integration with the existing control system modules are presented, along with experimental results.

Remodeling of JT-60 discharge control system

Remodeling of the JT-60 discharge control system (DCS) is initiated to minimize the cost and time for hardware maintenance and software development. Three principles have been adopted for remodeling. (1) The functions of the DCS must remain intact. (2) The shutdown period must be minimized to maximize JT-60 experiment time. To realize the new DCS, (3) a combination of the host workstation (WS) and target Versa Module Europe (VME)-bus system with real time OS was chosen as the fundamental structure. The prototype DCS was designed and tested to evaluate the performance of the converted discharge sequential control software modules and the message communication program. The new configuration of the DCS and procedure of smooth remodeling without shutdown is described in detail.

VisRes: A G RACE tool for displaying and analysing resonances

VisRes is a graphical tool for displaying and analysing resonance data. Files of eigenphase sums, generated during the computation of electron and photon interactions with atoms and molecules, can be read and the data displayed both as continuous and discontinuous graphs. Resonance resolution can be improved by interactively computing additional data points and merging them with the displayed data. Resonance positions and widths are determined by fitting user selected data points by the Breit—Wigner formula. VisRes is written in C and Motif for the UNIX operating system. It can be operated exclusively on the host workstation or in distributed mode where data is read from and computed on a remote computer but displayed and analysed on the host workstation. While it is published as a stand-alone tool, VisRes also forms part of the Graphical R-matrix Atomic Collision Environment (G RACE).

High-speed data paths in host-based routers

In networking today, host workstations are increasingly being used as routers. Host based routers offer a number of advantages, but they suffer from inefficient support for high bandwidth interfaces. The authors' work has focused on the technology's major drawback its inefficiency in supporting high bandwidth interfaces. Their approach is to optimize packet processing by applying techniques that transfer packets directly among host interfaces, thus removing an extra data copy. This technique increases data throughput by 45 percent while reducing the host's CPU load. They found that peer DMA forwarding can increase host based router throughput by up to 45 percent, supporting bandwidths of 480 Mbps. Peer DMA host based forwarding requires network interface cards with substantial shared memory resources, because packet queues are stored on the interfaces themselves, rather than in host RAM. The queuing algorithm remains in the host CPU, supporting advanced queue management. Current systems have limited packet processing. A combination of streamlined forwarding algorithms and aggregate interrupt processing should further increase host based capability. Moving some of the IP processing out to the NIC coprocessor may enable this. It is also apparent that as processor speeds increase, the advantages of peer DMA will aid throughput for small packet sizes.

Event-based debugging system for a parallel object-oriented language A-NETL

Debugging of parallel programs is generally very difficult to undertake since the execution of programs is nondeterministic and nonrepeatable. Considering a parallel object-oriented language, this paper proposes a method of preserving the repeatability of the order of execution in a replay by defining a logic time in terms of events in the message communication system and state transitions, and by representing the execution history of events. A debugger that mainly uses a two-dimensional (2-D) representation and replay debugging has been designed based on the proposed method. A high-performance system has been constructed based on the design. The debugger functions are distributed between a host workstation and multicomputer nodes, and between local OS on nodes and in firmware so that a high-performance system has been realized. The experiments show that the method is successful for practical applications; the time and space overhead of event recording is 0.04 ms (mean value) and 35 B per event, respectively; the display of 16 objects for one logical time is 0.94 s; and the overhead for a breakpoint is 3.1 ms per point. © 1998 Scripta Technica, Syst Comp Jpn, 28(11): 53–63, 1997

Smoothed Particle Hydrodynamics with GRAPE and Parallel Virtual Machine

We have developed Remote-GRAPE (for GRAvity PipE), a subroutine library to be used with the special purpose computer GRAPE-3A. GRAPE-3A can efficiently calculate gravitational forces between particles and construct neighbor lists. All other calculations are performed on the host workstation (WS), which is directly connected to GRAPE. The use of GRAPE for smoothed particle hydrodynamics (GRAPE-SPH) can in principle greatly speed up the calculations on the WS. However, the current bottleneck of GRAPE-SPH is that its performance is limited by the speed of the host WS. To solve this problem, we implement Remote-GRAPE; it allows us to run applications that use GRAPE-3A hardware on significantly faster computers than the physical host WS. Thus, we can take advantage of fast computers even though they cannot physically be connected to GRAPE. The Remote-GRAPE system is implemented on Parallel Virtual Machine. The details of implementation are described. We analyze the performance of Remote-GRAPE and obtain the following results. (1) When Remote-GRAPE is used to calculate gravitational forces only, the overhead due to the network decreases according to the number of particles (20%-40% of total time). (2) When Remote-GRAPE is used to calculate gravity and neighbor lists, the overhead due to the network does not occupy a large fraction of total time but only ~20%-30%, because the computation required on the slave machine is very large because of the properties of the GRAPE system. (3) We also compare the performance of Remote-GRAPE with the tree method. The tree method requires more time for a higher degree of clustering, while the required time for Remote-GRAPE does not much depend on it. We then analyze the performance of GRAPE-SPH with Remote-GRAPE. The performance of Remote-GRAPE is about 4 times faster than GRAPE-SPH with usual GRAPE for our configuration. Using Remote-GRAPE, we can calculate the GRAPE part and other parts in parallel. This parallel method leads to a further speedup of our SPH code. We estimate how the performance of Remote-GRAPE depends on the configuration. We also show that the performance of Remote-GRAPE can be further improved.

A compact real-time vision system using integrated memory array processor architecture

This paper describes the real-time vision system (RVS-2) which shows quite high performance for low-level image processing while it is implemented in a one-board type compact size format with small power consumption. The RVS-2 consists of an IMAP board, a video board and a host workstation. The IMAP board consists of eight highly-integrated IMAP LSIs and a dedicated control LSI (RVSC). The IMAP chip integrates 2 Mb image memory and 64 processing elements that operate in the SIMD mode. The RVSC chip performs global data operations efficiently without interactions with the host workstation, as well providing an instruction stream to the IMAP chips. The peak performance of the RVS-2 is 30 GIPS and most of the basic image processing tasks are carried out within about 0.1-0.7 ms, which is about 50-300 times faster than the video frame rate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A real-time vision system using an integrated memory array processor prototype

This paper describes a real-time vision system (RVS) architecture and performance and its use of an integrated memory array processor (IMAP) prototype. This prototype integrates eight 8-bit processors and a 144-kbit SRAM on a single chip. The RVS was developed with 64 IMAP prototypes connected in series in a 512 processor-system configuration. A host workstation can access the memory on the IMAP prototypes directly through a random access port. Images are inputted and outputted at high speed through serial access ports. The RVS performance is shown in real-time road-image processing and in a neural network simulation, as well as in low-level image processing algorithms, such as filtering, histograms, discrete cosine transform (DCT), and rotation. The RVS image processing is shown to be much faster than the video rate.

Hydraulic compliance identification using a parallel genetic algorithm

The application of a genetic algorithm to the estimation of hydraulic system parameters in heavy-duty hydraulically-actuated manipulators is described. Identification of hydraulic compliance (indication of joint flexibility) was particularly of interest because of its significant effect on the performance of the class of machines under investigation. Robust and fast identification of this important parameter is essential for diagnosis purposes as well as for improving the control actions. Using real experimental data obtained from an instrumented Caterpillar 215B excavator, the values of the hydraulic compliance for various links were successfully identified. The algorithm was able to handle the nonlinear and coupled actuation dynamics of the hydraulic system with its nonrecursive, population-based search power. The scheme was further studied in order to enhance its speed as well as its parameter tracking ability. Two different parallelization techniques, namely synchronous master-slave and cooperating sequential, were combined at both population and fitness evaluation levels. The algorithm was then implemented using 16 T800 transputers connected to a SUN host workstation. It achieved a speed-up factor of 12 over a traditional genetic algorithm. At such speed, real-time simultaneous monitoring of hydraulic compliances at two joints was possible. Using normal operating data, the right values of compliances from the parameter space were achieved in only a few iterations.

RAID-II

In 1989, the RAID (Redundant Arrays of Inexpensive Disks) group at U. C. Berkeley built a prototype disk array called RAID-I. The bandwidth delivered to clients by RAID-I was severely limited by the memory system bandwidth of the disk array' s host workstation. We designed our second prototype, RAID-H, to deliver more of the disk array bandwidth to file server clients. A custom-built crossbar memory system called the XBUS board connects the disks directly to the high-speed network, allowing data for large requests to bypass the server workstation. RAID-II runs Log-Structured File System (LFS) software to optimize performance for bandwidth-intensive applications.The RAID-II hardware with a single XBUS controller board delivers 20 megabytes/second for large, random read operations and up to 31 megabytes/second for sequential read operations. A preliminary implementation of LFS on RAID-II delivers 21 megabytes/second on large read requests and 15 megabytes/second on large write operations.

The automated interactive microscope (AIM) for investigating the functional dynamics of living cells: Status and vision

The current status and future development plans for the Automated Interactive Microscope (AIM), to better define the mechanisms of the function of living cells, is described. The development of AIM is fueled by biologists need to spatially and temporally correlate biochemical, molecular and genetic patterns to study cell functions such as division, locomotion and endocytosis. AIM will allow the investigator to use the cell as a “living microcuvette”.AIM redefines the meaning of the term “microscope” to include the functional capability of the microscope system provided by computerization, in addition to the more classical definition which emphasizes the opto-mechanical hardware. AIM is an next generation electronic light microscope imaging system which has grown out of our work in the development of the multimode light microscope. New functionality includes new experiment control facilities as well as related multidimensional image processing, image analysis and interactive data visualization. AIM is built around microscope hardware with high precision motion controls and a powerful host workstation computer linked, via a very high speed data gateway, with the high performance computing and communication (HPCC) facilities of the Pittsburgh Supercomputing Center (PSC).

Vision processor system for moving-object analysis

This paper proposes a vision processor for moving-object analysis in time-varying images. The process of motion analysis can be divided into three stages: moving-object candidate detection, object tracking, and final motion analysis. The processor Consists of three components corresponding to these three stages. The first isan overall image processing unitwith local parallel architecture. It locates candidate regions for moving objects. The second is a multimicroprocessor system consisting of 16 local modules. Each module tracks one candidate region. The third is the host workstation. In this paper, we describe both the architecture and the software of the vision processor.

A self-learning digital neural network using wafer-scale LSI

A large-scale, dual-network architecture using wafer-scale integration (WSI) technology is proposed. By using 0.8 mu m CMOS technology, up to 144 self-learning digital neurons were integrated on each of eight 5 in silicon wafers. Neural functions and the back-propagation (BP) algorithm were mapped to digital circuits. The complete hardware system packaged more than 1000 neurons within a 30 cm cube. The dual-network architecture allowed high-speed learning at more than 2 gigaconnections updated per second (GCUPS). The high fault tolerance of the neural network and proposed defect-handling techniques overcame the yield problem of WSI. This hardware can be connected to a host workstation and used to simulating a wide range of artificial neural networks. Signature verification and stock price prediction have already been demonstrated with this hardware.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

DELTA-T: A user-transparent software-monitoring tool for multi-transputer systems

Monitoring tools are important parts of future programming environments for parallel computers. In this paper the software monitor DELTA-T is presented which has been developed for performance monitoring of (standard) multi-transputer systems at the University of Paderborn. Instrumentation is implemented by ‘spy’-processes which are inserted into the target system either to observe it at the node or at the process level. Measurement traces generated by these spies are buffered locally in the node memories. A global system view is achieved by time-stamping the recorded events with a globally valid system time. Evaluation is carried out offline on a host workstation either with an animation tool or an interactive graphical visualization tool.

The Chimera II real-time operating system for advanced sensor-based control applications

The Chimera II has been designed as a local operating system, to be used in conjunction with a global operating system. It executes on one or more single board computers in a VMEbus-based system. Advanced sensor-based control systems are both statistically and dynamically reconfigurable. As a result, they require many special features, which are currently not found in commercial real-time operating systems. Several design issues for such systems are presented as well as the features the authors have developed and implemented as part of Chimera II. These features include: a real-time kernel with dynamic scheduling, global error handling, user signals, and two levels of device drivers; an enhanced collection of interprocessor communication mechanisms, including global shared memory, spin-locks, remote semaphores, priority message passing, global state variable tables, multiprocessor servo task control, and host workstation integration; and several support utilities, including a UNIX C and math libraries, a matrix library, a command interpreter library, and a configuration file library.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>