Hole Transistor Research Articles

E-beam Lithography Technology for Quantum Device Fabrication and Nanoscale Patterning

Currently nanotechnology becoming more important with the implementation of nano devices including quantum devices. In this paper, we will briefly introduce the JEOL JBX-8100FS e-beam lithography tool which was recently installed in Hallym University and the current status of the exposure conditions set up. As applications using e-beam lithography tool, we will introduce Schottky barrier single hole transistor and silicon nanowire thermoelectric device, respectively. We are under researching plasmonic and quantum devices as basic research.

Resonant tunneling and hole transport behavior in low noise silicon tri-gate junctionless single hole transistor

The fabrication of p-type silicon junctionless tri-gate transistors and their temperature dependent transport studies are reported in this work. The fabricated transistors have shown a good transfer characteristic down to a low temperature of ∼ 80 K with an ON/OFF ratio of 106. The threshold voltage and the subthreshold slope were found to be dependent on temperature. In particular, the threshold voltage and the flat band voltage have positive slopes of 2.24 and 1.19 mV K−1, respectively, with temperature. Channel resistance was found to be increasing with decreasing temperature. The devices have shown a typical 1/f noise behavior in the frequency range of (1–50) Hz and 1/f2 type behavior in the frequency range of (50–100 Hz). At a temperature of 4.2 K, current vs. gate voltage characteristic at a fixed source drain bias shows clear coulomb peaks with different intervals for different gate bias voltages and the observed spikes were consistent within the sub-bands. We relate this to the single hole tunneling, mediated by the charged acceptors available in the channel region. Coupling strength of the dopants was also studied.

Coulomb blockade in monolithic and monocrystalline Al-Ge-Al nanowire heterostructures

We report the realization of Ge single-hole transistors based on Al-Ge-Al nanowire (NW) heterostructures. The formation of these axial structures is enabled by a thermally induced exchange reaction at 350 °C between the initial Ge NW and Al contact pads, leading to a monolithic and monocrystalline Al-Ge-Al NW. The 25 nm-diameter Ge segment is a quasi-1D hole channel. Its length is defined by two abrupt Al-Ge Schottky tunnel barriers. At low temperatures, the device shows a single hole transistor signature with well pronounced Coulomb oscillations. The barrier strength between the Ge segment and the Al leads can be tuned as a function of the gate voltage VG. It leads to a zero conductance at VG= 0 V to a few quantum conductance at VG= –15 V. When the gate voltage increases from –5 V to –3 V, the charging energy is extracted and it varies from 0.39 meV to 2.42 meV.

(Invited) Characteristics of Si Single-Electron Transistor under Illumination

Photo-excited carriers in Si quantum islands and their surrounded area exhibit interesting features due to electron-hole generation. We show Si single- hole transistor (SHT) characteristics in a Si single-electron transistor (SET) comprising n-type source and drain electrodes under illumination. Holes excited in the Si are expected to flow through the SET island by applying negative gate voltages. Interesting phenomenon is the co-existence of electrons and holes around the island. In a SET, when holes generated by photo-excitation are trapped in the one side (either top or bottom side) of the SET island under the vertical electric field, the SET characteristics are changed depending on the number of trapped holes because effective total number of electrons can be negative. Here, we show the characteristics of photo-excited SETs without strong vertical electric fields.

Demonstration of Single Hole Transistor and Hybrid Circuits for Multivalued Logic and Memory Applications up to 350 K Using CMOS Silicon Nanowires

The operation of hybrid circuits consisting of a single hole transistor coupled to a metal oxide semiconductor field effect transistor (MOSFET) is demonstrated at 350 K. The devices are designed at ultimate scaling with complementary metal oxide semiconductor technology on 300 mm diameter silicon on insulator wafers using deep ultra‐violet lithography. Coulomb blockade oscillations up to 350 K are measured from silicon nanowire transistors with 20 nm Ω‐gate length and diameter under 5 nm. These oscillations are exploited to produce inverter/amplifier, literal gate, negative differential resistance and memory loop circuits for multivalued (MV) logic and MV memory applications, via hybridization with MOSFET in SETMOS configuration. The fabrication and the operation of these SHT‐MOSFET hybrid circuits at high temperature should spur single charge transistor integration into circuits for innovative applications in nanoelectronics.

Fabrication and characterization of p-channel Si double quantum dots

Lithographically defined p-channel Si single hole transistors (SHTs) and double quantum dot (DQD) devices are fabricated and characterized. Coulomb oscillations are clearly evident at a temperature of 4.2 K. The charging energy and the diameter of the SHT are estimated from the Coulomb diamonds. Honeycomb-like charge stability diagrams are observed from measurements of the DQD devices. Single hole transitions through the DQD are detected using an integrated SHT as a charge sensor, and a few-hole regime of the DQD is observed.

Single hole transport in a silicon metal-oxide-semiconductor quantum dot

We describe a planar silicon metal-oxide-semiconductor (MOS) based single hole transistor, which is compatible with conventional Si complementary MOS fabrication. A multi-layer gate design gives independent control of the carrier density in the dot and reservoirs. Clear Coulomb blockade oscillations are observed, and source-drain biasing measurements show that it is possible to deplete the dot down to the few hole regime, with excited states clearly visible. The architecture is sufficiently versatile that a second hole dot could be induced adjacent to the first one.

Modulation of peak-to-valley current ratio of Coulomb blockade oscillations in Si single hole transistors

We demonstrate a method to modulate the peak-to-valley current ratio of Coulomb blockade oscillation peaks in room temperature-operating Si single-hole tunnel transistors. By connecting the extra p+in+ junction (i.e., a current effluence path) to the drain reservoir, we effectively deplete the leakage current (i.e., valley current) that stem from the diffusion current of the parasitic field-effect transistor within the device. The addition of the extra current-effluence path significantly improves the Coulomb blockade characteristics in comparison to the original Coulomb blockade oscillations. We believe the method is advantageous for designing high performance Si single electron/hole tunnel devices.

Low Temperature Characteristics of Schottky Barrier Single Electron and Single Hole Transistors

Schottky barrier single electron transistors (SB-SETs) and Schottky barrier single hole transistors (SB-SHTs) are fabricated on a 20-nm thin silicon-on-insulator substrate incorporating e-beam lithography and a conventional CMOS process technique. Erbium- and platinum-silicide are used as the source and drain material for the SB-SET and SB-SHT, respectively. The manufactured SB-SET and SB-SHT show typical transistor behavior at room temperature with a high drive current of 550 μA/μm and −376 μA/μm, respectively. At 7 K, these devices show SET and SHT characteristics. For the SB-SHT case, the oscillation period is 0.22 V, and the estimated quantum dot size is 16.8 nm. The transconductance is 0.05 μS and 1.2 μS for the SB-SET and SB-SHT, respectively. In the SB-SET and SB-SHT, a high transconductance can be easily achieved as the silicided electrode eliminates a parasitic resistance. Moreover, the SB-SET and SB-SHT can be operated as a conventional field-effect transistor (FET) and SET/SHT depending on the bias conditions, which is very promising for SET/FET hybrid applications. This work is the first report on the successful operations of SET/SHT in Schottky barrier devices.

GaSb nanowire single-hole transistor

We present an experimental study of single hole transistors (SHTs) made from p-type GaSb nanowires. Closely spaced source-drain electrodes are fabricated onto GaSb nanowires to define a SHT within a GaSb nanowire. Room temperature back-gate transfer characteristics show typical hole transport behavior. The fabricated devices are characterized by transport measurements at 1.5 K, where periodic conductance oscillations due to Coulomb blockade are observed and a charging energy of 5 meV is determined.

Atomtronics with holes: Coherent transport of an empty site in a triple-well potential

We investigate arrays of three traps with two fermionic or bosonic atoms. The tunneling interaction between neighboring sites is used to prepare multi-site dark states for the empty site, i.e., the hole, allowing for the coherent manipulation of its external degrees of freedom. By means of an ab initio integration of the Schr\"odinger equation, we investigate the adiabatic transport of a hole between the two extreme traps of a triple-well potential. Furthermore, a quantum-trajectory approach based on the de Broglie-Bohm formulation of quantum mechanics is used to get physical insight into the transport process. Finally, we discuss the use of the hole for the construction of a coherent single hole diode and a coherent single hole transistor.

Fabrication and characterization of an induced GaAs single hole transistor

We have fabricated and characterized a single hole transistor in an undoped AlGaAs-GaAs heterostructure. Our device consists of a p-type quantum dot, populated using an electric field rather than modulation doping. Low temperature transport measurements reveal periodic conductance oscillations due to Coulomb blockade. We find that the low frequency charge noise is comparable to that in modulation-doped GaAs single electron transistors (SETs), and almost an order of magnitude better than in silicon SETs.

Gate induced crossover between Fabry–Pérot and quantum dot behavior in a single walled carbon nanotube hole transistor

Gate induced crossover between Fabry–Pérot and quantum dot behavior in a single walled carbon nanotube (SWCNT) hole transistor is observed. The SWCNT transistor that can operate as a resonant tunneling transistor (RTT) and also as a single-hole transistor (SHT) using SWCNT as channel is fabricated. When negatively high voltage is applied to the gate electrode, the SWCNT transistor shows RTT characteristic, e.g., Fabry–Pérot quantum interference pattern. While, when negatively low voltage is applied to the gate electrode, the SWCNT transistor shows SHT characteristic, e.g., Coulomb diamond characteristic. The transition between RTT and SHT is achieved by modulating the coupling strength between the electrode and the quantum island using gate voltage change. Schottky barriers at the contact between the SWCNT and the electrodes act as tunneling barriers. The thicknesses of the tunneling barriers are modulated by the gate voltage change, and the strength of the coupling between the electrode and quantum island is also changed. The characteristics of the convertible transistor can be observed up to 100K. Moreover, the channel length dependence is observed.

Extremely high flexibilities of Coulomb blockade and negative differential conductance oscillations in room-temperature-operating silicon single hole transistor

A unique feature of the extremely long-range-extended blockade regime with its shape of a long stick, where the Coulomb blockade oscillation and negative differential conductance peak-positions can be systematically and precisely modulated for both extremely-wide VG and VD ranges, was clearly observed in a room-temperature-operating silicon single hole transistor. These results originate from the large quantum level spacing, large tunnel-barrier height, small tunnel-barrier curvature, small bias-induced barrier modulation, and large voltage gain, attributing to the formation of an ultrasmall dot in the gently sloped tunnel barriers along the [100] Si nanowire channel having the large subband modulation.

Room-Temperature Single-Hole Transistors Made Using Semiconductor Carbon Nanotube with Artificial Defects near Carrier Depletion Region

We have succeeded in observing the single hole transistor characteristics in position-controlled grown carbon nanotubes (CNTs) with artificial defects formed by a chemical process. Coulomb blockade characteristics were observed around the hole depletion region even at room temperature. At a low temperature, however, the Coulomb blockade characteristics were observed both in hole and electron transport regions.

Applications of Diamond Surfaces to Electronics and Bioelectronics.

Hydrogen-terminated diamond surface shows p-type conduction even if it is not intentionally doped. Metal-semiconductor (MES) and metal-insulator-semiconductor (MIS) field-effect transistors have been fabricated on hydrogen-terminated diamond surface conductive layers, and their high-frequency performance is demonstrated. Nano-fabrication on a hydrogen-terminated diamond surface is performed by controlling surface adsorbates, using an atomic force microscope (AFM) technique. Insulated areas are successfully obtained by changing hydrogen termination to oxygen termination. Single hole transistors are also fabricated by AFM oxidation, and are operated at liquid nitrogen temperature (77 K). Polycrystalline diamond FET is operated in electrolyte solution. A perfect pinch-off and saturated current-voltage characteristics have been obtained for bias voltages within the potential window. The threshold voltages are almost constant in the electrolytes with different pH values of 7−13. Using this pH insensitive surface, ion selective regions can be fabricated to form transistor-based biosensors.

Single-hole transistor in a p-Si/SiGe quantum well

A single-hole transistor is patterned in a p-Si/SiGe quantum well by applying voltages to nanostructured top gate electrodes. Gating is achieved by oxidizing the etched semiconductor surface and the mesa walls before evaporation of the top gates. Pronounced Coulomb blockade effects are observed at small coupling of the transistor island to source and drain.

Nanodevice fabrication on hydrogenated diamond surface using atomic force microscope

ABSTRACTNanofabrication on a hydrogen-terminated diamond surface is performed usingan atomic force microscope (AFM) anodization. Locally insulated areas less than 30 nm aresuccessfully obtained. Side-gated field effect transistors (FETs) are fabricated using the local anodization, and they operate successfully. Single hole transistors composed ofone side-gated FET and two tunneling junctions are also fabricated and operate at liquid nitrogen temperature (77 K).

Simulation of circuits composed of HTSC-single hole transistors by using superconducting SET-SPICE

We have adapted the single electron transistor SPICE (SET-SPICE) in order to introduce the device model of HTSC-single hole transistor (HTSC-SHT) into the general-purpose circuit simulator SPICE. Some results of the simulation from the SuSET-SPICE are compared with those from the Monte-Carlo reference simulator. This work is based on the semiclassical theory of the single electron tunneling effects, and provides an approach to the simulation of the large scale and hybrid circuits containing superconducting single electron devices.

The active loads based on capacitively coupled HTSC-single hole transistor

Starting with the intrinsic current-voltage properties of the capacitively coupled HTSC-single hole transistor (HTSC-SHT), the intrinsic current-voltage properties of all forms of the active loads based on capacitively coupled HTSC-SHT are studied by using a semi-classical model of the single hole tunneling effect. The small signal equivalent circuit of the active loads is also discussed here, and the conclusions are significant to the design of the HTSC-SHT analog circuits.