Hold Static Noise Margin Research Articles

A boostless write optimised single ended robust 7T SRAM cell for ultra-low power memory design

ABSTRACTA boostless 7T static random access memory SRAM cell with high writability, improved stability and reduced read failure is proposed. The proposed 7T utilises feedback cutting during write operation, which does not require a boosted supply for single access transistor. This technique enhances the writability of the SRAM cell at ultra-low voltage (ULV) supply without any write assist at 90 and 20 nm technology nodes. The proposed 7T SRAM cell has write trip point (WTP) at 85.25 mV, whereas 5T fails to write ‘1’. The mean to sigma ratio (µ/σ) is improved by a factor of 1.08× and 7.14× for hold static noise margin (HSNM) and read margin, respectively, as compared to standard 5T at 300 mV in UMC 90 nm process technology. This also saves 26.41% read and 22.72% write power as compared to 5T SRAM cell at 300 mV. Moreover 7T also shows an improvement of 2.91% in HSNM and 1.85% in read margin by using FinFET technology.

Single-Ended Boost-Less (SE-BL) 7T Process Tolerant SRAM Design in Sub-threshold Regime for Ultra-Low-Power Applications

A novel single-ended boost-less 7T static random access memory cell with high write-ability and reduced read failure is proposed. Proposed 7T cell utilizes dynamic feedback cutting during write/read operation. The 7T also uses dynamic read decoupling during read operation to reduce the read disturb. Proposed 7T writes "1" through one NMOS and writes "0" using two NMOS pass transistors. The 7T has mean $$(\mu )$$(μ) of 222.3 mV (74.1 % of supply voltage) for write trip point where 5T fails to write "1" at 300 mV. It gives mean $$(\mu )$$(μ) of 276 mV (92 % of supply voltage) for read margin, while 5T fails due to read disturb at 300 mV. The hold static noise margin of 7T is maintained close to that of 5T. The read operation of 7T is 22.5 % faster than 5T and saves 10.8 % read power consumption. It saves 36.9 % read and 50 % write power consumption as compared to conventional 6T. The novel design of proposed 7T consumes least read power and achieves the lowest standard deviation as compared to other reported SRAM cells. The power consumption of 1 kb 7T SRAM array during read and write operations is 0.70$$\times $$× and 0.65$$\times $$×, respectively, of 1 kb 6T array. The techniques used by the proposed 7T SRAM cell allow it to operate at ultra-low-voltage supply without any write assist in UMC 90 nm technology node. Future applications of the proposed 7T cell can potentially be in low-voltage, ultra-low-voltage and medium-frequency operations like neural signal processor, sub-threshold processor, wide-operating-range IA-32 processor, FFT core and low-voltage cache operation.

Adaptive Technique for Overcoming Performance Degradation Due to Aging on 6T SRAM Cells

The threshold voltage drifts induced by positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI) weaken nMOS and pMOS, respectively. These long-term aging threshold voltage drifts degrade SRAM cell stability, margin, and performance. This paper presents a low area overhead adaptive body bias (ABB) circuit that compensates BTI aging effects and also improves performance of an aged SRAM cell. The proposed circuit uses a control circuit and word line voltage to control the voltage applied to the body of 6T SRAM cell's transistors such that the BTI effect dependence of threshold voltage is reduced. In the worst case, the proposed ABB reduces the HOLD SNM degradation by 6.85%, the READ SNM degradation by 12.24%, the WRITE margin degradation by 2.16%, the READ delay by 28.68%, and the WRITE delay by 32.61% compared to the conventional SRAM cell at 108 s aging time.

High-Performance and Robust SRAM Cell Based on Asymmetric Dual-$k$ Spacer FinFETs

This paper proposes a new asymmetric underlap Fin-Field Effect Transistor (FinFET) structure using a dual- k spacer. Asymmetric dual-spacer at source shows excellent gate control over the channel due to increase in the outer fringe field at gate/source underlap. Hence, this structure exhibits a superior short-channel effect metric over the conventional/single-spacer underlap FinFET. The proposed asymmetric structure enhances static random access memories (SRAMs) performance in terms of robustness, access times as well as leakage power during the hold, read, and write operations. The hold static noise margin and write margin increases by 5.16% and 5.66%, respectively. The read stability enhances by 13.75% and 19.35% over conventional FinFET SRAM circuit. Furthermore, the leakage power reduces by 60%, and write access time improves by 23.63%. Compared with conventional FinFET-based SRAM, same bit-cell area and read delay are associated with the proposed structure. Supply voltage scalability on SRAM design metrics is also investigated. In addition to SRAM application, underlap length, lateral source/drain doping gradient, and the high- k spacer width are optimized for high-performance digital applications.

Heterojunction Intra-Band Tunnel FETs for Low-Voltage SRAMs

We propose heterojunction intra-band tunnel (HIBT) FETs based on different semiconductor materials (with matched lattice constants) for the source/drain (S/D) and channel. HIBT FETs have an energy band offset at the interface of the S/D and channel. As a result, carrier transport in the on state occurs by intra-band tunneling. We analyze the device characteristics of HIBT FETs with Si S/D and GaP channel for different values of band offsets. We show that, due to intra-band tunneling, HIBT FETs exhibit lower on current at iso-off current compared to Si double gate (DG) MOSFETs. However, the energy band offset at the S/D-channel interface leads to 40%-59% lower drain-induced barrier lowering/thinning and significantly reduced variation in off current across a range of supply voltages (VDD). Moreover, due to the heterovalent nature of S/D and channel materials, there is negligible dopant straggle in HIBT FETs, which further improves their process variation tolerance. We evaluate the impact of low off-current variations in HIBT FETs on 6T SRAM stability and leakage. Considering the worst case parameter variations at VDD = 0.4 V, HIBT-FET-based 6T SRAMs show 1.56X to 2.85X reduction in cell leakage, 1.28X to 1.58X increase in read static noise margin (SNM), 1.04X to 1.07X higher hold SNM, and 1.7X to 3X increase in write margin compared to Si-DG-MOSFET-based 6T SRAM. The enhancement of cell stability and reduction in cell leakage at low VDD under process variations make HIBT FETs suitable for low-voltage SRAMs.

Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs

In this work, we propose three novel independently-controlled-gate Schmitt Trigger (IG_ST) FinFET SRAM cells for sub-threshold operation. The proposed IG_ST 8 T SRAM cells utilize split-gate FinFET devices with the front-gate devices serving as the stacking devices, and the back-gate devices serving as the intermediate node conditioning devices to provide built-in feedback mechanism for Schmitt Trigger action, thus reducing the cell transistor count/area and achieving improved static noise margin (SNM) and better tolerance to process variation and random variations. 3-D mixed-mode simulations are used to evaluate the Read static noise margin (RSNM), Write static noise margin (WSNM), hold static noise margin (HSNM), and Standby leakage of proposed cells, and results are compared with the standard 6 T cells and previously reported 10 T Schmitt Trigger sub-threshold SRAM cells. Compared with the conventional tied-gate 6 T cell, the proposed IG_ST SRAM cells demonstrate 1.81X and 2.11X higher nominal RSNM at VCS= 0.4 and 0.15 V, respectively. The cell layouts and areas are assessed based on scaled ground rules from 32 nm node, and the density advantage over previously reported 10 T Schmitt Trigger sub-threshold SRAM cells are illustrated. The cell AC performance (Read access time, Write time, and Read access time versus the number of cells per bit-line considering worst-case data pattern for bit-line leakage) and temperature dependence are evaluated, and shown to be adequate for the intended sub-threshold applications. Compared with previously reported 10 T Schmitt Trigger sub-threshold SRAM cells, the proposed cells exhibit comparable or better RSNM, higher density, and lower Standby leakage current. 3-D mixed-mode Monte Carlo simulations are performed to investigate the impacts of process variations (Leff, EOT, Wfin, and Hfin) and random variations (Gate LER and Fin LER) on RSNM, WSNM, and HSNM. Our results indicate that even at the worst corner, two of the proposed cells can provide sufficient margin of μ/σ ratio.

A Circuit for Robustness Enhancement of the Subthreshold SRAM Bitcell in 65nm Technology

This paper describes a circuit which can enhance the robustness of the subthreshold 6T SRAM bitcell. The proposed circuit can dynamically adjust the body voltages of the PMOS transistors in order to enhance the robustness of the subthreshold 6T SRAM bitcell by detecting the variation of the threshold voltage. The simulation results under 300mV in 65nm technology demonstrate that the mean values of the read and hold static noise margin (SNM) of the subthreshold 6T SRAM bitcell have been improved by 18% and 0.7%, respectively, meanwhile the standard values of the read and hold SNM have improved by 82% and 29.4%, respectively, by adopting the proposed circuit. Moreover, the proposed circuit functions well in a wide range of supply voltage from 0.2V to 0.5V.

Asymmetrically Doped FinFETs for Low-Power Robust SRAMs

We propose FinFETs with unequal source and drain doping concentrations [asymmetrically doped (AD) FinFETs] for low-power robust SRAMs. The effect of asymmetric source/drain doping on the device characteristics is extensively analyzed, and the key differences between conventional and AD FinFETs are clearly shown. We show that asymmetry in the device structure leads to unequal currents for positive and negative drain biases, which is exploited to achieve mitigation of read-write conflict in 6T SRAMs. The proposed device exhibits superior short-channel characteristics compared to a conventional FinFET due to reduced electric fields from the terminal that has a lower doping. This results in significantly lower cell leakage in AD-FinFET-based 6T SRAM. Compared to the conventional FinFET-based 6T SRAM, AD-FinFET SRAM shows 5.2%-8.3% improvement in read static noise margin (SNM), 4.1%-10.2% higher write margin, 4.1%-8.8% lower write time, 1.3%-3.5% higher hold SNM, and 2.1-2.5 lower cell leakage at the cost of 20%-23% higher access time. There is no area penalty associated with the proposed technique.

A novel high reliability CMOS SRAM cell

A novel 8T single-event-upset (SEU) hardened and high static noise margin (SNM) SRAM cell is proposed. By adding one transistor paralleled with each access transistor, the drive capability of pull-up PMOS is greater than that of the conventional cell and the read access transistors are weaker than that of the conventional cell. So the hold, read SNM and critical charge increase greatly. The simulation results show that the critical charge is almost three times larger than that of the conventional 6T cell by appropriately sizing the pull-up transistors. The hold and read SNM of the new cell increase by 72% and 141.7%, respectively, compared to the 6T design, but it has a 54% area overhead and read performance penalty. According to these features, this novel cell suits high reliability applications, such as aerospace and military.