HKMG Stack Research Articles

Experimental Investigation of Ultrathin Al₂O₃ Ex-Situ Interfacial Doping Strategy on Laminated HKMG Stacks via ALD

In this work, a p-type high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> metal gate (HKMG) with 3-nm interfacial Al₂O₃ doping HfO₂ laminated dielectric is presented to achieve the required gate electrode effective work function (EWF). Through the ex-situ interfacial doping strategy with various Al₂O₃ thickness, the electrical and interface characteristics of p-type HKMG MOSCAP are investigated. The results show that these parameters are strongly dependent on the thickness of the Al₂O₃. By increasing the Al₂O₃ thickness, the flat-band voltage (<inline-formula> <tex-math notation="LaTeX">${V}_{\text {FB}}$ </tex-math></inline-formula>) positive shift is elevated by 360 mV, and the trap/detrap electrons density (<inline-formula> <tex-math notation="LaTeX">${N}_{\text {ot}}$ </tex-math></inline-formula>) is significantly suppressed by an order of magnitude. In addition, the interface charge density (<inline-formula> <tex-math notation="LaTeX">${N}_{\text {SS}}$ </tex-math></inline-formula>) is significantly reduced, and interface trap density (<inline-formula> <tex-math notation="LaTeX">${D}_{\text {it}}$ </tex-math></inline-formula>), time-dependent dielectric breakdown (TDDB), and positive bias stress (PBS) is obviously improved. Finally, EWF modulation was increased from 4.976 to 5.206 eV (over the valence band edge of 5.17 eV). The results reveal that it is possible to tailor dielectric and electrical properties of high-<inline-formula> <tex-math notation="LaTeX">${k}$ </tex-math></inline-formula> layers by adding a proper amount of interfacial Al₂O₃ doping into HfO₂, meeting the criteria required for gate electrode p-type EWF. These results and discussion provide an effective method for the integration of the HKMG stack in the MOSFETs and also useful for design of CMOS integration.

Overview of Bias Temperature Instability in Scaled DRAM Logic for Memory Transistors

Continued scaling of DRAM technologies has required a limitation of the power dissipation from the logic components on-chip, while downscaling both transistor oxide thickness and gate length. One route to enable further scaling, while circumventing excessive leakage currents, is the integration of high-permittivity ( ${\kappa }$ ) metal-gate (HKMG) components into the logic and high-voltage (e.g., I/O) devices. The requirement of a gate-first flow for devices in the peripheral region introduces significant reliability challenges. Even though Negative Bias Temperature Instability (NBTI) performance of CMOS and memory thermal budget compatible transistors are aligned with conventional HKMG integration with thin oxide devices, it is not the case for thick oxide devices. In particular, it will be shown that strong NBTI lifetime degradation is observed as soon as high- ${\kappa }$ layers are deposited on top of the thick interfacial layer. In this work, a review of the impact of these high- ${\kappa }$ layers on the NBTI high voltage logic for memory devices is presented. The stress induced degradation is correlated to a diffusion of metal atoms from the HKMG gate stack towards the silicon surface. Directions for reliability improvements are then defined. The presence of Nitrogen throughout the HKMG stack can originate either from high- ${\kappa }$ processing or metal-nitride gate electrode. It is shown that preventing nitrogen diffusion towards the Si/SiO2 interface region, together with AlOx and/or F incorporation at the HKMG interface, can tune device threshold voltage and modulate access to donor trap-defect bands. The result of these effects is a vast improvement in NBTI performance. A detailed study of NBTI-degradation, supported by physical analysis, assessing the impact of various tuning components within the stack (interface layer, high- $\kappa $ fluorination and/or cap, metal gate) will be presented. Potential solutions for this reliability challenge will be reported.

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.

Investigation of the Process of Plasma Through Etching of HkMG Stack of Nanotransistor with a 32-nm Critical Dimension

The processes of plasma etching of stack layers to form a structure of a metal gate of a nanoscale transistor with a dielectric with a high level of dielectric permittivity (HkMG) are investigated. A resist mask formed by fine-resolution electron-beam lithography is used in the etching. The plasma etching of the stack’s layers is carried out in one technological etching cycle without a vacuum break. The sequential anisotropic etching process of the stack of polysilicon, tantalum nitride, and hafnium nitride, as well as the etching process of the gate insulator based on hafnium oxide with a high degree of selectivity in relation to the underlying crystalline silicon, which guarantees the complete removal of the layer of hafnium oxide and the minimal loss of the silicon layer (not more than 0.5 nm), is investigated.

Study of HKMG Stack Interface Engineer Applicable to 22nm/16nm Finfet Mosfet

Since Intel announced that they had made a great breakthrough in 22nm node[1][2]on May 4, 2011, FinFET Transistor structures had almost controlled CMOS technology beyond 22nm node. In this node, with the development of lithography, silicide process was switched to the back end. This huge change bring benefit to the formation of HKMG stack interface engineer. Before the silicide step switched, limited by the already formed silicide, the growth temperature of interfacial oxide layer couldn’t be higher than 600°C for NiSi unstability at high temperature, but now 800°C or 850°C will also be allowed. So we could adopt thermal oxide as HKMG stack interface layer. In this paper, as interface layer of HKMG stack, chemical and thermal oxide were all studied. In 32nm/22nm node Bulk Planar CMOS technology, chemical oxide was grown through spraying DI water diluted Ozone on bare silicon substrate which was generally used in industry. It’s advantage was low thermal budget and the disadvantage was thermal unstability of Chemical ox during ALD HfOX growth. ChemOX would diffuse into HK dielectric, referred to Fig 1(b). It could also be observed very clearly at Si/ChemOX/RTCVD SIN structure , referred to Fig 2(b). From Fig 1(a) and Fig 2(a) , we had no doubt about the stability of thermal oxide interface layer. In this article, We chose three different thermal oxidation methods which were RTO, ISSG alone, ISSG with plasma nitridation[3][4]respectively. Considering the state of silicon substrate surface would severely affect the quality of ultrathin interface oxide layer, we also chose two different cleaning process which were HF 100:1 and BOE 100:1 last.In conclusion, in order to improve HKMG stack characteristic in FinFET Transistor structures, different interface layer and cleaning process had been studied. Considering the thermal unstability of Chemical oxidation method currently used in industry, we plan to take high quality thermal ultrathin interface oxide into 22nm node and beyond.

Atomic Layer Deposition of SiN for spacer applications in high-end logic devices

Continuous down scaling of transistor size resulted in introduction of high-k material to replace the conventional gate oxide. High-k Metal Gate implementation brings new challenges to the subsequent processing steps of the device. Both oxide ingress and removal of the HKMG stack during later cleaning steps must strictly be avoided. We have developed and optimized an ALD SiN encapsulation liner which protects the HKMG stack and also serves as a robust spacer for subsequent ion implantation. SiN was chosen because of its oxide-blocking characteristics and its durability in diluted hydrofluoric acid. We developed sophisticated ALD processes using ionized ammonia radicals and dichloro-silane. This ALD process has several advantages compared to conventional LPCVD or PECVD processes: Superior thickness control and uniformity, excellent step coverage and no loading effects. In addition, process temperature could be reduced to 500°C, which is shown to be critical for protecting the HKMG stack. Further reduction in process temperature to 400°C is also demonstrated using a novel precursor.