Histogram Test Research Articles

The Histogram Test of ADCs With Sinusoidal Stimulus Is Unbiased by Phase Noise

This paper intends to show that the presence of normally distributed phase noise or jitter in the test setup or in the analog-to-digital converter (ADC) itself does not cause a bias in the sinusoidal histogram test estimation of the transfer function of an ADC. The analytical proof presented demonstrates that there is no need to use an extra overdrive when stimulating the ADC, as is the case with amplitude noise.

Current mode ADC design in a 0.5-μm CMOS process

This paper presents a pipelined current mode analog to digital converter (ADC) designed in a 0.5-μm CMOS process. Adopting the global and local bias scheme, the number of interconnect signal lines is reduced numerously, and the ADC exhibits the advantages of scalability and portability. Without using linear capacitance, this ADC can be implemented in a standard digital CMOS process; thus, it is suitable for applications in the system on one chip (SoC) design as an analogue IP. Simulations show that the proposed current mode ADC can operate in a wide supply range from 3 to 7 V and a wide quantization range from ±64 to ±256 μA. Adopting the histogram testing method, the ADC was tested in a 3.3 V supply voltage/±64 μA quantization range and a 5 V supply voltage/±256 μA quantization range, respectively. The results reveal that this ADC achieves a spurious free dynamic range of 61.46 dB, DNL/INL are −0.005 to +0.027 LSB/–0.1 to +0.2 LSB, respectively, under a 5 V supply voltage with a digital error correction technique.

Nano-mechanics based modeling of lifetime distribution of quasibrittle structures

The statistics of structural lifetime under constant load are related to the statistics of structural strength. The safety factors applied to structural strength must ensure failure probability no larger than 10 - 6 , which is beyond the means of direct verification by histogram testing. For perfectly brittle materials, extrapolation from the mean and variance to such a small tail probability is no problem because it is known that the Weibull distribution applies. Unfortunately, this is not possible for quasibrittle materials because the type of cumulative distribution function (cdf) has been shown to vary with structure size and shape. These are materials with inhomogeneities and fracture process zones (FPZ) that are not negligible compared to structural dimensions. A probabilistic theory of strength of quasibrittle structures failing at macro-crack initiation, which can be experimentally verified and calibrated indirectly, has recently been deduced from the rate of jumps of atomic lattice cracks governed by activation energy barriers. This paper extends this nano-mechanics based theory to the distribution of structural lifetime. Based on the cdf of strength and a power law for subcritical crack growth rate, the lifetime cdf of quasibrittle structures under constant loads is derived. The lifetime cdf is shown to depend strongly on the structure size as well as geometry. It is found that, for the creep rupture case, the mean structural lifetime exhibits a very strong size effect, much stronger than the size effect on the mean structure strength. The theory also implies temperature dependence of the lifetime cdf. For various quasibrittle materials, such as industrial ceramics and fiber composites, it is demonstrated that the proposed theory correctly predicts the experimentally observed deviations of lifetime histograms from the Weibull distribution.

Precision of Independently Based Gain and Offset Error of an ADC Using the Histogram Method

Two of the parameters that are determined when testing an analog-to-digital converter (ADC) are the gain and offset errors. One of the ways to define these two parameters is called ldquoindependently based.rdquo In this paper, we derive the precision of the gain and offset errors estimated with the histogram test method affected by additive noise.

Combined Self-Test of Analog Portion and ADCs in Integrated Mixed-Signal Circuits

Testing is a critical stage in integrated circuits production in order to guarantee reliability. The complexity and high integration level of mixed-signal ICs has put forward new challenges to circuit testing. This paper describes an oscillation-based combined self-test strategy for the analog portion and analog-to-digital converters (ADCs) in integrated mixed-signal circuits. In test mode, the analog portion under test is reconfigured into an oscillator, generating periodic signals as the test stimulus of ADC. By analyzing the A/D conversion results, a histogram test of ADC can be performed, and the oscillation frequency as well as amplitude can be checked, and in this way the oscillation test of the analog portion is realized simultaneously. For an analog benchmark circuit combined with an ADC, triangle oscillation and sinusoid oscillation schemes are both given to test their faults. Experimental results show that fault coverage of the analog portion is 92.2% and 94.3% in the two schemes respectively, and faults in the ADC can also be tested.

A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduces the hardware overhead and testing time while detecting any static faults in an ADC.

On improving training time of neural networks in mixed signal circuit fault diagnosis applications

Testing issues are becoming more and more important with the quick development of both digital and analog circuit industry. Analog-to-digital converters (ADCs) are becoming more and more widespread owing to their fundamental capacity of interfacing analog physical world to digital processing systems. In this paper, we study the use of neural networks in fault diagnosis of ADCs and compare the results with other ADC testing approaches such as histogram, FFT and sinewave curve fit test techniques. In this paper, we introduced the idea of separation of neural network’s output matrix to improve the training phase time, called ‘index-separation’ approach. Finally, we concluded that training time in this method is about 0.25 times as much as that in the normal training method. We also concluded that this approach does not affect network’s decision strength. Besides, we concluded that if the complexity of the circuit increases, this method will still be effective. Therefore, this method is a robust way for fault diagnosis of mixed signal circuits.

A Histogram-Based Testing Method for Estimating A/D Converter Performance

A sine-wave histogram-testing structure for analog-to-digital converters (ADCs) is proposed. The ADC static parameters, i.e., offset error, gain error, and nonlinearity errors, are directly obtained from the sine-wave histogram test. Then, the obtained static parameters are related to the estimation of the degraded signal-to-noise ratio (SNR) value. Therefore, the relationships among these parameters are analyzed, and a single sine-wave histogram test can be performed to evaluate the ADC. With the appropriate approximations in the reference sine-wave histograms and the estimations of the ADC parameters, the realization of an ADC output analyzer circuit could be a simple task. An ADC output analyzer circuit is therefore developed and synthesized using a 0.18-mum technique to analyze the outputs of an 8-bit ADC and estimate its performances using the proposed method.

Standard Histogram Test Precision of ADC Gain and Offset Error Estimation

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The quality of measurements made in any system is quantified by supplying the expanded uncertainty of the result, as recommended in the Guide to Uncertainty in Measurement. In a system that involves analog-to-digital converters (ADCs), one of the sources of uncertainty is the converter's gain and offset error. The uncertainty of these two parameters should be known in order to compute the uncertainty of the measurements made with the system. In this paper, we study the uncertainty of terminal-based defined gain and offset error that are estimated using a standard histogram test in the presence of an additive noise. </para>

Histogram Tests for Wideband Applications

Characterization and testing of analog-to-digital converters (ADCs) are important for many reasons. A histogram test is a common method to characterize the linearity features of an ADC. Two commonly used stimulus signals are sine waves and Gaussian noise. This paper presents a metrological comparison between Gaussian and sine-wave histogram tests for wideband applications, that is, we evaluate the performance of the characterization of the ADC and the usability of postcorrection. A postcorrection procedure involves the characterization of the ADC nonlinearity and then the use of this information by processing the ADC output samples to remove the distortion. The results show that the Gaussian histogram test gives reasonable accuracy in measuring nonlinearities. However, it does not result in a suitable model for postcorrection in wideband applications. A single-tone sine-wave histogram will be a better basis for postcorrection. The best result can be obtained if the lookup table is trained with several single-tone sine waves in the frequency band.

Using the histogram test to quantify reaction coordinate error

Many schemes for calculating reaction rates and free energy barriers require an accurate reaction coordinate, but it is difficult to quantify reaction coordinate accuracy for complex processes like protein folding and nucleation. The histogram test, based on estimated committor probabilities, is often used as a qualitative indicator for good reaction coordinates. This paper derives the mean and variance of the intrinsic committor distribution in terms of the mean and variance of the histogram of committor estimates. These convenient formulas enable the first quantitative calculations of reaction coordinate error for complex systems. An example shows that the approximate transition state surface from Peters' and Trout's reaction coordinate for nucleation in the Ising model gives a mean committor probability of 0.495 and a standard deviation of 0.042.

Simple and Time-Effective Procedure for ADC INL Estimation

This paper deals with a novel testing technique aimed at estimating the accuracy of analog-to-digital converters (ADCs). The main advantage of the proposed approach is the higher testing speed, particularly the ability to achieve an accurate estimate of the low-frequency component (LCF) of the integral nonlinearity (INL) pattern of an ADC in a time that may be even one order of magnitude shorter than that of other standard techniques such as the sine wave histogram test (SHT). The estimation accuracy associated with the testing procedure is determined theoretically and validated by means of simulations and experimental results

Truncated Gaussian noise in ADC histogram tests

One method to characterize analogue to digital converters (ADCs) is to use a histogram, where Gaussian noise may be used as stimulus signal. However, a Gaussian noise signal that excites all transition levels also generates input values outside working range of the ADC. Modern signal generators can generate arbitrary signals. Hence, excluding undesired values outside the ADC full scale can minimize test sequences. Truncating the signal to the working range gives further advantages, which are explored in this paper. The Cramér-Rao lower bound and a minimum variance estimator for histogram tests with an arbitrary stimulus are derived. These are applied for truncated Gaussian noise and the result is theoretically evaluated and compared to untruncated noise. It is shown that accuracy increases for a fixed sample length and that variation over transition levels decrease.

Noise sensitivity of the exponential histogram ADC test

This paper deals with some error effects caused by additive noise at analogue-to-digital converters (ADCs) testing based on the histogram method and the exponential shape of input testing stimulus. The histogram method with the exponential stimulus has been an alternative test method for ADC that was developed by the authors of this paper. Here, the theoretical analysis of some errors in estimations of code bin widths and quantisation levels caused by additive input Gaussian noise is performed. The theoretical results are verified by simulations and experimental tests. Finally the noise sensitivity of the exponential histogram test method is compared with the known noise sensitivity of the standardised sinewave histogram test method.

Fast estimation of ADC nonlinearities using the Sinewave Histogram Test

The Sinewave Histogram Test (SHT) is a widely used standard technique to estimate the threshold voltages and the Integral NonLinearity (INL) pattern of Analog-to-Digital Converters (ADCs). The main drawback of the SHT is that, for a given target accuracy, the number of test samples as well as the testing time tend to increase exponentially as the resolution of the converter grows. The strategy described in this paper still relies on the SHT, but it enables a major reduction in testing time without affecting estimator accuracy provided that the INL pattern exhibits prevailingly a low code frequency content. This result can be achieved simply by suitably filtering the INL pattern obtained using a standard SHT over a reduced amount of test samples. After being justified theoretically, the proposed solution is validated by means of both simulations and experimental evidences.

Overdrive in the Ramp Histogram Test of ADCs

This paper presents a study about the amount of overdrive to use when analog-to-digital converters (ADCs) are tested with the ramp histogram method. Overdrive is used to limit the error induced by input-equivalent noise in the estimation of the ADC transition voltages. This study has direct application in the new coarse ramp static test.

Combined Spectral and Histogram Analysis for Fast ADC Testing

The integral nonlinearity (INL) of analog-to-digital converters (ADCs) can be described by a behavioral error model expressed as one-dimensional image in the code domain. This image consists of low and high code frequency components which allow describing the ADC performance with a small number of parameters. This paper presents new methods for low code frequency and high code frequency testing. The identification of the low code frequency components is performed by multiharmonic sine fitting in the time domain. The high code frequency components are estimated in the statistical domain by a narrow band histogram test using a triangular stimulus signal. The performance of the proposed method is assessed for various ADC devices.

Effective ADC linearity testing using sinewaves

This paper deals with the effectiveness of the sinewave histogram test (SHT) for testing analog-to-digital converters. The implementation is discussed, with respect to the adopted procedures and to the choice of relevant parameters. Some of the published approximations currently limiting the characterization of the test performance are removed. The statistical efficiency of the SHT is evaluated by comparing the associated estimator variance with the corresponding Crame/spl acute/r-Rao lower bound, theoretically derived assuming sinewaves corrupted by Gaussian noise. Finally, both simulation and experimental results are presented to validate the proposed approach.

Efficient BIST scheme for A∕D converters

As SOC and complex systems usually include analogue IPs, it becomes more important to test analogue devices efficiently. The reason for this is that analogue testing for high quality requires substantial testing costs although the analogue portion in a whole chip or in a system is usually very small. In the paper, an efficient low-cost built-in self-test (BIST) scheme is developed for testing A/D converters. The key ideas are to use a triangular wave as a test input signal and to analyse the output response for functional testing. In order to perform functional testing, new fault models called successive value, oscillation and bit faults are proposed. Testing these faults guarantees the quality of A/D converters. For experimental results, a D-S A/D converter and a pipeline A/D converter are used. The results show that the new BIST scheme is very efficient in terms of fault coverage and hardware overhead. the presence of pre-existing DSP capabilities and the presence of both an A/D converter and a D/A converter. Another BIST approach uses pulse response sampling (4). This BIST uses pulse trains of varying duty ratio, generated from a digital linear feedback shift register (LFSR), as a test stimulus. The responses of the device under test (DUT) are sampled and compared with reference voltages to generate binary sequences that can be compressed to yield a signature for the anticipated responses. The BIST scheme using pulse response sampling has the advantage of a very small hardware overhead, but it takes a long time to test in high fault conditions. Finally, the BIST architecture, which is most widely known, is a histogram-based analogue BIST architecture (5-7). This method is based on statistical analysis of the A/D converter output code. In this approach, an analogue signal is applied to the A/D converter input and the number of times each code appears on the A/D converter output is recorded. These recorded samples are compared with theoretical values and then the BIST makes a decision whether the A/D converter is fault- free or faulty. To store both the measured and ideal histograms, the histogram test technique requires a large amount of hardware resources both in terms of memory and operative resources. In addition, a large number of samples and several successive periods of the signal are required to achieve satisfactory results. This paper investigates the viability of a new BIST approach. The input test signal waveform of A/D converters is a triangular wave obtained from an integrator. Then the output of the A/D converters is compared with the reference voltages, which are related to the three defined fault models used by the BIST. The proposed scheme is applicable to any A/D converter because it is related to functional testing. Comparing this new BIST with other BIST, this scheme does not need any DSP resources. Moreover, the proposed BIST has a small hardware overhead but achieves high fault coverage. Just three periods of input signal are required to achieve high fault coverage, so test time is reduced. 2 New test methodology

INL Reconstruction of A/D Converters via Parametric Spectral Estimation

The work presented in this paper builds on previous research done by the authors in detailing a novel procedure for obtaining a very fast measurement of the integral nonlinearity of an analog-to-digital converter (ADC). The core of the method is the parametric spectral estimation of the ADC output; the static characteristic is subsequently reconstructed as a sum of Chebyshev polynomials, in accordance with a previously developed procedure. The method allows one to test an ADC with sinusoids of any reasonable amplitude (even a slight overdrive is allowed), frequency (no synchronization is needed), and phase (which is digitally compensated). This approach is less accurate than the histogram test but incomparably faster (about 8000 samples are sufficient regardless of the ADC resolution).