High-speed Successive Approximation Register Research Articles

A 0.0012 mm2 6-bit 700 MS/s 1 mW Calibration-Free Pseudo-Loop-Unrolled SAR ADC in 28 nm CMOS

This paper presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. By utilizing the output of the dynamic amplifier (DA) to generate an asynchronous clock, the reset time for the DA can be hidden behind the comparator latching time. Dedicated latches for each digital-to-analog converter (DAC) element eliminate the need for DAC switching logic. The proposed inverter-inserted three-stage comparator significantly reduces the input-referred offset of the comparator. The prototype 6-bit 700 MS/s SAR ADC was implemented in a 28 nm CMOS process and has a small 0.0012 mm2 area. The measured peak DNL and INL without any mismatch calibration were 0.33 and 0.27 LSB, respectively. With Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 34.07 and 47.52 dB, respectively. The power consumption was 1 mW under a supply voltage of 1.0 V, leading to a Walden figure of merit (FoM) of 34.6 fJ/conversion-step at 700 MS/s.

10-Bit 5 MS/s Successive Approximation Register Analog-to-Digital Converter with a Phase-Locked Loop and Modified Bootstrapped Switch for a BLDC Motor Drive

In this paper, we present a successive approximation register (SAR) analog-to-digital converter (ADC) with a charge-pump (CP) phase-locked loop (PLL) and a bootstrapped switch, also called PLL-SAR ADC. To meet system-on-chip (SOC) and industrial requirements, the proposed SAR ADC and the control circuits of electric vehicles must be integrated into a single chip and be fabricated using the TSMC 0.25-μm 1P3M complementary metal oxide semiconductor (CMOS) high-voltage process. It is difficult to implement a high-speed SAR ADC with the TSMC 0.25-μm CMOS high-voltage process because it includes an N-type buried layer, which shorts all p-type metal oxide semiconductor field-effect transistor (PMOSFET) bodies together to withstand high voltages. In the proposed PLL-SAR ADC, two clock signals, an external clock signal and an internal clock signal from the CP-PLL, are provided to guarantee that a correct clock signal is fed. This design improves the robustness of the designed system. A monotonic capacitor-switching procedure is considered to reduce power consumption. Furthermore, a bootstrapped switch was added along with a dummy switch and a dummy transistor to eliminate disturbances in the input voltages and to improve the device’s anti-noise capability. Moreover, a two-stage dynamic comparator was used to prevent kickback noise induced by the parasitic capacitors. The measurements indicate that the signal-to-noise-and-distortion ratio, effective number of bits, power consumption, and chip area are 53.82 dB, 8.65 bits, 1.256 mW, and 1.261 × 0.975 mm2, respectively. The FoM is approximately 0.625 pJ/conv-step at 1.256 mW, 8.65 bits, and 5 MS/s. The high sampling rate of 5 MS/s and high accuracy of 8.65 bits are the main advantages of the proposed PLL-SAR ADC.

A 15-bit, 5 MSPS SAR ADC with on-chip digital calibration

In this paper, a digital algorithm based on a 15-bit, 5 million samples per second (MSPS), high-speed successive approximation register (SAR) analog-to-digital converter (ADC) is presented. It features on comparator offset cancellation and capacitor mismatch calibration. The algorithm uses a 13-bit bypass array to measure the errors of both comparator and capacitors. During calibration, errors are read and put into the bypass array to compensate for the mismatches of the main array. Verified by MATLAB, the errors of the SAR ADC output can be corrected into 1 LSB with the help of calibration. The simulation results show that the proposed algorithm improves the precision of the SAR ADC significantly.

A 10-bit 120-MS/s SAR ADC With Reference Ripple Cancellation Technique

This article presents a reference ripple cancellation technique for high-speed successive approximation register analog-to-digital converters (SAR ADCs) to address the reference voltage settling issue. Unlike prior techniques that aim to minimize the reference ripple, this article proposes a new perspective: it provides an extra path for the full-sized reference ripple to couple to the comparator but with an opposite polarity, so that the effect of the reference ripple is canceled out, thus ensuring an accurate conversion result. To verify the proposed technique, a prototype 10-bit 120-MS/s SAR ADC is fabricated in a 40-nm CMOS process. The proposed ripple cancellation technique improves the signal-to-noise and distortion ratio (SNDR) by 8 dB and reduces the worst case integrated non-linearity (INL)/differential non-linearity (DNL) by ten times. Overall, the ADC achieves an SNDR of 55 dB with only 3-pF reference decoupling capacitor.

Analysis of Reference Error in High-Speed SAR ADCs With Capacitive DAC

The high-speed successive-approximation-register (SAR) analog-to-digital converters (ADCs) rely on the switched capacitive digital-to-analog converter (CDAC) to perform the fast transition, which causes voltage ripples at the output of the reference circuits. Such ripples lead to the reference error that eventually prolongs the time for DAC settling. To minimize such error with a short available time, it either demands a power-hungry reference buffer or large die area for the decoupling. In this paper, we offer a comprehensive analysis of the reference errors in SAR ADCs with a practical reference network circuit (RNC) in consideration. A circuit model is developed in order to quantify the error amplitude for the critical DAC settling condition. Based on the proposed model, the settling behavior of the DAC with reference buffer can be precisely characterized, leading to a better understanding about the design tradeoff of the RNC. Finally, the developed model is verified by both circuit level simulations and measurement results.

A 1.4-mW 10-Bit 150-MS/s SAR ADC With Nonbinary Split Capacitive DAC in 65-nm CMOS

This brief presents a high-speed successive approximation register analog-to-digital converter (ADC) with nonbinary searching technique. By inserting redundancy in the first five decision steps, the digital-to-analog converter (DAC) settling errors can be tolerated and settling time can thus be reduced. In addition, split capacitor technology has also been adopted to further boost the conversion speed. With split switching method, no common mode voltage is needed in DAC reset phase and dynamic offset can be removed as well. Full adder-based encoder is employed to convert the raw 11-bit to 10-bit binary codes, showing less power penalty. The prototype ADC fabricated in 65-nm CMOS achieves 51.1 dB SNDR and 62.3 dB SFDR at 150-MS/s sampling rate. It consumes 1.4 mW, resulting in a Walden figure of merit of 31.8 fJ/conversion step.

A 6-bit 0.81-mW 700-MS/s SAR ADC With Sparkle-Code Correction, Resolution Enhancement, and Background Window Width Calibration

This paper presents a 6-bit high-speed successive approximation register analog-to-digital converter (ADC) with sparkle-code correction. By quantizing the comparator decision time (CDT), the sparkle codes are identified and corrected, reducing the error rate from 10−4 to below 10−9. Furthermore, CDT quantization enables 1-bit increase in the ADC resolution by setting the detection boundary to be ±0.25 LSB. Thus, only five comparison cycles are needed to reach 6 bits, leading to an increased ADC speed. A novel dither-based background calibration technique is devised to accurately control the CDT detection window size and ensure process, temperature, and voltage robustness. A prototype ADC in 40-nm CMOS achieves 35.3-dB signal-to-noise/distortion ratio (SNDR) and consumes 0.81 mW while sampling at 700 MS/s.

60-dB SNDR 100-MS/s SAR ADCs With Threshold Reconfigurable Reference Error Calibration

This paper presents a reference error calibration scheme for successive approximation register (SAR) analog-to-digital converters (ADCs) verified with two prototypes. Such a reference error often occurs in high-speed SAR ADCs due to the signal dependent fast switching transient, and leads to a large differential nonlinearity and missing codes, eventually degrading conversion accuracy. The calibration concept aims to differentiate the error outputs and correct them by simply performing a subtraction in the digital domain. It runs in the background with a little hardware overhead, and does not depend on the type of the input signal or reduce the dynamic range. Two prototypes were measured which are made up of different reference generation circuits. Design #1 has the reference voltage from off-chip and a 3-pF decoupling capacitor on-chip, while design #2 includes an on-chip reference buffer. Both designs were fabricated in 65-nm CMOS and achieve at least 9-dB improvement on signal-to-(Noise + Distortion) ratio (SNDR) after calibration. The total core area is around 0.012 mm2 for both chips and the Nyquist SNDR of designs #1 and #2 is 59.03 and 57.93 dB, respectively.

A 10-bit 110 MHz SAR ADC with asynchronous trimming in 65-nm CMOS**Project supported by the Science and Technology on Analog Integrated Circuit Laboratory (No. 9140C090105140C09041).

A 10-bit 110 MHz SAR ADC with asynchronous trimming is presented. In this paper, a high linearity sampling switch is used to produce a constant parasitical barrier capacitance which would not change with the range of input signals. As a result, the linearity of the SAR ADC will increase with high linearity sampled signals. Farther more, a high-speed and low-power dynamic comparator is proposed which would reduce the comparison time and save power consumption at the same time compared to existing technology. Additionally, the proposed comparator provides a better performance with the decreasing of power supply. Moreover, a highspeed successive approximation register is exhibited to speed up the conversion time and will reduce about 50% register delay. Lastly, an asynchronous trimming method is provided to make the capacitive-DAC settle up completely instead of using the redundant cycle which would prolong the whole conversion period. This SAR ADC is implemented in 65-nm CMOS technology the core occupies an active area of only 0.025 mm and consumes 1.8 mW. The SAR ADC achieves SFDR > 68 dB and SNDR > 57 dB, resulting in the FOM of 28 fJ/conversion-step. From the test results, the presented SAR ADC provides a better FOM compared to previous research and is suitable for a kind of ADC IP in the design SOC.

Meta‐stability immunity technique for high speed SAR ADCs

An 8-bit 4 GS/s 8-channel time-interleaved successive approximation register (SAR) analogue-to-digital converter (ADC) is presented. To enhance the ENOB (effective number of bits), a meta-stability immunity technique is proposed, which utilises pre-installation to eliminate uncertain decision. The technique has negligible design overhead in terms of power and silicon area. The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.

Metastablility in SAR ADCs

The fundamental limitation of Nyquist analog-to-digital converter (ADC) architectures toward high speed is metastability. It refers to the inability of a latched comparator to produce a valid decision in a certain available time. This issue is usually severe in high-speed successive approximation register (SAR) ADCs due to their serial conversion scheme, which includes the regeneration and the reset process of the comparator in a feedback loop, thus significantly reducing the available time for the regeneration. Our analysis considers the probability of metastability errors as a function of their magnitude and is customized for a timer-based asynchronous SAR ADC (with loop time-out). The resulting framework can also quantify the metastability in a synchronous architecture, and we provide a numerical comparison. To validate the analysis, measurement results of an 8-bit 130-MS/s SAR ADC in 90-nm CMOS are provided.

A Flexible-Weighted Nonbinary Searching Technique for High-Speed SAR-ADCs

This brief presents a low-computational, flexible nonbinary searching technique for high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). By embedding the redundant weights into each capacitor branch of digital-to-analog converter (DAC) array, the conventional binary DAC array is customized as a nonbinary DAC array without additional control logics, resulting in fast conversion and negligible overhead. The weight of each branch could be defined flexibly with certain constraints, which is derived in this brief. Moreover, the nonbinary output codes are encoded to binary codes by adder-based encoding logics that show far less power and area penalty. To demonstrate the proposed nonbinary searching technique, a 10-bit 280-MS/s high-speed SAR-ADC is presented, which achieved an signal-to-noise-distortion ratio of 52.4 dB and a figure of merit of 21 fJ/conversion step.

Pipelining method for low-power and high-speed SAR ADC design

A low power analog to digital converter (ADC), based on a pipelining method employed in successive approximation register (SAR) architecture is presented. This structure is a two-stage pipeline SAR ADC with asymmetrical time interleaved (TI) channels, aimed to reach sampling rate as high as about threefold of a conventional SAR ADC while benefiting from its low power consumption and small area. Passive residue conversion without inter-stage amplifier and symphonic collaboration of stages are employed to design a low power, high speed, and accurate converter. In the proposed architecture, every signal sample experiences equal comparator offset during its conversion due to the applied novel operation sequence, without adding redundancy or comparator rotation scheme. A 7-bit ADC with sampling rate of 83 MS/s based on the proposed architecture is designed and its performance is verified by post layout simulation results in a 180-nm CMOS Technology. Both system level analysis and simulation verifications support proposed architecture superiority over similar reported SAR architectures.

A capacitive DAC with custom 3-D 1-fF MOM unit capacitors optimized for fast-settling routing in high speed SAR ADCs

Asynchronous successive approximation register (SAR) analog-to-digital converters (ADC) feature high energy efficiency but medium performance. From the point of view of speed, the key bottleneck is the unit capacitor size. In this paper, a small size three-dimensional (3-D) metal—oxide—metal (MOM) capacitor is proposed. The unit capacitor has a capacitance of 1-fF. It shapes as an umbrella, which is designed for fast settling consideration. A comparison among the proposed capacitor with other 3-D MOM capacitors is also given in the paper. To demonstrate the effectiveness of the MOM capacitor, a 6-b capacitive DAC is implemented in TSMC 1P9M 65 nm LP CMOS technology. The DAC consumes a power dissipation of 0.16 mW at the rate of 100 MS/s, excluding a source-follower based output buffer. Static measurement result shows that INL is less than ±1 LSB and DNL is less than ±0.5 LSB. In addition, a 100 MS/s 9-bit SAR ADC with the proposed 3-D capacitor is simulated.

Linearity Analysis on a Series-Split Capacitor Array for High-Speed SAR ADCs

A novel Capacitor array structure for Successive Approximation Register (SAR) ADC is proposed. This circuit efficiently utilizes charge recycling to achieve high-speed of operation and it can be applied to high-speed and low-to-medium-resolution SAR ADC. The parasitic effects and the static linearity performance, namely, the INL and DNL, of the proposed structure are theoretically analyzed and behavioral simulations are performed to demonstrate its effectiveness under those nonidealities. Simulation results show that to achieve the same conversion performance the proposed capacitor array structure can reduce the average power consumed from the reference ladder by 90% when compared to the binary-weighted splitting capacitor array structure.