Highly Accelerated Stress Test Research Articles

Implementation of microcontroller board on a sustainable and degradable PLA/flax composite substrate: a case study

In this paper, we present a novel polylactic-acid/flax-composite substrate and the implementation of a demonstrator: a microcontroller board based on commercial design. The substrate is developed for printed circuit board (PCB) applications. The pre-preg is biodegradable, reinforced, and flame-retarded. The novel material was developed to counter the increasing amount of e-waste and to improve the sustainability of the microelectronics sector. The motivation was to present a working circuit in commercial complexity that can be implemented on a rigid substrate made of natural, bio-based materials with a structure very similar to the widely used Flame Retardant Class 4 (FR4) substrate at an early technological readiness level (2–3). The circuit design is based on the Arduino Nano open-source microcontroller board design so that the demonstration could be programmable and easy to fit into education, IoT applications, and embedded designs. During the work, the design was optimized at the level of layout. The copper-clad pre-preg was then prepared and processed with subtractive printed wiring technology and through hole plating. The traditional surface mounting methodology was applied for assembly. The resulting yield of PCB production was around 50%. Signal analysis was successful with analogue data acquisition (voltage) and low-frequency (4 kHz) tests, indistinguishable from sample FR4 boards. Eventually, the samples were subjected to highly accelerated stress test (HAST). HAST tests revealed limitations compared to traditional FR4 printed circuit materials. After six cycles, the weight loss was around 30% in the case of PLA/Flax, and as three-point bending tests showed, the possible ultimate strength (25 MPa at a flexural state) was reduced by 80%. Finally, the sustainability aspect was assessed, where we found that ∼95 vol% and ∼90 wt% of the traditional substrate can be substituted, significantly easing the load of waste on the environment.

Thermal Performance and Reliability of Liquid Metal Pastes with Solid Metal Particles as Thermal Interface Materials for the Cooling of Computing Electronics

In recent years, we have developed a series of gallium-based liquid metal pastes containing low content solid metal particle additives (LMPMPs) to enhance thermal performance and control bondline thickness (BLT) of prepared liquid metal composites as thermal interface materials (TIMs). This new material is synthesized via in-situ by introducing gallium oxide into liquid metal alloys. In our recent research, we intensively investigated thermal properties of different primary liquid metal alloys containing small amounts of metal additives, and ran extensive reliability tests including power cycling, thermal cycling, and aging tests on the synthesized LMPMPs. In this paper, the thermal properties of the synthesized LMPMPs with different liquid metal alloys are studied with reliability tests that focus on power cycling by monitoring thermal resistance of LMPMPs over time using a custom power cycler. We have found power density, BLT, and different liquid metal alloys have a significant impact on thermal properties and reliability of LMPMPs. We also conducted thermal aging tests on Cu-LMPMPs-Cu sandwich specimens at 85°C in an ambient atmosphere to study the deterioration of thermal conductivity of LMPMPs over time, measured by laser flash analyzer using the layered structure method. Highly accelerated stress test (HAST) with a profile of 110°C, 85RH%, and 264 hours was used to study the decomposition of liquid metal alloys. Thermal cycling test with a profile of -40 to 125°C was employed to investigate the pump-out of LMPMPs. It has been proven that LMPMPs have much better thermal performances than polymer-based thermal grease.

Low Temperature Curable Low Dk & Df Polyimide for Redistribution Layer

In this paper, we report low temperature curable (around 200～250℃), low Dk (2.7) and low Df (0.007) negative tone type photo-definable polyimides. Those materials, which were in states of liquid or B-stage sheet, were able to be patterned by photolithography process. Our novel polyimides showed excellent dielectric and mechanical properties, and good results on reliability tests. Our developed polyimides kept enough insulating performance after a biased HAST (High Accelerated Stress Test). Finally, in collaboration with IME, a test package which mounted our novel polyimide as redistribution layers was fabricated.

Highly Accelerated Stress Testing of Proton Exchange Fuel Cell Membranes for Heavy Duty Transportation Applications

According to the US DOE’s multi-year Fuel Cell research, development, and demonstration plan, a 30,000 h lifetime, approximately four times that of the light-duty vehicles (LDV), is required for Heavy Duty Vehicle (HDV) applications [1]. Thus, highly accelerated stress tests are necessary in order to assess the viability to novel membrane concepts within a reasonable amount of time. Previously we have reported the development of a highly accelerated stress test (HAST) to generate local stressful conditions that are representative of those in automotive fuel cell stacks [2]. Using a 50-cm2 cell cycled between 0.05 and 1.2 A/cm2 with a low inlet RH in the co-flow configuration, the HAST creates a distribution of combined mechanical/chemical stressors in the membrane with the maximum chemical stress occurring near the gas inlets and the maximum mechanical stress near the outlets. Conducting HASTs using a current distribution measurement tool and a shorting/crossover diagnostic method to track the state of health of a state-of-the-art membrane containing both a mechanical support and a cerium-containing chemical stabilizing additive, the result shows that the membrane location with the most severe thinning coincides with that of the deepest membrane hydration cycling. Upon examination of the cerium redistribution patterns after the test, it was found that the severe humidity cycling generated by the HAST condition near the outlet region not only generated the highest membrane mechanical stress but also resulted in the strongest water flux, which may cause local depletion of the cerium added as chemical stabilizer.In this study, we have focused on determining the root cause of membrane failure in the region of hydration cycling. Two hypotheses were investigated. The first is that chemical degradation can be accelerated in the presence of mechanical stress. The chemical degradation leads to membrane thinning which, in turn, leads to fewer sulfonic acid sites in the membrane available for Ce cation exchange. Two synergistic pathways for membrane degradation by combined mechanical and chemical stressors have been summarized by Kusoglu and Weber [3]. Ex-situ hydrogen peroxide vapor cell tests conducted with a pressure bias across the membrane to create a tensile stress were conducted to see if mechanical stress has an impact on membrane chemical degradation rate [4].The second hypothesis is that local depletion of the mobile Ce stabilizer in regions of high humidity gradients can lead to chemical degradation in those regions. We have shown previously that humidity gradients can cause cations to move with convective forces from wetter to drier regions within a perfluoro-sulfonic acid (PFSA) membrane [5]. To study this hypothesis, we conducted two types of tests. First, we repeated the HAST tests of the state-of-the-art membranes and stopped the tests prior to the onset on membrane thinning to see whether Ce depletion occurs before or after the onset of thinning. We also ran HAST tests on membranes which contained no Ce stabilizer to see if membrane failure still occurred in the region of strongest humidity cycles. In the absence of stabilizer, we expect chemical degradation to occur faster towards the cell inlets where, on average, the MEA is driest.We will show that the HAST test significantly accelerates membrane failure by increasing temperature and frequency of local deep humidity cycles without changing the primary failure mode or location of a state-of-the-art membrane. This work suggests that these HAST tests can be used to accelerate the development of membranes for HD fuel cell applications. DOE H2 Heavy Duty Truck Targets; https://www.hydrogen.energy.gov/pdfs/19006_hydrogen_class8_long_haul_truck_targets.pdf Y.-H. Lai et. al, J. Electrochem. Soc., 165 (6) (2018) F3100-F3103Kusoglu and Weber, J. Phys. Chem. Lett., 6, 4547 (2015)Y.-H. Lai et. al, ECS s 2021; https://iopscience.iop.org/article/10.1149/MA2021-02381128mtgabs F.D. Coms et. al, ECS s 2021; https://iopscience.iop.org/article/10.1149/MA2021-02381130mtgabs

Evaluation of the helium hermeticity reliability of copper through-glass vias

This work aims to understand and assess the helium hermeticity reliability of metallized copper (Cu) through-glass vias (TGVs) made in Corning® HPFS® Fused Silica glass substrate. To assess this, the Cu TGV wafers were subjected to numerous stringent environmental reliability tests that includes high temperature storage (HTS) at 125 °C, highly accelerated stress testing (HAST), 130 °C/85 % RH and thermal shock (−40 °C/125 °C). Using a helium leak rate of >1.0 × 10−8 atm·cm3/s as the failure criteria, it was found that all the Cu TGV wafers used in this study significantly outperformed specification requirements, irrespective of the harsh environmental conditions that they were subjected to. This finding clearly attests to the robustness and suitability of Cu TGV wafers used in this study for stringent helium hermeticity requirement applications. At the completion of the tests, no failures were found for all samples subjected to thermal shock and HTS even after 9000 cycles and 4600 h respectively. For HAST samples that failed after exposure times of 400 h and 1500 h, it was found that the root cause for their failure was due to the erosion of Cu at the titanium (Ti)–Cu interface, caused by the formation of CuO and/or Cu2O. This led to sidewall debonding of the Ti–Cu interface, resulting in helium leak rates > 1.0 × 10−8 atm·cm3/s. Additionally, higher HAST exposure time was found to lead to increased degradation of the Ti–Cu interface.

Application of deuterium oxide (D2O) isotope tracing technique for encapsulated QFN failure analysis

Polymer encapsulated components are universally used in consumable applications. However, polymer encapsulants for packages commonly are non-hermetic. The polymer encapsulants can absorb moisture from atmosphere which will post a risk to the package reliability. In this study, a type of polymer encapsulated Quad Flat No-Lead (QFN) package encountered electricity leakage after Highly Accelerated Stress Tests (HAST) 96 h. Although it is suspected that penetration of moisture into the encapsulated package caused electrical leakage failure, there is no direct evidence to prove this assumption. Traditional X-ray and Scanning Acoustic Microscopy (C-SAM) techniques cannot detect any defect of the package due to their detection limit.To solve above issues, this study employed a new deuterium oxide (D2O) isotope tracing method. The encapsulated package underwent highly Accelerated Stress Tests (HAST) with D2O, and D signal of the sample was analysed by Time-of-Flight Secondary Ion Mass Spectrometry (ToF-SIMS). The results showed that D localized at the failure area where leakage occurred. It is direct evidence to show it is a moisture-induced leakage.

Ultrasonic Bonding Interface Degradation Characteristics of Gold-Coated Silver Wire for Semiconductor Packaging

Gold-coated silver wire was developed to alleviate the high cost of Au wire used in semiconductor packaging. Ball-bonding and stitch-bonding techniques were used to fabricate the dummy packaging material, comprising 97.3 % Ag, 97.3% Au-Coated Ag, and 99.99 %Au wires. The wire ball shear test (BST), the wire ball pull test (BPT), and the microstructural attributes of the ultrasonic bonding interfaces were compared with the initial properties, both before and after the highly accelerated stress test (HAST), conducted at 130 ℃ and 85% relative humidity (RH). The initial bonding strength for all the wire variants was ?23~24 gf. Following the HAST, the bonding strength of the Ag wire, the Au-coated Ag wire, and the Au wire decreased by approximately 75 %, 47 %, and 17 %, respectively. The microstructure analysis revealed that cracks developed and propagated at the ends of the interface and that the Au-rich Au-Al intermetallic compound (IMC) inhibited the propagation of the crack at the ACA/Au wire interface. Additionally, it was discovered that the presence of the Ag-Au-Al IMC at the interface of the ACA wire reduced Kirkendall voids, which act as a barrier to Au-Al interdiffusion.

Electrical Characteristics and Reliability of Wafer-on-Wafer (WOW) Bumpless Through-Silicon Via

Electrical characteristics and reliability of the wafer-on-wafer (WOW) bumpless through-silicon via (TSV) structure are investigated, and the new lumped circuit model is proposed to simulate the performance of the structure. Including the actual contact resistance in the model, the integrity of the high-frequency signal can be accurately simulated. For the 12-layer stacked bumpless TSV structure with plasma cleaning at the via bottom, the transmission loss of the signal up to 20 GHz can be lower than 2 dB. High eye height and low jitter at 3.2 Gbps show excellent signal integrity for high bandwidth memory (HBM) applications. In addition, a complete reliability study, including thermal cycling test (TCT), highly accelerated stress test (HAST), and electromigration test, reveals excellent electrical and mechanical properties, indicating that the structure is robust with great potential for 3-D integration.

A 300°C High Reliability HALT/HAST Screening/Sorting Procedure for Ceramic Capacitors – Part 2

Abstract This is Part 2 of a study initially presented at HiTEC 2018, for context, some introductory material is duplicated. A highly accelerated life test (HALT) and highly accelerated stress test (HAST) procedure for ceramic capacitors developed by the author in the mid 1980’s to early 1990’s, and published in 1994, consists of a 400 Volt biased six (6) hour stress sort at 150°C (423K), a methanol current leakage test that located mechanical and structural cracks, a visual inspection at ten times (10X) magnification, and a capacitance and dissipation measurement before and after the test. In over thirty (30) years of use, there has never been a user reported in-circuit failure in industrial, military, and aerospace application at temperatures as high as 500°C (773K). However, reviewing user feedback, two concerns with the original sorting procedure are the stress is performed at 150°C (423K), and the lack of a more detailed ceramic capacitor electrical model. To address the first, the low aging temperature, the stress temperature was increased from 150°C to 300°C, in order to age ceramic solid state crystal mineral phases that may change with temperature. The test results for X7R and NP0/COG multilayer ceramic capacitors (MLCC) at 300°C, are compared to the test results using the original HALT/HAST procedure at 150°C. Differences between X7R/NP0/COG and porcelain capacitors are discussed when applicable. Further, a more detailed ceramic capacitor electrical model that represents the physical and electrical characteristics of the ceramic capacitors is presented, including the electrical current leakage effects with temperature, and the carbonized residue effects from the manufacturing process.

반도체용 미세 회로 기판의 절연 파괴 고장 분석

Purpose: The failure mechanism of electrical breakdown of organic substrate was identified. The median lives of various samples under biased Highly accelerated stress test (HAST) were determined from log-normal distributions.<BR>Methods: Failure analyses of electrical breakdown were conducted. Electrical test, optical microscopy, focus ion beam, electron microscopy, energy dispersive X-ray spectroscopy, and Fouriertransformed infrared were performed on electrical breakdown failure.<BR>Results: The median lives of the customer’s failed samples, the archived samples, and re-designed samples were measured to be 29.0 h, 59.5 h, and 270.8 h, respectively. The result promoted copper ion migration due to excessive water absorption of photosensitive solder resist, and the excessive water absorption results from the un-cured photosensitive solder resist.<BR>Conclusion: The electrical breakdown causes were uncured SR and consequent excess water absorption.

SMT assembly effects on organic substrate lifetime reduction

PurposeThe purpose of this study is that the effects of surface mount technology (SMT) assembly process on the product lifetime of fine-pitch printed circuit boards (PCBs) were investigated under biased highly accelerated stress testing (HAST).Design/methodology/approachSMT assembly from a semiconductor SMT assembly process was replicated to test PCBs under the same conditions as SMT-assembled PCBs. The median lives µ and standard deviation s of the test PCBs were calculated from the log-normal distribution. The failure analysis of current leakages was conducted by the focused ion beam, scanning electron microscopy and energy-dispersive X-ray spectroscopy. Using the inverse power law and modified Peck-H’s relationship, the PCB lives at accelerated (by SMT assembly stress) and user conditions were calculated.FindingsThe failure analysis demonstrated that SiO2 and BaSO4 fillers added for stiffening organic materials promote current leakage failure. Therefore, the hydrophobicity of these fillers is believed to be necessary to suppress the current leakage failure under biased HAST. The inverse power law model indicates that the acceleration life model with SMT assembly stress can be given as follows: L(V) = 271.9(S)−0.5031. From modified Peck-H’s relationship, after the third SMT assembly, the time required to attain 0.96 per cent failures at 35°C/60 per cent RH/1.9 V and 130°C/85 per cent RH/3.5 V are 129 y and 69.5 h, respectively. The biased HAST at 130°C/85 per cent/3.5 V after the third SMT assembly for 69.5 h on 238 samples could be recommended as an early quality-monitoring procedure.Research limitations/implicationsIn the future, the failure modes in an early stage of a bathtub should be analyzed and the life prediction model should be studied accordingly.Originality/valueThrough this study, the lifetime prediction model and early quality-monitoring procedure for organic substrates because of SMT assembly stress were obtained.

Evaluation of Metal/Polymer Adhesion and Highly Reliable Four-Point Bending Test Using Stealth Dicing Method in 3-D Integration

The adhesion between metal and polymer layer was studied using four-point bending tests. It was shown that as the annealing temperature increased, oxidation binding increased, which decreased adhesion and reduced the $G_{c}$ value. A new four-point bending test sample prepared using the stealth dicing method with a 100% success rate was proposed for the first time. With samples prepared with stealth dicing, the region where crack extension occurred was smaller after the stress test. Less crack extension generated less loading on the samples. Owing to the coefficient of thermal expansion (CTE) mismatch after increasing the temperature in a highly accelerated stress test (HAST), a void formed in stealth dicing was made close to the interface between the silicon layer and the polymer layer after the stress test, and less crack extension occurred compared with samples kept at room temperature. The smaller loading force guarantees much more stable measurement with a higher success rate after the stress tests. The stealth dicing method can be applied to other structures, such as redistribution layers (RDLs).

High bond reliability of newly developed silver alloy bonding wire

Abstract In this paper, a new type of silver (Ag) alloy bonding wire is introduced, and its bonding property and long term reliability are demonstrated. The new Ag wire, called GX2s, is developed as a cost-effective alternative to gold (Au) wire targeting at automotive electronics. The wire material is doped with added element, and its electrical resistivity is much lower than the conventional palladium (Pd) doped Ag wire. Highly accelerated stress test (HAST) and high temperature storage life (HTSL) test were carried out along with other bonding evaluations. The results show that GX2s has good bonding property and excellent long term bond reliability. Microstructural analyses of bond interface after the reliability tests were also conducted to investigate its improving mechanism. GX2s is a suitable alternative to Au wire for many applications including high temperature automotive devices.

Study Photo Imagable dielectric (PID) and non-PID on process, fabrication and reliability by using panel glass substrate for next generation interconnection

Abstract In 1965, Gordon E. Moore, the co-founder of Intel stated that numbers of transistors on a chip will double every 18 months and his theory called the Moore's Law. The law had been the guiding principle of chip design over 50 years. The technology dimension is scaling very aggressively in IC foundry. For example, TSMC announced their 5nm Fin Field-Effect Transistor (FinFET) process technology is optimized for both mobile and high performance computing applications. It is scheduled to start risk production in the second half of 2019.[1] To overview the semiconductor supply chain included IC foundry, wafer bumping, IC carrier, PCB (Printed circuit board) and OSAT (oversea assembly and testing)… etc., the IC carrier and PCB technology dimension scaling are far behind than the IC foundry since many reasons for the traditional industry. The industry needs different kinds of breakthrough approaches for the scaling of via and strip line in next generation interconnection. Traditional organic substrates faces many challenges of warpage, surface roughness and material dimension stability issues for manufacturing and high density I/Os with very fine line interconnections. To breakthrough these challenges, the materials of glass carrier, new photo-imagable dielectric (PID) and advanced equipment were evaluated for the fine line and fine via interconnection. In the papers, there are many PID and non-PID materials were surveyed and compared for fine via (&amp;lt; 10μm) interconnection or low loss of high frequency application. The first candidate was chosen for redistribution layers (RDL) fabrication by using 370mm × 470mm glass panels. Semi additive process (SAP) was used for direct metallization on glass panel with different build-up dielectric materials to form daisy chain test vehicles. The process, fabrication integration and electrical measurement results of daisy chain showed good continuity and electric resistance in the glass panel substrate. The reliability of the thermal cycling test (TCT) and highly accelerated stress test (HAST) were evaluated as well in this study.

Heterogeneous System Level Integration Using Active Si Interposer

Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA die. Chip on Chip on Substrate packaging methodology was demonstrated for handling active Si interposer die as thin as 40 $\mu \text{m}$ . Different packaging approaches were evaluated and the results are benchmarked. In addition, active Si interposer concept is introduced to provide Analog to Digital Converter (ADC), Digital to Analog Converter (DAC) and Power Management Unit (PMU) functions to support high-performance logic. Furthermore, benefits of active Si approach such as system scaling and cost-effectiveness have been demonstrated. “Via Last” TSV approach is used for the fabrication of 130 nm tech node active Si interposer. It was confirmed that appropriate selection of temporary bonding material plays a critical role in device wafer warpages in via last TSV process flow. Functionality checks were carried out on all samples subjected to pre- and post-reliability assessments, which include thermal cycling (TC), moisture sensitivity tests (MSL) and highly accelerated stress tests (HAST). All samples were found to be functional with no deterioration in performance despite being subjected to reliability tests and high-voltage stress tests.

Copper Ball Voids: Failure Mechanisms and Methods of Controlling at High Temperature Automotive Application

Since 2008, fine gauge (≤ 35 μm diameter) copper (Cu) wire has been rapidly replacing fine gauge gold (Au) wire in consumer, commercial, and industrial products [2–4]. The first wave of Cu wire products used bare, uncoated Cu wire which is soon to known having Cu-Al IMC corrosion induced by mobile chlorine ions in the epoxy mold compound system when IC parts are subjected to moisture related package stress tests such as biased HAST (Highly Accelerated Stress Test) [1–7]. Additionally, when comparing to Au wires, the 2nd bond process window of bare Cu wire can be very narrow and becomes a concern of moving into HVM (high volume manufacturing) [8]. Thus, palladium-coated Cu (PdCu) wire was introduced to the semiconductor assembly market aiming to provide more margin of passing biased HAST and enhance 2nd bond process capability [9–13]. However, the use of Pd-Cu wire is not a panacea to all Cu wire bond problems. One unique anomaly for Pd-Cu wire is the Cu ball void [1] which is observed only with Pd-Cu and not bare Cu ball bonds during HTSL (high temperature storage life) tests. The mechanism of forming Cu ball voids was proven to be the galvanized corrosion mechanism with Pd-Cu coupling. Significant factors affecting the formation rate of Cu ball voids are found to be baking temperature, EFO current settings, bonding parameters and mold compound additives (sulfur). Both anodic and cathodic chemical reactions will be proposed for Cu voids in this paper. Even though Cu void can be considered as a cosmetic defect for the majority of application since the peak temperature of device mission profile is always no larger than 175C. The application at extreme high temperature (for example, 190C) can actually cause electrical failure at the ball bon region due to the Cu void formation in terms of size and location at the Cu-Al IMC region. The main effect is due to the selected mold compound having high amount of metallic adhesion promoter which is sulfur-based and extensive high temperature storage test condition (190C). The FIB/SEM picture of failing ball bond due to Cu voids from this particular device will be presented in the paper. Thus, a newly developed doped Cu wire without Pd coating has been proposed by many wire suppliers to overcome Cu ball voids. However, doped Cu wires without Pd coating have suffered the same high volume manufacturing issues observed by bare Cu wires. For example, short tail and mean time between assist (MTBA) for doped Cu wires without Pd coating are both as poor as bare Cu wires. We will present high temperature storage test results obtained by doped PdCu wires in this paper. To balance high volume manufacturing issues and Cu void formation, doped PdCu wires are also proposed recently. Several doped PdCu wires whose extensive high temperature storage results (220C) will be presented in this paper. The worst case mold compound with high amount of sulfur based adhesion promoter has been used to test the effectiveness of these new wire types. At such harsh testing condition, there is one doped PdCu wire in our test can actually survive without electrical failed ball bond due to Cu voids. Factors of effectiveness of doped PdCu wires will be discussed in this paper. Authors have chosen to focus on Cu voids at both 1st bond (ball bond) and 2nd bond (wedge). 20 um wire diameter has been used for all test vehicle in this study. All controlling factors of eliminating Cu voids will surely be included at the end of this paper.

Result of high accelerated stress test of organic substrates made by integrated dry process

Abstract The uses of the semiconductor increase by the development of Internet of Things. Miniaturization of the semiconductor wiring to bring speedup, electric power saving advances, and various technologies are developed. The new technology that applied a semiconductor production technology is waited eagerly for the production of the printed circuit board and semiconductor packaging. We presented new dry process “Integrated dry process” using Photodesmear technology and sputter seed process in IMAPS2016 Pasadena. After the micro via formation with the laser, the smear is effective to remove a smear remaining behind in the via bottom by Photodesmear. Furthermore, we improved adhesion between copper metal and epoxy resin in a sputtering seed together. We made the large experimental tool that Photodesmear could process an actually size of the print circuit board by static irradiation. And we proved that handling of panel size was technically possible. The connection reliability of the contact via is evaluated after electric copper plating by quick via peel examination. A cross section of the vias was made and, the residual smear removal properties of wet desmear processing and the Photodesmear processing were compared with the residual smear and the thin oxidation layer by observation of the connection interface. The interfacial surface state after the desmear processing was analyzed in X-ray probe analyzer. We produced the test vehicle using Photodesmear technology and a sputtering seed technology. I compared it with the same pattern sample produced by a process conventionally. In this paper, we report the result of the high accelerated temperature and humidity stress test.

A comparison of the Cu electrochemical migration behavior between Cu lines with 5 um L/S realized by conventional Semi Additive Process (SAP) and an innovative Excimer Laser Damascene Process

Abstract The technological evolution regarding multi-chip integrated Fan-Out packages and chip scale packages (CSPs) with high amounts of I/O demands for even higher routing densities. Conventional used technologies and materials like mask aligner and photosensitive polymers used for semi additive process (SAP) in the BEOL have reached its limits to push the resolution down to two um. New materials and technologies are necessary to overcome these limits. As the routing density increases, so does the reliability requirements. The electrochemical migration between Cu lines cannot be neglected and need to be analyzed as the distance between the Cu lines is decreasing. A new approach for fine-line multi redistribution layers (RDL) realized by an excimer laser dual damascene process was presented in the past, using laser ablation and Cu chemical mechanical planarization (CMP) to realize embedded Cu lines. This approach has several advantages regarding the processing but one of the most important characteristics of the damascene approach is the improved electrochemical migration behavior. The Cu lines are partially cladded by the Ti part of the seed layer due to the way of processing. The Ti acts as a barrier layer and inhibits the Cu migration into the surrounding polymer. RDL structures realized by conventional SAP have Ti only under and not between the Cu lines. In this study different test samples with interdigital structures (resp. interdigital capacitor IDC) with five um line and space width (L/S) were realized to analyze the electrochemical migration behavior between the fingers of the IDC. The samples were realized by SAP and by the excimer laser damascene process and were subsequently tested by the temperature humidity bias (THB) test resp. biased High Accelerated Stress Test (bHAST). With the help of this work, we were able to compare the reliability of both process variants and to demonstrate and prove the reliability of embedded copper lines realized by the excimer laser damascene process.

Reliability Testing and Stress Measurement of QFN Packages Encapsulated by an Open-Ended Microwave Curing System

In this paper, the influence of microwave curing on the reliability of a representative electronic package is examined by reliability testing and measurement of residual stresses. A LM358 voltage regulator die was mounted to an open quad flat no-leads (QFN) package for reliability testing. For the stress measurement, a specifically designed stress measurement die was mounted to the QFN package. The chips were encapsulated with Hysol EO1080 thermosetting polymer material. Curing was performed using an open-ended microwave oven system equipped with in situ temperature control. Three different temperature profiles for microwave curing were selected according to the requested degree of cure and chemical composition of the cured material. A convection cure profile was selected for the control group samples. Temperature cycle tests and highly accelerated stress tests (HAST) were performed on a total number of 80 chips. Ninety-five QFN packages with stress measurement chips were also manufactured. The increased lifetime expectancy of the microwave-cured packaged chips was experimentally demonstrated and measured between the 62% and 149% increased lifetime expectancies after temperature cycle test (TCT), and between 63% and 331% after a HAST and TCT compared to conventionally cured packages. The analysis of specifically designed stress test chips showed significantly lower residual stresses ranging from 26 to 58.3 MPa within the microwave-cured packages compared to conventionally cured packaged chips, which displayed residual stresses ranging from 54 to 80.5 MPa. Therefore, this paper provides additional confidence in the industrial relevance of the microwave curing system and its advantages compared to the traditional convection oven systems.

(Invited) Durability of Polymer Electrolyte Membranes for Automotive Applications

There are three critical membrane degradation mechanisms that can lead to failure of polymer electrolyte fuel cell systems: chemical, mechanical and thermal degradation. Chemical and mechanical degradation can occur during normal fuel cell operation whereas thermal degradation should only occur at extreme temperatures such as those that can be induced by membrane shorting. This talk will focus on the individual failure modes; with attention dedicated to describing the fundamental model-based mechanistic understandings, appropriate accelerated stress tests that enable rapid screening and relevant in-situ diagnostics to track membrane health during fuel cell operation, as well as discussions of effective mitigation strategies to prevent or minimize the risk of failure caused by the specific modes of membrane degradation with focus on the effect of simultaneous chemical and mechanical degradation. Both chemical and mechanical degradation of perfluorosulfonic acid (PFSA) membranes have been extensively studied, and effective mitigation strategies have been developed that can significantly extend PFSA proton exchange membrane (PEM) lifetimes. For example, porous polymer supports such as (expanded polytetrafluoroethlene) ePTFE can be used to make PFSA membrane which exceed US Department of Energy mechanical durability requirements and hydroxyl radical scavenging additives such as Ce3+ and Mn2+ can enable PFSA membranes to meet chemical stability requirements. Accelerated stress tests (ASTs) have been developed that can be used to screen various membrane types and mitigation strategies, and effective in-situ diagnostics have been developed to track degradation of PFSA membranes during fuel cell operation. The failures observed in these accelerated tests as seen by postmortem analysis mimic the failures of PFSA membranes in field tests. A new highly accelerated stress test (HAST) has been developed to generate local stressful conditions that are representative of those in automotive fuel cell stacks. The HAST creates a distribution of combined mechanical/chemical stressors in the membrane with the maximum chemical stress occurring near the gas inlets and the maximum mechanical stress near the gas outlets. HASTs were conducted using a current distribution measurement tool and a shorting/crossover diagnostic method to track the state of health of a state-of-the-art robust membrane containing both an ePTFE mechanical support and a Ce-based chemical stabilizing additive. Result shows that the membrane location with the most severe thinning coincides with that of the deepest membrane hydration cycling. Upon examination of the cerium redistribution patterns after the test, it was found that the severe humidity cycling generated by the HAST condition near the outlet region not only generated the highest membrane mechanical stress but also resulted in the strongest water flux, which may cause local depletion of the cerium added as chemical stabilizer. Further results will be presented that decouple the cerium migration effect from the mechanical/chemical synergistic degradation effect.