Abstract
Achieved system level heterogeneous integration involving 130 nm tech node active Si interposer, two 65 nm tech node I/O chips and one 28 nm tech node FPGA die. Chip on Chip on Substrate packaging methodology was demonstrated for handling active Si interposer die as thin as 40 $\mu \text{m}$ . Different packaging approaches were evaluated and the results are benchmarked. In addition, active Si interposer concept is introduced to provide Analog to Digital Converter (ADC), Digital to Analog Converter (DAC) and Power Management Unit (PMU) functions to support high-performance logic. Furthermore, benefits of active Si approach such as system scaling and cost-effectiveness have been demonstrated. “Via Last” TSV approach is used for the fabrication of 130 nm tech node active Si interposer. It was confirmed that appropriate selection of temporary bonding material plays a critical role in device wafer warpages in via last TSV process flow. Functionality checks were carried out on all samples subjected to pre- and post-reliability assessments, which include thermal cycling (TC), moisture sensitivity tests (MSL) and highly accelerated stress tests (HAST). All samples were found to be functional with no deterioration in performance despite being subjected to reliability tests and high-voltage stress tests.
Highlights
Packaging industry is undergoing tremendous transformation, where the focus has shifted to overall system performance, system scaling and cost reduction rather than on individual components alone
The active Si interposer (ATSI) is fabricated in 130nm CMOS, which provides/supports Analog to Digital Converter (ADC), Digital to Analog Converter (DAC), Power Management Unit (PMU), I/O, analog and ESD functions with Via-last TSV
It has been reported that the cost savings from the via-last fabrication from wafer backside, when compared to via–middle approach is about 10% [8] and the same process flow is used for the fabrication of ATSI in this work
Summary
Packaging industry is undergoing tremendous transformation, where the focus has shifted to overall system performance, system scaling and cost reduction rather than on individual components alone. Active Si interposer (ATSI) concept is introduced, which enhances signal integrity, power integrity, lower power consumption and cost-effectiveness. The ATSI is fabricated in 130nm CMOS, which provides/supports ADC, DAC, PMU, I/O, analog and ESD functions with Via-last TSV This approach results in the top-die size reduction, which is usually the expensive advanced node CMOS die [6]. In via –last TSV process integration flow, TSV is fabricated after all BEOL layers. It has been reported that the cost savings from the via-last fabrication from wafer backside, when compared to via–middle approach is about 10% [8] and the same process flow is used for the fabrication of ATSI in this work. All the heterogeneously integrated ATSI packages passed the reliability tests and high voltage stress tests
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