High Field-effect Mobility Research Articles

Design and Performance Analysis of Low Sub-threshold Swing p-Channel Cylindrical Thin-film Transistors

Background: Tin monoxide (SnO) attracts considerable interest for p-channel Cylindrical Thin Film Transistors (CTFTs) applications due to their merits, including low hole effective mass, Sn s and O p orbital hybridization at the valance band maxima, and ambipolar nature, among other p-type oxide semiconductors. Objective: This article analyses the influence of channel radius and the impact of dielectric materials on the performance of SnO-based CTFT devices through 3D numerical simulations. Methods: The radius of the active layer in the CTFT was varied in the range from 10 nm to 30 nm, and it has been observed that an increase in channel radius reduces the switching behavior of the devices. Results: The 10 nm thick CTFT exhibited superior results with a lower threshold voltage of 1.5 V and higher field-effect mobility of 13.12 cm2/V-s over other simulated CTFTs. Conclusion: The obtained mobility values are superior to the existing planar TFTs reports. To improve the device performance further, the CTFTs with various dielectric materials have been simulated and optimized with high field-effect mobility and low sub-threshold swing values.

Temperature dependence of carrier mobility in hydrogenated germanane field-effect transistor with various electrode materials

Germanane, a layered material in which single-layer germanium is terminated by hydrogen atoms, was utilized as a channel material in back-gate-type FETs. Titanium, aluminum, and nickel were used as source and drain electrodes of FETs, and most of the fabricated FETs showed ambipolar characteristics. Among the three electrode materials, nickel was the best for high field-effect carrier mobility. It was also found that the mobility changes with temperature T according to the T −3/2 law below 273 K, whereas the mobility change deviates from the law of T −3/2 above 293 K.

High-mobility and low subthreshold swing amorphous InGaZnO thin-film transistors by in situ H2 plasma and neutral oxygen beam irradiation treatment

In this work, staggered bottom-gate structure amorphous In–Ga–Zn–O (a-IGZO) thin film transistors (TFTs) with high-k ZrO2 gate dielectric were fabricated using low-cost atmospheric pressure-plasma enhanced chemical vapor deposition (AP-PECVD) with in situ hydrogenation to modulate the carrier concentration and improve interface quality. Subsequently, a neutral oxygen beam irradiation (NOBI) technique is applied, demonstrating that a suitable NOBI treatment could successfully enhance electrical characteristics by reducing native defect states and minimize the trap density in the back channel. A reverse retrograde channel (RRGC) with ultra-high/low carrier concentration is also formed to prevent undesired off-state leakage current and achieve a very low subthreshold swing. The resulting a-IGZO TFTs exhibit excellent electrical characteristics, including a low subthreshold swing of 72 mV dec−1 and high field-effect mobility of 35 cm2 V−1 s−1, due to conduction path passivation and stronger carrier confinement in the RRGC. The UV–vis spectroscopy shows optical transmittance above 90% in the visible range of the electromagnetic spectrum. The study confirms the H2 plasma with NOBI-treated a-IGZO/ZrO2 TFT is a promising candidate for transparent electronic device applications.

Cu2O p-type Thin-Film Transistors with Enhanced Switching Characteristics for CMOS Logic Circuit by Controlling Deposition Condition and Annealing in the N2 Atmosphere

Cuprous oxide (Cu2O) p-type thin-film transistors (TFTs) can be practically applied for complementary metal oxide semiconductor (CMOS) logic circuits, but the electrical performances are still insufficient due to high off-current and low field-effect mobility. Here, we have demonstrated Cu2O TFTs with improved field-effect mobility and low off-current through reduction of cupric oxide (CuO) impurities and dissociative Cu defects with the combination of deposition and annealing conditions. Copper oxide was deposited by radio frequency sputtering in mixed gases of argon and oxygen. After that, the deposited copper oxide was annealed at 800 °C in the tube furnace under a N2 atmosphere instead of a high vacuum condition. The fabricated Cu2O thin film had a high crystalline quality, the ratio of dissociative Cu defects decreased from 11.3 to 3.1%, and the electrical performances of the TFT including the fabricated Cu2O thin film exhibited the field-effect mobility of 1.11 ± 0.05 cm2/V·s, the on/off current ratio of 4.68 ± 0.8 × 104, and the subthreshold swing value of 3.91 ± 0.21 V dec–1. The fabricated Cu2O TFT showed a Vth shift of 3.31 V in the transfer curve under negative bias stress. Nitrogen plays a role in promoting Cu2O phase formation while it prevents CuO phase formation during the annealing process. In addition, oxygen added during sputtering increases the ratio of CuO in the copper oxide thin film and works effectively to reduce dissociative Cu defects in the annealing process. To determine the feasibility of the CMOS logic circuit, we also demonstrated the inverter with n-type indium–gallium–zinc oxide (IGZO) TFT and p-type Cu2O TFT, which showed a voltage gain of 14 at VDD = 20 V.

High Field-Effect Mobility and On/Off Current Ratio of p-Type ALD SnO Thin-Film Transistor

High-performance p-type thin-film transistors (TFTs) with high field-effect mobility and high on/off current ratios (Ion/Ioff) were fabricated by engineering the microstructure and surface morphology of the atomic layer-deposited (ALD) SnO channel layer. ALD SnO films grown at a deposition temperature of 225 °C showed excellent crystallinity and dense, smooth surfaces, which resulted in superior field-effect mobility of 6.13–7.24 cm2/V·s without using a high-temperature postannealing process. Optimization of the SnO channel thickness suppressed the off-state leakage current, which consequently yielded excellent TFT switching performance, with an Ion/Ioff value of 104–105. Additionally, backchannel passivation by the ALD Al2O3 film improved the subthreshold swing characteristics by reducing surface defect states. These results suggest that synergistic control of the microstructure, surface morphology, and thickness of ALD SnO channels is crucial for achieving high-performance p-type SnO TFTs.

Unlocking performance potential of two-dimensional SnS2 transistors with solution-processed high-k Y:HfO2 film and semimetal bismuth contact

Two-dimensional (2D) tin disulfide (SnS2) is emerging as a viable channel material for high-performance field-effect transistors (FET) with high intrinsic mobility. To implement a high-performance two-dimensional SnS2 FET, high field-effect mobility (μFE), steep subthreshold swing (SS), high on-current value (Ion), and high on/off ratio (Ion/Ioff) must be realized. To improve these parameters, we first fabricated a high-k (∼30.5) yttrium-doped hafnium dioxide (Y:HfO2) film through a solution process to suppress Coulomb electron scattering, and to enhance the semiconductor-dielectric interface with an efficient metal–oxygen framework and a very smooth (root mean square = 0.29 nm) surface. Second, we induced Fermi level depinning by introducing a semimetal bismuth (Bi) contact with a low density of states (DOS) at the Fermi level to suppress the metal-induced gap state (MIGS). Through these two strategies, the SnS2 FET obtained high μFE (60.5 cm2V-1s−1), the SS theoretical limit of 60 mV/dec, negligible Schottky barrier height, high normalized on-current (IonL/W) of 90.6 μA, and high Ion/Ioff of 3 × 107, demonstrating that SnS2 can be re-evaluated as a potentially effective 2D channel material.

Improved Electron Transport Properties of Zn-Rich In–Ga–Zn–O Thin-Film Transistors

Amorphous transparent oxide semiconductor InGaZnO4 (IGZO)-based thin-film transistors (TFTs) have been practically used as the backplane of flat panel displays. For future higher-definition displays, alternative active materials with a higher field effect mobility (μFE) are necessary. Although there are a few reports on InGaO3(ZnO)m with Zn-rich composition (IGZOm)-based TFTs, their electron transport properties have not been clarified. Here, we show that a Zn-rich composition enhances the electron transport properties of IGZOm-TFTs. The best TFT performance was obtained for m = 7 (μFE ∼12 cm2 V–1 s–1, subthreshold swing ∼0.1 V decade–1, and a negligibly small bias stress shift). The carrier effective mass (m*) of IGZOm films was found to be 0.16 m0, independent of the m-value. We found that μFE of IGZOm-TFT increased with the m-value for m ≤ 7, whereas it decreased for m > 7 due to the crystallization. The thermopower modulation analyses revealed that the effective channel thickness increased with m (m ≤ 7), which resulted in a longer carrier relaxation time. The present results provide an improving strategy toward new material design for next-generation TFTs with higher μFE values.

Ion Migration Induced Unusual Charge Transport in Tin Halide Perovskites

Metal halide perovskites are considered next-generation semiconductors for various optoelectronic devices owing to their low-cost processability and superior optoelectronic properties. However, the performance and reliability of perovskite-based devices depend on electric-field-driven ion migration, whose mechanism remains unclear. Tin (Sn2+)-based perovskites are attracting particular interest owing to their unique charge-transport properties and eco-friendly characteristics. Here, we explore the effect of ion migration on the charge-transport properties of the Sn2+ perovskite using the transistor as the test platform. To supply mobile ions, we added copper iodide to the Sn2+ perovskite film. The ion migration and accumulation-induced electrochemical doping of the perovskite channel resulted in abnormal transitions in the electrical characteristics with the abnormally high transient field-effect mobility. We expect this study provides a hint for the decipherment of ion migration effect on the charge-transport properties of Sn2+ perovskites and the design of novel perovskite-based electronics.

Effect of passivation layer on back channel etching InGaZnO thin film transistors

Amorphous indium gallium zinc oxide (IGZO) thin film transistors (TFT) are widely used in active-matrix displays because of their excellent stability, low off-current, high field-effect mobility, and good process compatibility. Among IGZO TFT device structures, back channel etching (BCE) is favorable due to low production cost, short channel length and small SD-to-gate capacitance. In this work, prepared are the BCE IGZO TFTs each with the passivation layer of silicon dioxide (SiO<sub>2</sub>), polyimide (PI) or SiO<sub>2</sub>-PI stacked structure to study their difference in back channel hydrogen impurity and diffusion behavior. Comparing with the conventional SiO<sub>2</sub> passivation BCE TFT, the performance of PI passivation TFT is improved greatly, specifically, the saturation field effect mobility increases from 4.7 to 22.4 cm<sup>2</sup>/(V·s), subthreshold swing decreases from 1.6 to 0.28 V/decade, and the an on-off current ratio rises dramatically from 1.1×10<sup>7</sup> to 1.5×10<sup>10</sup>. After the SiO<sub>2</sub> passivation layer is substituted with PI, the I<sub> off</sub> decreases from 10<sup>–11</sup> A to 10<sup>–14</sup> A, which indicates that there exist less shallow-level donor states of hydrogen impurities, which might be explained by the following three mechanisms: first, in the film formation process of PI, the direct incorporation of hydrogen-related radicals from SiH<sub>4</sub> precursor into the back channel is avoided; second, the hydrogen content in the PI film is lower and harder to diffuse into the back channel; third, the hydrogen impurity of back channel that is introduced by the H<sub>2</sub>O<sub>2</sub>-based etchant in the SD etching process could diffuse more easily toward the PI layer. The TFTs with PI passivation layer also shows the less electrical degradation after the annealing treatment at 380 ℃ and better output performance, which confirms less defects and higher quality of the back channel. The bias stabilities of PI devices are improved comprehensively, especially negative bias illumination stability with the threshold voltage shifting from –4.8 V to –0.7 V, which might be attributed to the disappearance of hydrogen interstitial sites and hydrogen vacancies that are charged positively in the back channel. The PI passivation layer is effective to avoid back channel hydrogen impurities of BCE TFT and promises to have broad applications in the display industry.

Synthesis and Characterization of a Non-Conjugated Backbone Polymer Bearing [1]Benzothieno[3,2-<i>b</i>][1]benzothiophene with a Herringbone Packing Motif

Conjugated polymers encompassing delocalized π-electrons in their backbones exhibit high photoabsorption and efficient charge carrier transport through the intermolecular π-π stacking suitable for organic photovoltaics (OPV). By contrast, small molecules such as [1]benzothieno[3,2-b][1]benzothiophene (BTBT) derivatives, which demonstrates high field-effect transistor hole mobilities owing to their 2-dimensional herringbone packing, have not yet been applied to OPVs. Here we report a non-conjugated backbone polymer bearing phenyl- and decyl-substituted BTBT (Ph-BTBT-10) as the pendant conjugated unit, which was synthesized by ring opening polymerization of epoxy append. The polymer showed an X-ray diffraction pattern ascribed to the layered lamellar and less ordered herringbone packing. In addition, a model molecule of Ph-BTBT-10 showed charge separation upon photoexcitation when blended with a non-fullerene acceptor (ITIC) or fullerene (PCBM).

Facile control of p-type SnO TFT performance with restraining redox reaction by ITO interlayers

By comparing Ni and ITO electrodes of SnO TFT, we find a facile method to control p-type SnO TFT performance. A Ni-electrode TFT has a high field-effect mobility of 3.3 cm2/Vs and a low on/off current ratio of 3.6 × 101. Compared to Ni, ITO-electrode TFT has low field-effect mobility of 1.4 cm2/Vs and a high on/off current ratio of 1.1 × 103. Using various analysis methods, we suggested why the electrical properties of SnO TFT differed depending on the electrode materials. First, a redox reaction occurs at the interface of SnO and Ni during the post-annealing process. Second, Ni has an ohmic-like contact formation with SnO, which lowers the Schottky barrier height of carriers. ITO ILs are adopted to Ni electrode to reduce the off-current by hindering the redox reaction. The off-current of TFTs is effectively reduced with ITO ILs as thickness increases. An ITO IL that is 10-nm thick yields the optimum electrical properties: field-effect mobility of 2.5 cm2/Vs, Ion/Ioff of 1.7 × 103 and Vth shift under NBS of −1.4 V.

Passivating Graphene and Suppressing Interfacial Phonon Scattering with Mechanically Transferred Large-Area Ga2O3.

We demonstrate a large-area passivation layer for graphene by mechanical transfer of ultrathin amorphous Ga2O3 synthesized on liquid Ga metal. A comparison of temperature-dependent electrical measurements of millimeter-scale passivated and bare graphene on SiO2/Si indicates that the passivated graphene maintains its high field effect mobility desirable for applications. Surprisingly, the temperature-dependent resistivity is reduced in passivated graphene over a range of temperatures below 220 K, due to the interplay of screening of the surface optical phonon modes of the SiO2 by high-dielectric-constant Ga2O3 and the relatively high characteristic phonon frequencies of Ga2O3. Raman spectroscopy and electrical measurements indicate that Ga2O3 passivation also protects graphene from further processing such as plasma-enhanced atomic layer deposition of Al2O3.

Bi2O2Se nanowires presenting high mobility and strong spin–orbit coupling

Systematic electrical transport characterizations were performed on high-quality Bi2O2Se nanowires to illustrate its great transport properties and further application potentials in spintronics. Bi2O2Se nanowires synthesized by chemical vapor deposition method presented a high field-effect mobility up to ∼1.34 × 104 cm2 V−1 s−1 and exhibited ballistic transport in the low back-gate voltage (Vg) regime where conductance plateaus were observed. When further increasing the electron density by increasing Vg, we entered the phase coherent regime and weak antilocalization (WAL) was observed. The spin relaxation length extracted from the WAL was found to be gate tunable, ranging from ∼100 nm to ∼250 nm and reaching a stronger spin–obit coupling (SOC) than the two-dimensional counterpart (flakes). We attribute the strong SOC and the gate tunability to the presence of a surface accumulation layer, which induces a strong inversion asymmetry on the surface. Such scenario was supported by the observation of two Shubnikov–de Haas oscillation frequencies that correspond to two types of carriers, one on the surface and the other in the bulk. The high-quality Bi2O2Se nanowires with a high mobility and a strong SOC can act as a very prospective material in future spintronics.

High performance carbon nanotubes thin film transistors by selective ferric chloride doping

Single wall carbon nanotubes (SWNT) have been a significant research topic as active layers for thin film transistors (TFTs) due to their high charge carrier mobility beyond that of crystalline silicon. In this study, we report an effective approach to achieve a very high field-effect mobility and on/off ratio for solution processed semiconducting SWNT TFTs, by selective doping through contact with a thin ferric chloride (FeCl3) dopant layer. The semiconducting layer is formed by a double spin coating of the highly purified (>99%) high pressure carbon mono oxide (HiPCO) SWNT sorted by wrapping of poly (3-dodecylthiophene-2,5-diyl) (P3DDT). In order to achieve effective hole injection from the top Au source electrode without increasing the off-state drain current, less purified (98-99%) SWNTs produced by the plasma discharge process sorted by wrapping of poly (9,9-di-n-dodecylfluorene) (PFDD) are formed on the top of HiPCO film. Significantly improved TFT performance is achieved by the insertion of a few nanometers of a FeCl3 dopant layer at the semiconductor-contact interface. A significant high hole field-effect of 48.35 ± 3.11 cm2V−1s−1 (bare: 6.18 ± 0.87 cm2V−1s−1) with a reasonable on/off current ratio of 105, and low off current of ∼80 pA, are obtained by controlling the concentration of FeCl3 dopant (thickness = 1.5 nm) at the contact. Mobility is improved further at 2.5 nm thickness of the FeCl3 dopant layer resulting in a hole mobility of 177 ± 13.2 cm2 V−1s−1, an on/off ratio of 7.4 × 103, and off state current of 1.2 × 10−9 A.

Fluorine-passivated In2O3 thin film transistors with improved electrical performance via low-temperature CF4/N2O plasma

In this Letter, we report the electrical performance improvement of indium oxide (In2O3) thin film transistors (TFTs) via a low-temperature CF4/N2O plasma treatment. It is found that the fluorination via CF4/N2O plasma can reduce the excessive electrons in the In2O3 channel more effectively compared to the oxidative annealing, providing the same low off-currents at a lower temperature of 200 °C, while the hydrogenation could not give rise to the off-current reduction. The fluorinated In2O3 TFTs with a channel thickness of 3.5 nm, a HfO2 dielectric thickness of 3.5 nm, and a channel length ranging from 80 nm to 1 μm demonstrate markedly improved electrical performances, including a high field effect mobility of 72.8 cm2/V s, a more positive threshold voltage, a higher on/off current ratio of ∼106, a smaller subthreshold swing below 200 mV/dec, and a higher stability to both negative and positive gate biases. X-ray photoelectron spectroscopy (XPS) confirms the fluorine incorporation in In2O3/HfO2 heterojunction upon CF4/N2O plasma, speculatively passivating the oxygen vacancies and explaining TFT performance enhancement. This study suggests that the anion doping such as fluorine incorporation could be an effective method to improve the performance of oxide semiconductor TFTs with ultrathin channel and dielectric.

A general one-step plug-and-probe approach to top-gated transistors for rapidly probing delicate electronic materials.

The miniaturization of silicon-based electronics has motivated considerable efforts in exploring new electronic materials, including two-dimensional semiconductors and halide perovskites, which are usually too delicate to maintain their intrinsic properties during the harsh device fabrication steps. Here we report a convenient plug-and-probe approach for one-step simultaneous van der Waals integration of high-k dielectrics and contacts to enable top-gated transistors with atomically clean and electronically sharp dielectric and contact interfaces. By applying the plug-and-probe top-gate transistor stacks on two-dimensional semiconductors, we demonstrate an ideal subthreshold swing of 60 mV per decade. Using this approach on delicate lead halide perovskite, we realize a high-k top-gate CsPbBr3 transistor with a low operating voltage and a very high two-terminal field-effect mobility of 32 cm2 V-1 s-1. This approach can be extended to centimetre-scale MoS2 and perovskite and generate top-gated transistor arrays, offering a rapid and convenient way of accessing intrinsic properties of delicate emerging materials.

High-Performance Thin-Film Transistor with Atomic Layer Deposition (ALD)-Derived Indium-Gallium Oxide Channel for Back-End-of-Line Compatible Transistor Applications: Cation Combinatorial Approach.

In this paper, the feasibility of an indium-gallium oxide (In2(1-x)Ga2xOy) film through combinatorial atomic layer deposition (ALD) as an alternative channel material for back-end-of-line (BEOL) compatible transistor applications is studied. The microstructure of random polycrystalline In2Oy with a bixbyite structure was converted to the amorphous phase of In2(1-x)Ga2xOy film under thermal annealing at 400 °C when the fraction of Ga is ≥29 at. %. In contrast, the enhancement in the orientation of the (222) face and subsequent grain size was observed for the In1.60Ga0.40Oy film with the intermediate Ga fraction of 20 at. %. The suitability as a channel layer was tested on the 10-nm-thick HfO2 gate oxide where the natural length was designed to meet the requirement of short channel devices with a smaller gate length (<100 nm). The In1.60Ga0.40Oy thin-film transistors (TFTs) exhibited the high field-effect mobility (μFE) of 71.27 ± 0.98 cm2/(V s), low subthreshold gate swing (SS) of 74.4 mV/decade, threshold voltage (VTH) of -0.3 V, and ION/OFF ratio of >108, which would be applicable to the logic devices such as peripheral circuit of heterogeneous DRAM. The in-depth origin for this promising performance was discussed in detail, based on physical, optical, and chemical analysis.

Rational design of oxide heterostructure InGaZnO/TiO2 for high-performance thin-film transistors

In this study, hetero-structured and self-passivated oxide thin film transistors (TFTs) were fabricated, wherein the channel comprised a N2O plasma (a-IGZO:N2O) treated a-IGZO front layer and TiO2 ultra-thin back layer. A high field-effect mobility (μFE) of 40.5 cm2/Vs and small sub-threshold swing (SS) of 250 mV/decade upon a SiO2/Si substrate were achieved using a rational design. Moreover, small threshold voltage shifts (ΔVth) of 0.5 (−0.7) and 0.8 (−0.9) V under gate bias and light illumination stress tests were obtained. Using Si3N4/HfO2 gate dielectrics, μFE and SS were enhanced to 53.6 cm2/Vs and 75 mV/decade, respectively. Experimental observations indicate that the electrons transfer from TiO2 to a-IGZO:N2O layer resulted in the accumulation of free carriers near a-IGZO:N2O/TiO2 interfaces. Additionally, an appropriate N2O treatment reduced the oxygen-related defects and bulk/interface trap density, while controlling the carrier density in the bilayer a-IGZO:N2O/TiO2 TFTs. Furthermore, the ultra-thin TiO2 layer acted as a surface passivation layer that reduced the leakage current and protected the channel from ambient influences. The proposed high-performance hetero-structured a-IGZO:N2O/TiO2 TFTs with superior stability are expected to provide a new and effective approach to obtaining high-performance metal oxide TFTs for application in thin film electronics.

(Invited, Digital Presentation) Nondegenerate Hydrogen-Doped Polycrystalline Indium Oxide (InOx:H) Thin Films for High-Mobility Thin Film Transistors

Transparent metal oxide semiconductors (OSs) have been extensively investigated for use as the active channel layer of thin film transistors (TFTs) for next-generation flat-panel displays, nonvolatile memories, image sensors, and pH sensors, to name a few. Among OSs, the amorphous In–Ga–Zn–O (IGZO) has attracted particular attention for TFT applications owing to its high field effect mobility (μFE) of more than 10 cm2V−1s−1, steep subthreshold swing (S.S.), extremely low off-state current, large-area uniformity, and good bias stress stability. Although the μFE of an IGZO TFT is approximately one order of magnitude higher than that of an amorphous Si TFT, further improvement of the μFE of OS TFTs is required to expand their range of applications as an alternative to polycrystalline Si TFT.Single-crystalline In2O3 has a Hall mobility as high as 160 cm2V−1s−1, which makes amorphous (a-) or polycrystalline (poly-) InOx a potential material for enhancing the μFE of OS TFTs. However, undoped InOx thin films is known as a degenerate semiconductor with high background electron density of over 1020 cm-3, which is attributed to the presence of native defects, such as oxygen vacancies, making them unsuitable for a channel material of OS TFTs. In this presentation, nondegenerate hydrogen-doped polycrystalline InOx (poly-InOx:H) thin films were successfully prepared by low-temperature solid phase crystallization (SPC). A degenerate amorphous InOx:H thin film was deposited by sputtering in Ar, O2, and H2 gases, and an amorphous to polycrystalline phase transition (SPC) of the film was achieved after PDA at more than 175 °C. By PDA at 250 °C in air, a nondegenerate poly-InOx:H film could be obtained with a carrier density as low as 2.4 × 1017 cm−3, which is approximately three orders of magnitude lower than that of the initial a-InOx:H film. The TFTs with a 50 nm thick nondegenerate poly-InOx:H channel could be fully depleted by a gate electric field. A maximum μFE of 125.7 cm2V−1s−1 was exhibited by the TFT with the poly-InOx:H channel. The use of a nondegenerate poly-InOx:H film is a promising approach to boost the μFE of OS TFTs.

(Invited) Achieving Lower Power Logic Using P-Type Metal Oxide Thin Film Transistors

Thin film transistors (TFTs) have enabled the active matrix displays that are a ubiquitous part of everyday life, from mobile phones and tablets through to desktop monitors and home televisions. They are used in the circuit at each pixel over the display as they can be fabricated for relatively low cost with excellent uniformity at low temperatures over large areas on glass substrates. These pixel circuits only require either n-channel or p-channel enhancement mode TFTs. However, there has long been a desire to integrate the display driver electronics onto the display panel as an alternative to connecting silicon-based integrated circuits using complementary metal oxide semiconductor (CMOS) field effect transistors (FETs) to displays. More recently, there has been an increasing interest in producing other logic circuits using TFTs on glass and plastic substrates as this could enable a new generation of products with embedded electronics. However, both of these applications need low power logic circuits. CMOS is an inherently low power technology, but it requires both n-channel and p-channel transistors. Whilst this can be realised in silicon CMOS FETs, it has not yet been achieved using TFTs because it has proved difficult to realise both n-channel and p-channel devices using one material system at low cost. For example, hydrogenated amorphous silicon can be used to make reasonable n-type material but not p-type.Thin film oxide semiconductors such as amorphous indium gallium zinc oxide have been successfully commercialised in the pixel circuits of active matrix displays as they possess high field effect mobility, low threshold voltage, low off-state current and a high switching ratio. There is therefore a lot of interest in finding a suitable complementary p-type metal oxide thin film material to allow CMOS-type logic to be realised using this material system.Cuprous oxide is one such promising candidate material as the top of the valence band is dominated by states which form as a result of hybridisation of the completely filled Cu 3d orbitals and the O 2p orbitals. These hybridised states are less localised and have a higher dispersion with a resulting decrease in the effective mass of holes in these states and a higher carrier mobility. The results of an extensive study of this material shows that the grain structure is of critical importance with [100] oriented films resulting in a higher mobility. Furthermore, the impact of grain boundaries on conduction must be controlled. Although this allows TFTs with reasonable on-state current to be fabricated, it is found that there is a significant residual off-state current which is a result of electron accumulation in the channel. This is consistent with the high off-state current that has been observed widely in TFTs using p-type metal oxide thin film materials.The low off-state current in silicon MOSFETs means that the geometric transistor design in low power CMOS logic circuits only needs to focus on the effect of the on-state current in the p-channel and n-channel transistors. However, in TFTs, the much larger off-state current also becomes important as it can end up being a significant parameter when calculating the power consumption of CMOS logic circuits. An alternative geometric design parameter for TFT logic circuits is presented. This compares the maximum switching current with the static currents allowing optimisation based on both the noise margin and static power consumption. The result is improved performance of TFT-based CMOS logic circuits using the n- and p-type thin film oxide semiconductors that are currently available.