High Level Of Abstraction Research Articles

Safe abstractions of data encodings in formal security protocol models

Abstract When using formal methods, security protocols are usually modeled at a high level of abstraction. In particular, data encoding and decoding transformations are often abstracted away. However, if no assumptions at all are made on the behavior of such transformations, they could trivially lead to security faults, for example leaking secrets or breaking freshness by collapsing nonces into constants. In order to address this issue this paper formally states sufficient conditions, checkable on sequential code, such that if an abstract protocol model is secure under a Dolev–Yao adversary, then a refined model, which takes into account a wide class of possible implementations of the encoding/decoding operations, is implied to be secure too under the same adversary model. The paper also indicates possible exploitations of this result in the context of methods based on formal model extraction from implementation code and of methods based on automated code generation from formally verified models.

A high abstraction level approach for detecting feature interactions between telecommunication services

When several telecommunication services are running at the same time, undesirable behaviors may arise, which are commonly called feature interactions. Several methods have been developed for detecting and resolving feature interactions. However, most of these methods are based on detailed models of services, which make them suffer from state space explosion. Moreover, different telecommunication operators cannot cooperate to manage feature interactions by exchanging detailed service models because this violates the confidentiality principle. Our work is a part of the few attempts to develop feature interaction detection methods targeting to avoid or reduce significantly state space explosion. In order to reach this objective, we first develop a so called Cause–Restrict language to model subscribers of telecommunication services at a very high abstraction level. A Cause–Restrict model of a subscriber provides information such as: what is the cause of what, and what restricts (or forbids) what, and specifies coarsely the frequency of each operation “cause” or “restrict” by “always” or “sometimes”. Then, we develop a method that detects feature interactions between telecommunication services modeled in the Cause–Restrict language. We demonstrate the applicability of our approach by modeling several services and detecting several feature interactions between them. New feature interactions have been detected by our approach.

Integrating the SysML and the SystemC-UML profiles in a model-driven embedded system design flow

Modern embedded systems development, due to systems complexity and multifaceted nature, requires flexible high-level design techniques and notations. In this context, model-driven approaches are gaining popularity, both in industry as well as in academy, since they offer a high degree of abstraction and provide a common framework for the design, simulation and configuration management of complex heterogeneous systems. Moreover, a great variety of languages have been emerging as customization (or profiles) of the Unified Modeling Language (UML) for the embedded system and System-on-Chip (SoC) domains. No single modeling language or profile is adequate to cover aspects and requirements of the whole system development flow. Indeed, each of these languages owns characteristics and offers modeling primitives suitable for designing at a specific abstraction level. Therefore, possible strategies for integrating such UML profiles must be determined, in order to establish a common modeling framework able to support all steps of a system design development. This paper presents the integration of two modeling languages, the SysML and the SystemC UML profiles. The integration is based on a mapping from the SysML to the SystemC UML profile for the structural aspects, while for the behavioral aspects two main models of computation, SysML control-flow graphs and SystemC Process state machines, are proposed as complementary behavioral formalisms to be adopted in a model-driven SoC design flow at platform-independent and platform-specific description level, respectively. The integration we propose, has enabled us also to refine an already defined model-driven hardware-software co-design flow, where a gap remained moving from a platform-independent design level to a platform-specific level. The refined co-design flow starts from a SysML description at a high level of design abstraction, and proceeds through a chain of refined SystemC UML models, to lower levels of design abstraction, where the more complex last-level SystemC coding is left to automation.

Expressing embedded systems configurations at high abstraction levels with UML MARTE profile: Advantages, limitations and alternatives

Embedded systems have become an essential aspect of our professional and personal lives. From avionics, transport and telecommunication systems to general commercial appliances such as smart phones, high definition TVs and gaming consoles; it is difficult to find a domain where these systems have not made their mark. Moreover, Systems-on-Chips (SoCs) which are considered as an integral solution for designing embedded systems, offer advantages such as run-time reconfiguration that can change system configurations during execution, depending upon Quality-of-Service (QoS) criteria such as performance and energy levels. This article deals with aspects related to modeling of these configurations, useful for describing various states of an embedded system, from both structural and operational viewpoints. Our proposal adapts a high abstraction level approach based on the principles of Model-Driven Engineering (MDE) and takes into account the UML MARTE profile for modeling of real-time and embedded systems. Elevating the design abstraction levels help to increase design productivity and achieve execution platform independence, among other advantages. The article details the current proposition of configurations in MARTE via some examples, and points out the advantages as well as some limitations, mainly concerning the semantic aspects of the defined concepts. Finally, we report our experiences on the modeling of an alternate notion of configurations and execution modes within the MARTE compliant Gaspard2 SoC Co-Design framework that has been successful for the design as well as implementation of FPGA based SoCs.

On the simulation of large-scale architectures using multiple application abstraction levels

Simulation is a key tool for computer architecture research. In particular, cycle-accurate simulators are extremely important for microarchitecture exploration and detailed design decisions, but they are slow and, so, not suitable for simulating large-scale architectures, nor are they meant for this. Moreover, microarchitecture design decisions are irrelevant, or even misleading, for early processor design stages and high-level explorations. This allows one to raise the abstraction level of the simulated architecture, and also the application abstraction level, as it does not necessarily have to be represented as an instruction stream. In this paper we introduce a definition of different application abstraction levels, and how these are employed in TaskSim, a multi-core architecture simulator, to provide several architecture modeling abstractions, and simulate large-scale architectures with hundreds of cores. We compare the simulation speed of these abstraction levels to the ones in existing simulation tools, and also evaluate their utility and accuracy. Our simulations show that a very high-level abstraction, which may be even faster than native execution, is useful for scalability studies on parallel applications; and that just simulating explicit memory transfers, we achieve accurate simulations for architectures using non-coherent scratchpad memories, with just a 25x slowdown compared to native execution. Furthermore, we revisit trace memory simulation techniques, that are more abstract than instruction-by-instruction simulations and provide an 18x simulation speedup.

A Model-Driven Design Framework for Massively Parallel Embedded Systems

Modern embedded systems integrate more and more complex functionalities. At the same time, the semiconductor technology advances enable to increase the amount of hardware resources on a chip for the execution. Massively parallel embedded systems specifically deal with the optimized usage of such hardware resources to efficiently execute their functionalities. The design of these systems mainly relies on the following challenging issues: first, how to deal with the parallelism in order to increase the performance; second, how to abstract their implementation details in order to manage their complexity; third, how to refine these abstract representations in order to produce efficient implementations. This article presents the Gaspard design framework for massively parallel embedded systems as a solution to the preceding issues. Gaspard uses the repetitive Model of Computation (MoC), which offers a powerful expression of the regular parallelism available in both system functionality and architecture. Embedded systems are designed at a high abstraction level with the MARTE (Modeling and Analysis of Real-time and Embedded systems) standard profile, in which our repetitive MoC is described by the so-called Repetitive Structure Modeling (RSM) package. Based on the Model-Driven Engineering (MDE) paradigm, MARTE models are refined towards lower abstraction levels, which make possible the design space exploration. By combining all these capabilities, Gaspard allows the designers to automatically generate code for formal verification, simulation and hardware synthesis from high-level specifications of high-performance embedded systems. Its effectiveness is demonstrated with the design of an embedded system for a multimedia application.

Jaql

This paper describes Jaql, a declarative scripting language for analyzing large semistructured datasets in parallel using Hadoop's MapReduce framework. Jaql is currently used in IBM's InfoSphere BigInsights [5] and Cognos Consumer Insight [9] products. Jaql's design features are: (1) a flexible data model, (2) reusability, (3) varying levels of abstraction, and (4) scalability. Jaql's data model is inspired by JSON and can be used to represent datasets that vary from flat, relational tables to collections of semistructured documents. A Jaql script can start without any schema and evolve over time from a partial to a rigid schema. Reusability is provided through the use of higher-order functions and by packaging related functions into modules. Most Jaql scripts work at a high level of abstraction for concise specification of logical operations (e.g., join), but Jaql's notion of physical transparency also provides a lower level of abstraction if necessary. This allows users to pin down the evaluation plan of a script for greater control or even add new operators. The Jaql compiler automatically rewrites Jaql scripts so they can run in parallel on Hadoop. In addition to describing Jaql's design, we present the results of scale-up experiments on Hadoop running Jaql scripts for intranet data analysis and log processing.

A neural model of human fear pathways based on anatomical and neuroimaging data

Fear responses in the human brain consist of several evolved pathways with different levels of processing [1]. A neural model has been developed for human fear, which includes a subcortical (low) road and cortical (high) road for affective processing and cortical control. The neural model is at a mid to high level of abstraction, at the level of neural populations. Each brain region of interest (ROI) in the model is represented by one or more neural populations. Neurons in these populations are non-spiking, adapting and can have both excitatory and inhibitory connections. A neural activity level (mean spiking rate) between 0 and 1 was recorded for every population within an ROI. This output was convolved with a canonical hemodynamic response function (HRF) to produce a synthetic BOLD signal for comparison with PET and fMRI experimental data. To compare model simulations with a fear/phobic PET study [2], event and timing protocols were mapped to corresponding model inputs, which included both masked and long presentations of fear relevant and neutral images for phobic and non-phobic subjects. The thalamus, visual cortex (2 levels), amygdala, orbitofrontal cortex (OFC) and prefrontal cortex (PFC) are represented in the model as ROIs. Several recurrent loops are represented, including visual cortical-thalamic and PFC-OFC loops. The amygdala has neural populations for the intercalated cells (ITC), lateral and central nuclei. Amygdala inputs entering the lateral nuclei are modulated by the ITC before producing output from the central nuclei. The phobic state was simulated by reducing the strength of the recurrent connections between the neural populations involved in a PFC-OFC loop, resulting in less inhibition of the amygdala via the ITC. Simulation results are presented that show activation of neural populations over simulated trials which correspond with ROI activity in the fear PET study. Figure 1 Fear network model and simulation results. A. Neural non-spiking population model with 7 ROIs.B. Neural population mean-field levels from a simulation of a masked, long (274ms) fear-relevant stimulus.

WSO2 Stratos: An Application Stack to Support Cloud Computing

Abstract Cloud computing has heralded many advantages including self-service, elasticity, pay as you go, improved accessibility to computation resources, and ease of deployment and deployment automation. However, to extend those advantages to a larger audience, higher-level abstractions such as Software as a Service (SaaS) or Platform as a Service (PaaS) are needed. This paper presents Stratos, which is a Platform-as-a-Service based around the principles and design of Service Oriented Architecture (SOA). Furthermore, we introduce the concept of Cloud Native attributes, which we argue are properties essential to extend the benefits of the underlying Cloud to PaaS and SaaS users. We present Stratos as a Cloud Native PaaS offering, discuss the architecture that enables Cloud Native attributes, and discuss scenarios where Stratos can be useful to the end user.

Chemistry at a Higher Level of Abstraction

Chemistry at a Higher Level of Abstraction

Toward higher level abstractions for cloud computing

The general idea of cloud computing is offering computational resources as scalable, on demand services accessible over the internet. However, this new realisation of on demand computing is hindered by the amount of user involvement. Currently, high level abstractions in cloud computing only exist in the form of services. In particular, there is no effective means to publish, discover and finally use required services in clouds. In response, we propose a user level abstraction on top of already available cloud abstraction layers, present its concept using the resources via web services (RVWS) framework and demonstrate its feasibility by simplifying the exposure and use of clusters, a commonly used resource in cloud computing.

A Comparison of High-Level Approaches for Speeding Up Pathfinding

Most games being shipped today use some form of high-level abstraction such as a navmesh or waypoint graph for path planning. These structures can generally be represented in a form which is compact enough to meet the tight memory constraints in a game. But, when such a graph grows too large, finding paths can still be a complex task. This challenge was faced in Dragon Age: Origins and solved by adding an additional level of abstraction.In the last few years a variety of novel approaches have been developed for finding optimal paths through graphs with specific design applications for road networks. Currently these techniques cannot be feasibly applied to the lowest detail of movement possible in a game map, but can be applied to the high-level abstractions which are commonly found in games.In this paper we describe the pathfinding challenge faced before shipping the title Dragon Age: Origins and perform a postmortem analysis on the extended abstraction that was used in comparison to building more advanced heuristics or the use of contraction hierarchies. We show that contraction hierarchies and abstractions have similar overhead and performance and are both useful approaches for high-level planning in games.

Teaching Programming Principles through a Game Engine


 
 
 Teaching fundamental programming to freshmen is a hard task to be performed, given the high level of abstraction and logical reasoning that are required for these students to develop in a very early stage of their course. This paper presents a discussion about this topic, along with a case study where computer games are meant to be developed by students in a first programming course, through the use of a game engine which allow students to develop fundamental programming skills without having to learn syntax and idiosyncrasies of any programming language.
 
 

Certification of thread context switching

With recent efforts to build foundational certified software systems, two different approaches have been proposed to certify thread context switching. One is to certify both threads and context switching in a single logic system, and the other certifies threads and context switching at different abstraction levels. The former requires heavy weight extensions in the logic system to support first-class code pointers and recursive specifications. Moreover, the specification for context switching is very complex. The latter supports simpler and more natural specifications, but it requires the contexts of threads to be abstracted away completely when threads are certified. As a result, the conventional implementation of context switching used in most systems needs to be revised to make the abstraction work. In this paper, we extend the second approach to certify the conventional implementation, where the clear abstraction for threads is unavailable since both threads and context switching hold pointers of thread contexts. To solve this problem, we allow the program specifications for threads to refer to pointers of thread contexts. Thread contexts are treated as opaque structures, whose contents are unspecified and should never be accessed by the code of threads. Therefore, the advantage of avoiding the direct support of first-class code pointers is still preserved in our method. Besides, our new approach is also more lightweight. Instead of using two different logics to certify threads and context switching, we employ only one program logic with two different specifications for the context switching. One is used to certify the implementation itself, and the more abstract one is used as an interface between threads and context switching at a higher abstraction level. The consistency between the two specifications are enforced by the global program invariant.

OpenRoads

We present OpenRoads, an open-source platform for innovation in mobile networks. OpenRoads enable researchers to innovate using their own production networks, through providing an wireless extension OpenFlow. Therefore, you can think of OpenRoads as "OpenFlow Wireless". The OpenRoads' architecture consists of three layers: flow, slicing and controller. These layers provide flexible control, virtualization and high-level abstraction. This allows researchers to implement wildly different algorithms and run them concurrently in one network. OpenRoads also incorporates multiple wireless technologies, specifically WiFi and WiMAX. We have deployed OpenRoads, and used it as our production network. Our goal here is for those to deploy OpenRoads and build their own experiments on it.

Targeting reconfigurable FPGA based SoCs using the UML MARTE profile: from high abstraction levels to code generation

As SoC design complexity is escalating to new heights, there is a critical need to find adequate approaches and tools to handle SoC co-design aspects. Additionally, modern reconfigurable SoCs offer advantages over classical SoCs as they integrate adaptivity features to cope with mutable design requirements and environment needs. This paper presents a novel approach to address system adaptivity and reconfigurability. A generic model of reactive control is presented in a SoC codesign framework: Gaspard. Afterwards, control integration at different levels of the framework is illustrated for both functional specification and FPGA synthesis. The presented work is based on Model-Driven Engineering and the UML MARTE profile proposed by Object Management Group, for modeling and analysis of real-time embedded systems. The paper thus presents a complete design flow to move from high level MARTE models to code generation, for implementation of dynamically reconfigurable SoCs.

A look at Ada from both sides now (a government, and a defense contractor perspective)

The Ada programming language has had a remarkable history, and promises an even more remarkable future. In this keynote address, Dr. J. Smart from Raytheon will provide his perspective on both as seen from within government, and from within private industry. With the pervasive nature of computing, the trade-craft of contemporary software development has changed considerably in recent years. Arguably, not all the change has been for the better. What may have once been regarded as minor flaws or operational nuisances in software system implementations can now manifest in far more devastating ways, and with potentially severe consequences. The boundaries of Ada's "embedded system" niche are becoming increasingly difficult to discern from commodity software, particularly as the challenges of computer security compound. A critical need now exists for a much broader application of the unique culture and programming discipline that has naturally accompanied Ada for these many years. Of particular personal research interest to the presenter is the new generation of reconfigurable computing systems and devices (e.g., FPGAs). The ability to specify a system from the highest level of abstraction all the way down to an individual gate level is now possible from within a single unified description framework. Ada is potentially the ideal choice for such a framework. The presenter will describes his experiences using Ada in this manner to design and implement a most unusual dynamic computing machine. In this application where reliability and formal verification is of upmost importance, the Ada language has been the major contributor to the effort's success.

How We Might Be Able to Understand the Brain

Abstract Current methodologies in the neurosciences have difficulty in accounting for complex phenomena such as language, which can however be quite well characterised in phenomenological terms. This paper addresses the issue of unifying the two approaches. We typically understand complicated systems in terms of a collection of models, each characterisable in principle within a formal system, it being possible to explain higher-level properties in terms of lower level ones by means of a series of inferences based on these models. We consider the nervous system to be a mechanism for implementing the demands of an appropriate collection of models, each concerned with some aspect of brain and behaviour, the observer mechanism of Baas playing an important role in matching model and behaviour in this context. The discussion expounds these ideas in detail, showing their potential utility in connection with real problems of brain and behaviour, important areas where the ideas can be applied including the development of higher levels of abstraction, and linguistic behaviour, as described in the works of Karmiloff-Smith and Jackendoff respectively.

From the EIC: Building and verifying hardware at a higher level of abstraction

From the EIC: Building and verifying hardware at a higher level of abstraction

High abstraction level CAD tool implementation of MOS drain current models

This paper presents a toolbox in which a compact high abstraction level formulation of the MOS drain current was implemented. The formulation is based on the popular ACM compact MOS model: the approximations introduced in the model preserve the drain-to-source device symmetry and the continuity between all regions of operation (i.e. weak, moderate and strong inversion). The technological parameters involved in the formulation are obtained by means of a fully automatic extraction procedure. Finally, a detailed case study, in which a behavioural analysis of sample-and-hold circuits using the proposed toolbox is performed, is presented. The ATMEL®0.24μm CMOS process was used as reference for the case study. The MATLAB® environment was used to implement the drain current model formulation, the technological parameters extraction and the case study as well.