Higher Hardware Efficiency Research Articles

A Compact Hardware Design and Implementation on FPGA Based Hybrid of AES and Keccak SHA3-512 for Enhancing Data Security

Data security means protecting important information from unauthorised persons. In a security system, cryptography is the most secure method. Cryptography has many kinds, but the Advanced Encryption Standard (AES) is the most secure system. If combined with AES and Secure Hash Algorithm-3-512Bits (SHA3-512), it becomes compact, more secure, and more authenticated for data communications. The proposed methodology is a hybrid cryptography technique that combines AES with the SHA3-512 algorithm. This system becomes a strong, secure system and produces a strong cipher text. The proposed method AES/SHA3-512 is Hardware implementation on the Artix-7 FPGA family yields the lowest cost and highest hardware efficiency with a reduction in area usage of LUT 18.49%, Flip Flops 0.83%, and IO 3.8%. The proposed architecture is synthesised and simulated using the Vivado 2017.2 version Tool.

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

A High Efficiency Hardware Implementation of S-Boxes Based on Composite Field for Advanced Encryption Standard

Design of High Hardware Efficiency Approximate Floating-Point FFT Processor

Design of High Hardware Efficiency Approximate Floating-Point FFT Processor

SpikoPoniC: A Low-Cost Spiking Neuromorphic Computer for Smart Aquaponics

Aquaponics is an emerging area of agricultural sciences that combines aquaculture and hydroponics in a symbiotic way to enhance crop production. A stable smart aquaponic system requires estimating the fish size in real time. Though deep learning has shown promise in the context of smart aquaponics, most smart systems are extremely slow and costly and cannot be deployed on a large scale. Therefore, we design and present a novel neuromorphic computer that uses spiking neural networks (SNNs) for estimating not only the length but also the weight of the fish. To train the SNN, we present a novel hybrid scheme in which some of the neural layers are trained using direct SNN backpropagation, while others are trained using standard backpropagation. By doing this, a blend of high hardware efficiency and accuracy can be achieved. The proposed computer SpikoPoniC can classify more than 84 million fish samples in a second, achieving a speedup of at least 3369× over traditional general-purpose computers. The SpikoPoniC consumes less than 1100 slice registers on Virtex 6 and is much cheaper than most SNN-based hardware systems. To the best of our knowledge, this is the first SNN-based neuromorphic system that performs smart real-time aquaponic monitoring.

Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications

Developing flexible, high-processing-rate, and low-power BLAKE/BLAKE2 hardware is extremely necessary for maintaining dependability, safety, and security in blockchain-based IoT systems. However, the existing hardware designs are difficult to achieve high flexibility and performance with high hardware efficiency. Therefore, this paper proposes the first flexible and scalable BLAKE/BLAKE2 coprocessor to gain high flexibility, high performance, and low power for blockchain-based IoT applications. To achieve those goals, three novel optimization techniques are proposed, including a dual-core hashing engine, a pipelined hashing engine, and a scalable four-engine coprocessor. The experimental results on FPGA and ASIC prove that our coprocessor is 3.6-65.5 times, 1.4-2.9 times, and 113-195 times better than existing works in throughput, area efficiency, and energy efficiency, respectively. Additionally, our coprocessor supports more hash functions, making it more flexible than previous architectures. Besides, the proposed coprocessor outperforms the industrial CPU/GPU by 4.7-7.1 times in the energy-delay product (EDP).

Review of Wireless RFID Strain Sensing Technology in Structural Health Monitoring.

Strain-based condition evaluation has garnered as a crucial method for the structural health monitoring (SHM) of large-scale engineering structures. The use of traditional wired strain sensors becomes tedious and time-consuming due to their complex wiring operation, more workload, and instrumentation cost to collect sufficient data for condition state evaluation, especially for large-scale engineering structures. The advent of wireless and passive RFID technologies with high efficiency and inexpensive hardware equipment has brought a new era of next-generation intelligent strain monitoring systems for engineering structures. Thus, this study systematically summarizes the recent research progress of cutting-edge RFID strain sensing technologies. Firstly, this study introduces the importance of structural health monitoring and strain sensing. Then, RFID technology is demonstrated including RFID technology's basic working principle and system component composition. Further, the design and application of various kinds of RFID strain sensors in SHM are presented including passive RFID strain sensing technology, active RFID strain sensing technology, semi-passive RFID strain sensing technology, Ultra High-frequency RFID strain sensing technology, chipless RFID strain sensing technology, and wireless strain sensing based on multi-sensory RFID system, etc., expounding their advantages, disadvantages, and application status. To the authors' knowledge, the study initially provides a systematic comprehensive review of a suite of RFID strain sensing technology that has been developed in recent years within the context of structural health monitoring.

High-Performance Acceleration of 2-D and 3-D CNNs on FPGAs Using Static Block Floating Point.

Over the past few years, 2-D convolutional neural networks (CNNs) have demonstrated their great success in a wide range of 2-D computer vision applications, such as image classification and object detection. At the same time, 3-D CNNs, as a variant of 2-D CNNs, have shown their excellent ability to analyze 3-D data, such as video and geometric data. However, the heavy algorithmic complexity of 2-D and 3-D CNNs imposes a substantial overhead over the speed of these networks, which limits their deployment in real-life applications. Although various domain-specific accelerators have been proposed to address this challenge, most of them only focus on accelerating 2-D CNNs, without considering their computational efficiency on 3-D CNNs. In this article, we propose a unified hardware architecture to accelerate both 2-D and 3-D CNNs with high hardware efficiency. Our experiments demonstrate that the proposed accelerator can achieve up to 92.4% and 85.2% multiply-accumulate efficiency on 2-D and 3-D CNNs, respectively. To improve the hardware performance, we propose a hardware-friendly quantization approach called static block floating point (BFP), which eliminates the frequent representation conversions required in traditional dynamic BFP arithmetic. Comparing with the integer linear quantization using zero-point, the static BFP quantization can decrease the logic resource consumption of the convolutional kernel design by nearly 50% on a field-programmable gate array (FPGA). Without time-consuming retraining, the proposed static BFP quantization is able to quantize the precision to 8-bit mantissa with negligible accuracy loss. As different CNNs on our reconfigurable system require different hardware and software parameters to achieve optimal hardware performance and accuracy, we also propose an automatic tool for parameter optimization. Based on our hardware design and optimization, we demonstrate that the proposed accelerator can achieve 3.8-5.6 times higher energy efficiency than graphics processing unit (GPU) implementation. Comparing with the state-of-the-art FPGA-based accelerators, our design achieves higher generality and up to 1.4-2.2 times higher resource efficiency on both 2-D and 3-D CNNs.

A 218 GOPS neural network accelerator based on a novel cost-efficient surrogate gradient scheme for pattern classification

The accuracy and hardware efficiency of a neural system depends critically on the choice of an activation function. Rectified linear unit (ReLU) is a contemporary activation function that yields high accuracy and allows the construction of efficient neural chips, but it results in a lot of dead neurons, especially at the output layer. This problem is more pronounced in case of multichannel, multiclass classification. This is due to the fact that ReLU cancels out negative values altogether, as a result of which the corresponding values cannot be successfully backpropagated. This phenomenon is referred to as the dying ReLU problem. In this article, we present a novel ‘surrogate gradient’ learning scheme in order to solve gradient vanishing and the dying ReLU problems. To the best of our knowledge, this is the first learning scheme that enables the use of ReLU for all network layers while solving the Dying ReLU problem. We also present a high-performance inference engine that uses ReLU-based actuators for all the network layers in order to achieve high hardware efficiency. The design is excellent for online learning as well, since the derivative of the activation is equal to a constant and can be implemented using low-complexity components. The proposed technique significantly outperforms various contemporary schemes for the CIFAR-10 dataset, and can successfully yield about 98.39% accuracy on MNIST dataset while using less than 159k synapses. Moreover, the proposed hardware implementation is able to perform about 218 giga operation per second (GOPS) while consuming only about 3.95 slice registers and 25.89 slice look-up tables per synapse on a low-end Virtex 6 FPGA. The system is able to operate at a clock frequency of 93.2 MHz.

Design and implementation for a high-efficiency hardware accelerator to realize the learning machine for predicting OLED degradation

Design and implementation for a high-efficiency hardware accelerator to realize the learning machine for predicting OLED degradation

Iterative Signal Processing for Integrated Sensing and Communication Systems

Integrated sensing and communication (ISAC), with sensing and communication sharing the same wireless resources and hardware, has the advantages of high spectrum efficiency and low hardware cost, which is regarded as one of the key technologies of the fifth generation advanced (5G-A) and sixth generation (6G) mobile communication systems. ISAC has the potential to be applied in the intelligent applications requiring both communication and high accurate sensing capabilities. The fundamental challenges of ISAC system are the ISAC signal design and ISAC signal processing. However, the existing ISAC signal has low anti-noise capability. And the existing ISAC signal processing algorithms have the disadvantages of quantization errors and high complexity, resulting in large energy consumption. In this paper, phase coding is applied in ISAC signal design to improve the anti-noise performance of ISAC signal. Then, the effect of phase coding method on improving the sensing accuracy is analyzed. In order to improve the sensing accuracy with low-complexity algorithm, the iterative ISAC signal processing methods are proposed. The proposed methods improve the sensing accuracy with low computational complexity, realizing energy efficient ISAC signal processing. Taking the scenarios of short distance and long distance sensing into account, the iterative two-dimensional (2D) fast Fourier transform (FFT) and iterative cyclic cross-correlation (CC) methods are proposed, respectively, realizing high sensing accuracy and low computational complexity. Finally, the feasibility of the proposed ISAC signal processing methods are verified by simulation results.

Hybrid Stochastic LDPC Decoder With Fully Correlated Stochastic Computation

The ultra-low hardware consumption feature of stochastic decoding has made it a potential candidate for the implementation of low-density parity-check(LDPC) decoders. However, the existing stochastic LDPC decoders still suffer from performance degradation and relatively high decoding cycles caused by the correlation among stochastic bit streams. In this paper, we propose Hybrid Stochastic(HS) decoding, which achieves high performance, high throughput, and high hardware efficiency by jointly using our proposed novel stochastic check node(CN) and Two’s Complement(TCS) variable node(VN) to realize Min-Sum Algorithm(MSA) and its enhancements. Fully correlated stochastic bit streams are used to entirely eliminate the indeterminacy caused by the correlation, which results in high performance and fast convergence and inherits the low complexity of stochastic decoders at the same time. We demonstrate the HS decoding by designing a (2048,1723) decoder in a 65 nm process, which achieves the highest Bit-Error-Ratio(BER) performance, highest throughput, and top hardware efficiency among existing stochastic LDPC decoders. We also demonstrate that HS decoding can achieve excellent decoding performance for different code rates and lengths 5G New Radio(NR) LDPC codes. Thus, HS decoding can be adopted in wide applications.

Revisiting the Partial Power Processing Concept: Case Study of a 5-kW 99.11% Efficient Flyback Converter-Based Battery Charger

This article proposes an analytical methodology to evaluate the performance of the main partial power processing (PPP) architectures in terms of the improvements in the system’s conversion efficiency. This analysis considers the influence of the system’s voltage gain, the auxiliary dc/dc converter’s efficiency, and the possibility of bidirectional power flow. Herein, the key PPP architectures are, thus, modeled and benchmarked. The presented results attest to the series configuration as the most efficient PPP circuit solution, with no limits on the system voltage gain, contrary to the generalized results found in today’s literature. To assess these results and the significance of the proposed analysis, a well-known, simple, and cost-effective flyback topology has been designed and tested for a series PPP circuit solution able to effectively interface a 5-kW battery energy storage system (BESS) to a 700-V dc grid. A relatively high power conversion efficiency and compact hardware are achieved due to the reduced size requirements on the input and output filtering stages. Above all, while explaining the PPP concept, this study shows that even converter circuits known for their low power efficiency can be used to derive highly efficient systems. A design approach is, thus, provided to facilitate the design of the presented PPP circuit, and measurements are, finally, carried out to compare the obtained results with the expected ones derived from the developed analytical models.

Exploration of the High-Efficiency Hardware Architecture of SM4-CCM for IoT Applications

The widespread use of the internet of things (IoT) is due to the value of the data collected by IoT devices. These IoT devices generate, process, and exchange large amounts of safety-critical or privacy-sensitive data. Before transmission, the data should be protected against information leakage and data stealing. Deploying authenticated encryption with additional data (AEAD) algorithms on IoT devices ensures data confidentiality and integrity. However, AEAD algorithms are computationally intensive, while IoT devices are resource constrained or even battery powered. Therefore, a low-cost, low-power, and high-efficiency method of implementing an AEAD algorithm into resource-constrained IoT devices is required. The SM4-CCM algorithm, introduced in RFC 8998, is selected as the AEAD algorithm to address this problem. Algorithms similar to SM4-CCM (e.g., SM4 and AES-CCM) provide many architectural design references, but it is challenging to decide which architecture is the most suitable for SM4-CCM. In order to find the most efficient SM4-CCM hardware architecture, a design space exploration method is proposed. Firstly, the SM4-CCM algorithm is divided into five layers, and three candidate architectures are provided for each layer. Secondly, 63 design schemes for SM4-CCM are constructed by combining candidate architectures from each layer. Finally, a batch number of comparisons and analyses of experimental results are used to identify the most efficient one. Under TSMC 90 nm technology, the experimental results of the identified scheme show that the throughput, power consumption, and area achieve 199.99 Mbps, 1.625 mW, and 14.6 K gates, respectively. As a proof of concept, implementing this scheme on an FPGA board is also presented.

Optimal Hybrid Precoding Based QoE for Partially Structured Massive MIMO System

Precoding is a beamforming technique that supports multi-stream transmission in which the RF chain plays a significant role as a digital precoding at the receiver for wireless communication. The traditional precoding contains only digital signal processing and each antenna connects to each RF chain, which provides high transmission efficiency but high cost and hardware complexity. Hybrid precoding is one of the most popular massive multiple input multiple output (MIMO) techniques that can save costs and avoid using complex hardware. At present, network services are currently in focus with a wide range of traffic volumes. In terms of the Quality of Service (QoS), it is critical that service providers pay a lot of attention to this parameter and its relationship to Quality of Experience (QoE) which is the measurement of the overall level of user satisfaction. Therefore, this paper proposes hybrid precoding of a partially structured system to improve transmission efficiency and allocate resources to provide network services to users for increasing the user satisfaction under power constraints that optimize the quality of baseband precoding and radio frequency (RF) precoding by minimizing alternating algorithms. We focus on the web browsing, video, and Voice over IP (VOIP) services. Also, a Mean Opinion Score (MOS) is employed to measure the level of user satisfaction. The results show that the partially structured system provides a good user satisfaction with the network's services. The partially structured system provides high energy efficiency up to 85%. Considering web service, the partially structured system for 10 users provides MOS at 3.21 which is higher than 1.75 of fully structured system.

Hardware Phase Shift Hybrid Precoding Designs For Multi-User Massive MIMO Systems

Hybrid precoding is a challenging design for massive MIMO systems that involves a combination of analog and digital processing, aiming to maximize the spectral efficiency (SE). Most works on hybrid precoding focus on the single phase shifter (SPS) implementation to adapt the phase from RF chains to antennas. In this paper we propose to develop the double phase shifter (DPS) and the fixed phase shifter (FPS) in both single-path and multi-path configuration. Simulation results certify a significant improvement for both proposed implementations with high hardware efficiency (HE) and high spectral efficiency especially in multi-path environment.

Reconstruction of a Fully Paralleled Auditory Spiking Neural Network and FPGA Implementation.

This paper presents a field-programmable gate array (FPGA) implementation of an auditory system, which is biologically inspired and has the advantages of robustness and anti-noise ability. We propose an FPGA implementation of an eleven-channel hierarchical spiking neuron network (SNN) model, which has a sparsely connected architecture with low power consumption. According to the mechanism of the auditory pathway in human brain, spiking trains generated by the cochlea are analyzed in the hierarchical SNN, and the specific word can be identified by a Bayesian classifier. Modified leaky integrate-and-fire (LIF) model is used to realize the hierarchical SNN, which achieves both high efficiency and low hardware consumption. The hierarchical SNN implemented on FPGA enables the auditory system to be operated at high speed and can be interfaced and applied with external machines and sensors. A set of speech from different speakers mixed with noise are used as input to test the performance our system, and the experimental results show that the system can classify words in a biologically plausible way with the presence of noise. The method of our system is flexible and the system can be modified into desirable scale. These confirm that the proposed biologically plausible auditory system provides a better method for on-chip speech recognition. Compare to the state-of-the-art, our auditory system achieves a higher speed with a maximum frequency of 65.03 MHz and a lower energy consumption of 276.83 μJ for a single operation. It can be applied in the field of brain-computer interface and intelligent robots.

Efficient Design of Spiking Neural Network With STDP Learning Based on Fast CORDIC

In emerging Spiking Neural Network (SNN) based neuromorphic hardware design, energy efficiency and on-line learning are attractive advantages mainly contributed by bio-inspired local learning with nonlinear dynamics and at the cost of associated hardware complexity. This paper presents a novel SNN design employing fast COordinate Rotation DIgital Computer (CORDIC) algorithm to achieve fast spike timing–dependent plasticity (STDP) learning with high hardware efficiency. In this study, a system design and evaluation method of CORDIC-based SNN is proposed for finding optimal CORDIC type and precision, from theoretical CORDIC-level error to application-level learning performance. From the proposed design and evaluation method, a reconfigurable SNN design based on fast-convergence CORDIC is designed to achieve high classification accuracy on MNIST, fast on-line learning and good energy efficiency. By utilizing SNN’s fault tolerance and time-division-multiplexing (TDM) strategy, the reconfigurable SNN design employs 8-bit fast-convergence CORDIC and TDM-based hardware accelerator for high efficiency. FPGA implementation results confirm that the proposed fast-convergence CORDIC SNN design outperforms the state-of-the-art CORDIC method by 38.5%−45.3% in terms of learning speed and energy efficiency, with the STDP learning of 30.2 ns/SOP, energy efficiency of 176.6 pJ/SOP, processing speed of 6.1 ms/image, and on-line learning convergence of 21.4 s (time to reach the final accuracy, on average), on MNIST benchmark.

An Efficient Ensemble Binarized Deep Neural Network on Chip with Perception-Control Integrated.

Lightweight UAVs equipped with deep learning models have become a trend, which can be deployed for automatic navigation in a wide range of civilian and military missions. However, real-time applications usually need to process a large amount of image data, which leads to a very large computational complexity and storage consumption, and restricts its deployment on resource-constrained embedded edge devices. To reduce the computing requirements and storage occupancy of the neural network model, we proposed the ensemble binarized DroNet (EBDN) model, which implemented the reconstructed DroNet with the binarized and ensemble learning method, so that the model size of DroNet was effectively compressed, and ensemble learning method was used to overcome the defect of the poor performance of the low-precision network. Compared to the original DroNet, EBDN saves more than 7 times of memory footprint with similar model accuracy. Meanwhile, we also proposed a novel and high-efficiency hardware architecture to realize the EBDN on the chip (EBDNoC) system, which perfectly realizes the mapping of an algorithm model to hardware architecture. Compared to other solutions, the proposed architecture achieves about 10.21 GOP/s/kLUTs resource efficiency and 208.1 GOP/s/W energy efficiency, while also providing a good trade-off between model performance and resource utilization.

An FPGA-Based Four-Channel 128k-Point FFT Processor Suitable for Spaceborne SAR

Spaceborne synthetic aperture radar (SAR) plays an important role in many fields of national defense and the national economy, and the Fast Fourier Transform (FFT) processor is an important part of the spaceborne real-time SAR imaging system. How to meet the increasing demand for ultra-large-scale data processing and to reduce the scale of the hardware platform while ensuring real-time processing is a major problem for real-time processing of on-orbit SAR. To solve this problem, in this study, we propose a 128k-point fixed-point FFT processor based on Field-Programmable Gate Array (FPGA) with a four-channel Single-path Delay Feedback (SDF) structure. First, we combine the radix-23 and mixed-radix algorithms to propose a four-channel processor structure, to achieve high efficiency hardware resources and high real-time performance. Secondly, we adopt the SDF structure combined with the radix-23 algorithm to achieve efficient use of storage resources. Third, we propose a word length adjustment strategy to ensure the accuracy of calculations. The experimental results show that the relative error between the processor and the MATLAB calculation result is maintained at about 10−4, which has good calculation accuracy.

Evaluation of semi-frozen semi-fixed neural network for efficient computer vision inference

Deep neural networks have been utilized in an increasing number of computer vision tasks, demonstrating superior performance. Much research has been focused on making deep networks more suitable for efficient hardware implementation, for low-power and low-latency real-time applications. In [1], Isikdogan et al. introduced a deep neural network design that provides an effective trade-off between flexibility and hardware efficiency. The proposed solution consists of fixed-topology hardware blocks, with partially frozen/partially trainable weights, that can be configured into a full network. Initial results in a few computer vision tasks were presented in [1]. In this paper, we further evaluate this network design by applying it to several additional computer vision use cases and comparing it to other hardware-friendly networks. The experimental results presented here show that the proposed semi-fixed semi-frozen design achieves competitive performanc on a variety of benchmarks, while maintaining very high hardware efficiency.