High Dielectric Breakdown Field Research Articles

BaTiO3-based lead-free relaxor ferroelectric ceramics for high energy storage

Barium titanate (BaTiO3, BT) is widely used in capacitors because of its excellent dielectric properties. However, owing to its high remanent polarisation (Pr) and low dielectric breakdown field strength (Eb), achievement of high energy storage performance is challenging. Herein, a systematic strategy was proposed to reduce Pr and elevate Eb of BT via: (i) modification of the relaxor behavior by alloying it with Bi(Mg2/3Ta1/3)O3 (BMT) and (ii) heightening Eb by introducing NaTaO3 (NT) with high band gap. Consequently, the energy storage efficiency (η) of 90 % and high Eb of 780 kV cm−1 were achieved simultaneously for the BT-BMT-xNT system, which facilitated the recoverable energy density (Wrec) of 6.02 J cm−3. At 300 kV cm−1, its temperature (20–120 °C) and frequency (1–500 Hz) stabilities were found to be good. Moreover, the BT-BMT-0.15NT possessed ultrafast discharge rate (t0.9 < 51 ns) and ultrahigh power density (PD > 94 MW cm−3). This study offers an effective strategy for the design of novel high-performance dielectric energy storage materials.

Influence of Chemical Cleaning Procedures and Thermal Oxidation Processes on the Uniformity of MOS Gate Oxides on Abrupt Steps on Silicon Surfaces

This work analyzes the influence of some chemical steps used in standard cleaning recipes on the surface micro-roughness of silicon wafers. The effect of varying the ammonium hydroxide concentration in the NH4OH: H2O2:H2O solution was studied and silicon wafer micro-roughness was characterized by atomic force microscopy technique at different scans of 1µmx1µm. Based on the results, it was possible to point the condition to obtain low surface micro-roughness for NH4OH-based solutions with the lowest NH4OH content before the growth of gate oxides. Following, it silicon-oxide thin films were grown onto periodic rectangular shapes, 100 nm in height, obtained by localized plasma etching on silicon wafer surfaces. Silicon oxides (SiO2), about 4.5 nm thick, were grown in ultrapure dry-O2 or pyrogenic (O2 + H2) environments in order to compare the planar uniformity and the grade of coverage at the step edges of rectangular shapes defined onto silicon surfaces. Pyrogenic and conventional oxidation at 850 oC allowed one to obtain gate oxides on 100 nm-stepped silicon surfaces with high dielectric breakdown field (&gt;10 MV/cm), good planar uniformity and conformal coverage at the step edges. The impact of this result is now the feasibility of fabricating good-quality gate oxides for surrounding gate transistors (SGT’s) and texturized MOS solar cells.

SiO2/GaN interfaces with low defect densities and high breakdown electric fields formed by plasma-enhanced atomic layer deposition

We present SiO2/GaN interfaces with a low interface state density and a high breakdown electric field. The SiO2 films were deposited by plasma-enhanced atomic layer deposition (ALD) using bis(diethylamino)silane and O2 plasma at 300 °C on n-type GaN (0001) homoepitaxial layers. An interface state density of less than 1011 cm−2 eV−1 at 0.3 eV below the conduction band edge was confirmed by the conductance method. The value is much lower than those of previously reported ALD-SiO2/GaN interfaces (1012–1013 cm−2 eV−1). A low fixed charge density at the SiO2/GaN interface of 3.7 1011 cm−2 and a high dielectric breakdown field of ~10 MV cm–1 were obtained. Moreover, the interface state density and current−voltage characteristics were further improved by post-deposition annealing at 400 °C in N2 ambient. Scanning transmission electron microscopy with energy-dispersive X-ray analysis revealed the existence of a GaO x interlayer between SiO2 and GaN. The unintentionally formed interlayer could be one of the reasons for the improvement of interface properties at ALD-SiO2/GaN.

Characterization of MOCVD-grown AlSiO gate dielectric on β-Ga2O3 (001)

The interface and bulk properties of aluminum-silicon-oxide (AlSiO) dielectric grown by metal-organic chemical vapor deposition (MOCVD) on (001) β-Ga2O3 were investigated systematically using a deep UV-assisted capacitance–voltage methodology. The improved surface preparation with a combination of UV-ozone and wet chemical treatment reduced near-interface traps resulting in a negligible hysteresis. An average interface state density of 6.63 × 1011 cm−2 eV−1 and AlSiO bulk trap density of 4.65 × 1017 cm−3 eV−1 were quantified, which is half of that for Al2O3 deposited by atomic layer deposition (ALD). A net positive interface fixed charge of 1.56 × 1012 cm−2 was measured. In addition, a high dielectric breakdown field of ∼7.8 MV/cm and more effective suppression of gate leakage were achieved on these devices compared with ALD-Al2O3 on similar metal-oxide-semiconductor (MOS) structures.

Energy storage performance of BaTiO3-based relaxor ferroelectric ceramics prepared through a two-step process

As the industrial pillar of electronic ceramics, BaTiO3 ceramic is difficult to achieve large energy storing performance due to its high Pr and low dielectric breakdown field strength, making it difficult to satisfy their development requirements of miniaturization and lightweight of power electronic equipment. Therefore, a two-step strategy including adjusting the ratio of chemical elements to modify the microstructures and optimizing the preparation process to enhance electric breakdown strength has been proposed to greatly enhance the energy storing performance of lead-free ferroelectric ceramics, whose effectiveness has been proved within this investigation. Especially, the (Ba0.65Sr0.245Bi0.07)0.99Nd0.01TiO3 (BT-SBT-NdVPP) ceramic prepared by this strategy obtains a superhigh energy storage density of 4.2 J/cm3 under 460 kV/cm, and its temperature (30 ~ 100 °C) and frequency (10 ~ 400 Hz) stabilities under 300 kV/cm are pretty good. In addition, this ceramic has excellent pulse performance under 350 kV/cm between 30 and 150 °C. Therefore, this two-step strategy put forward within this investigation not only significantly improves the energy storage performance of BT-based ceramics but also provides a reference for the preparation of dielectric ceramics with high quality, which could has great potential for the practical industrial application.

Time-stable giant energy density and high efficiency in lead free (Ce,Mn)-modified (Na0.8K0.2)0.5Bi0.5TiO3 ceramic film capacitor

The current urgent desire of the renewable energy has imposed much challenge and inspiration for the design and development of the lead-free dielectric capacitors. High recoverable energy storage density (Wrec) and efficiency (η) associated with long-time stability are highly demanded for the pulsed power systems. Here, we present a significantly enhanced energy storage performance in (Ce,Mn) hybrid doped (Na0.8K0.2)0.5Bi0.5TiO3–BiFeO3 [(Ce,Mn):NKBT-BFO] ceramic film capacitor deposited on indium tin oxide (ITO)/glass substrate. Meanwhile, the pure NKBT-BFO, Ce doped NKBT-BFO and Mn doped NKBT-BFO are studied for comparison. A large Wrec of 58.3 J/cm3 together with a high η of 58.1% is realized in (Ce,Mn):NKBT-BFO at 2200 kV/cm, which is proposed by the formation of a slim loop with a large difference between the remanent polarization (Pr) and maximum polarization (Pmax) at a high dielectric breakdown field strength. Moreover, the energy storage property is weakly dependent on time with small variations of Wrec (<23.4%) and η (<11.3%) over a long time range of 2 days–6 months. These results indicate that the (Ce,Mn)-codoped NKBT-BFO ceramic thin film has great potential for the applications in lead-free energy storage film capacitors.

Effect of Zr Substitution for Ti on BaZrxTi1−XO3 Thin Films for Energy Storage Applications

Recently, energy storage capacitors research attention turned towards lead-free and eco-friendly dielectric BaTiO3. Many efforts have been made to improve the dielectric properties of the BTO thin film capacitors. Barium titanate is one of the most studied ferroelectric materials because they possess high permittivity, polarization and piezoelectric properties, low dielectric loss and high dielectric breakdown field and it is very attractive for many applications. With this motivation, highly oriented thin films of BaZrxTi1−xO3 (BZT) with different concentrations of Zr were fabricated on LSMO/MgO(100) substrates to compare their energy storage performances while varying Zr concentration in Pt/BZT/LSMO/MgO(100) heterostructures. Deposition of BZT layers were done at an oxygen partial pressure of ∼150 mTorr. During laser ablation of BZT at a laser energy 250 mJ on the target, substrate temperature was maintained at 650 °C using an excimer laser operating at a pulse frequency of 10 Hz. Thickness of the thin films was precisely maintained by controlling the number of laser shots. These thin films was analyzed by x-ray diffractometry and Raman spectroscopy. Studies on structural phase transition, ferroelectric, dielectric, leakage current, and energy-storage properties revealed the applicability of these thin film structures in future integrated high energy density capacitors. We will present the aforementioned properties of these thin films and will discuss the intended energy storage applications of this dielectric material in detail.

Thermal Stability of Quasi-Two-Dimensional β-Ga2O3 and Its Device Application

An ultra-wide bandgap of around 4.8-4.9 eV (at room temperature), high thermal and chemical stabilities are some of the attractive properties of β-gallium oxide (β-Ga2O3) for fabricating (opto)electronics. Its noticeably high dielectric breakdown field (Ebr) also has drawn attention; the theoretical value was calculated to be ~8 MV/cm and a recent report reached an experimental value of 3.8 MV/cm, which is higher than those of GaN and SiC. These advantages obviously led to various applications on power devices including metal-semiconductor field-effect transistors (MESFETs), metal-oxide-semiconductor field-effect transistors (MOSFETs) and Schottky barrier diodes. Mechanically exfoliated β-Ga2O3 flakes were studied in our investigation. The mechanical exfoliation of β-Ga2O3 is possible although it is not formed by van der Waals interaction as its monoclinic structure allows cleavage into thin flakes along [100] direction. This new possibility of preparing β-Ga2O3 samples not only suggests that β-Ga2O3 can possess two-dimensional (2D) properties, but also offer a solution for low thermal conductivity of β-Ga2O3, which is a critical limitation when fabricating high power devices. Since it is only recently that mechanically exfoliated β-Ga2O3 gained attention, there still exists several characteristics to be investigated. Unlike bulk substrates, quasi-2D β-Ga2O3 needs more research on stability to be applied to devices such as sensors and high-power electronics that operate at high temperature. In this study, the thermal stability of β-Ga2O3 flakes was observed over time and the means to improve the stability were investigated. The optical and structural changes with time were measured as the samples were exposed to higher temperature (200 – 400 °C). MESFETs were also fabricated using β-Ga2O3 flake as the channel material to investigate the thermal effects on the device, especially the Schottky barrier between the channel and the gate metal. Different metals and an additional thermally conductive 2D layer was used to enhance the thermal stability of the device. This study shows the potential of quasi-2D material (β-Ga2O3) devices with long term stability at high temperature. Further results and discussion will be presented in detail.

Chemical vapor deposited monolayer MoS2 top-gate MOSFET with atomic-layer-deposited ZrO2 as gate dielectric

For the first time, ZrO2 dielectric deposition on pristine monolayer MoS2 by atomic layer deposition (ALD) is demonstrated and ZrO2/MoS2 top-gate MOSFETs have been fabricated. ALD ZrO2 overcoat, like other high-k oxides such as HfO2 and Al2O3, was shown to enhance the MoS2 channel mobility. As a result, an on/off current ratio of over 107, a subthreshold slope of 276 mV dec−1, and a field-effect electron mobility of 12.1 cm2 V−1 s−1 have been achieved. The maximum drain current of the MOSFET with a top-gate length of 4 μm and a source/drain spacing of 9 μm is measured to be 1.4 μA μm−1 at VDS = 5 V. The gate leakage current is below 10−2 A cm−2 under a gate bias of 10 V. A high dielectric breakdown field of 4.9 MV cm−1 is obtained. Gate hysteresis and frequency-dependent capacitance–voltage measurements were also performed to characterize the ZrO2/MoS2 interface quality, which yielded an interface state density of ∼3 × 1012 cm−2 eV−1.

Direct Wafer Bonding of SiC-SiC at Room Temperature by SAB Method

The efficiency improvement of power devices is of significance because the energy saving and prevention of global warming are urgent issues. However, it is difficult to realize further improvement by using the conventional silicon (Si) because of its limited physical properties. Silicon carbide (SiC) has attracted considerable attention owing to its superior properties such as wider band gap, higher dielectric breakdown field, higher thermal conductivity, higher stability in a harsh environment, and so on [1-3]. With successive breakthroughs in aspects of material technology and device fabrication such as 6-inch 4H-SiC wafer being and various devices becoming commercially available, SiC power devices will be widely used in the foreseeable future [4]. As a result, the fabrication and integration technologies of SiC power device in mass production will be very important. Wafer bonding is a widely used technology for device fabrication and integration, while studies about directly wafer bonding of SiC-SiC at low temperature are still hardly. Therefore, directly wafer bonding of SiC-SiC at room temperature by SAB method was investigated in this work. In the directly wafer bonding process, the two SiC wafers surfaces were firstly activated by argon fast-atom-beam (Ar-FAB), followed by directly contacted in UHV bonding chamber under a certain pressure. After bonding, a scanning acoustic microscopy (SAM) was used to inspect the voids of the bonded wafer, followed by blade insertion method to test the bonding strength. In addition, the bonding interfaces were analyzed by high-resolution transmission electron microscopy (HR-TEM) and energy-dispersive X-ray spectroscopy (EDX). References M. B. J. Wijesundara, and R. G. Azevedo, Silicon carbide microsystems for harsh environments (Springer, New York, 2011), pp. 15.Y. Hijikata, Physics and Technology of Silicon Carbide Devices, (InTech, Rijeka, 2012) pp. 181.T. Kimoto, Symp. VLSI Technology, 2010, p. 9.H. Okumura, MRS. Bull. 40, 439 (2015).

Quantum transport and spin properties of the carriers in Ⅲ-nitride heterostructures

Owing to their advantages of wide direct-band gap, excellent physical and chemical stability, high saturated electron drift velocity, and high dielectric breakdown field, Ⅲ-nitride semiconductor materials are the most favorite materials in developing high-frequency, high-temperature and high-power electronic devices and optical devices. Owing to their advantages of long spin relaxation time and high Curie temperature, Ⅲ-nitride semiconductor materials are the most favorite materials in developing spintronic devices. The magnetotransport methods at low temperatures and the circular photogalvanic effect at room temperature are introduced. The research status of the quantum transport and spin properties of the carriers in GaN-based heterostructures is reviewed.

Effects of annealing time on the electrical properties of the Y2O3 gate on silicon

Effects of post-deposition annealing time (15, 30, and 45 minutes) have been studied on a Y2O3 film sputtered on a Si substrate. A negative flatband voltage shift was observed in a forward bias direction, indicating the presence of positive charges in all samples. The highest dielectric breakdown field and lowest leakage current density were obtained by a sample annealed for 45 minutes, attributed to the acquisition of the lowest effective oxide charge, interface trap density, total interface trap density, and highest barrier height. It was believed that the formation of Y2Si2O7 and/or SiO2 interfacial layers has contributed to the above-mentioned observation.

Effect of Postdeposition Annealing in Oxygen Ambient on Gallium-Nitride-Based MOS Capacitors With Cerium Oxide Gate

This paper presents the effects of postdeposition annealing temperatures (400, 600, 800, and 1000°C) in oxygen ambient on the metal-organic decomposed CeO2 films spin coated on an n-type GaN substrate. The compositions, structures, and morphologies of these samples are revealed by X-ray diffraction (XRD), field-emission scanning electron microscopy, and an atomic force microscope. XRD analysis discloses the presence of CeO2 films, α-Ce2O3, and an interfacial layer of β-Ga2O3. The formation of α-Ce2O3 is due to the phase transformation of CeO2, whereas the β-Ga2O3 interfacial layer is formed due to the inward diffusion of the released oxygen from CeO2 reacting with decomposed GaN. These characterization results are then correlated with the metal-oxide-semiconductor characteristics of the CeO2 gate annealed at different temperatures. It has been demonstrated that oxide annealed at 1000°C shows the lowest semiconductor-oxide interface-trap density, effective oxide charge, and the highest dielectric breakdown field.

Investigation of forming-gas annealed CeO2 thin film on GaN

The effects of post-deposition annealing temperatures (400, 600, 800, and 1,000°C) in forming gas (95% N2 + 5% H2) ambient on metal–organic decomposed cerium oxide (CeO2) thin films deposited on n-type GaN substrate had been investigated. The occurrence of CeO2 phase transformation was reported and presence of CeO2, α-Ce2O3, and β-Ga2O3 had been detected, depending on the annealing temperature. As the annealing temperature increased, grain size and microstrains of CeO2 films were, respectively, increased and reduced. Metal–oxide–semiconductor characteristics of the annealed samples were systematically investigated. The highest dielectric breakdown field was perceived by sample annealed at 400°C due to the reduction of semiconductor–oxide interface trap density and effective oxide charge.

Metal-oxide–semiconductor characteristics of thermally grown nitrided SiO 2 thin film on 4H-SiC in various N 2O ambient

Metal-oxide–semiconductor characteristics of thermally grown nitrided SiO 2 (9–11.5 nm) on n-type 4H-SiC at 1175 °C in various N 2O ambient (1, 10, and 50% N 2O mixed with 99, 90, and 50% of high purity N 2 gas, respectively) have been investigated. The chemical composition of oxide–semiconductor interface has been evaluated by X-ray photoelectron spectroscopy. The interfacial layer consists of either silicon oxynitride, silicon nitride, and/or silicon oxide phases that may be segregated or mixed in a single layer. Depending on the percentage of N 2O being used, the stoichiometry may vary accordingly. The lowest leakage current density is recorded for thin film oxide grown in10% N 2O and it is limited to an applied electric field of not more than 7 MV/cm. This is attributed to the lowest density value of deep oxide trap in this sample if compared with others. The highest dielectric breakdown field has been obtained for thin film oxide grown in 50% N 2O as this sample is having the lowest interface trap density and negative effective oxide charge. The origin of these charges is explained in the text.

Characteristics and Reliability of Hafnium Oxide Dielectric Stacks With Room Temperature Grown Interfacial Anodic Oxide

Hafnium oxide dielectric stacks with anodic oxide interfacial layer (ANO-IL) were investigated under low-temperature consideration. A tilted-substrate sputtering technique, which provides various film thicknesses in one processing step, was proposed and useful for the characterization of charge distribution. It was found that charges existed in the HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /ANO-IL were smaller than that in HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /rapid-thermal-oxidation IL. The prepared samples exhibit good electrical characteristics, including small electrical hysteresis (< 10 mV), low leakage current, high effective dielectric breakdown field of 12.7 MV/cm, and maximum operating voltages of -2.74 V at 25degC and -2.32 V at 125degC for EOT = 2.3 nm stacks under a ten-year lifetime evaluation. The results suggest that the quality of IL in the dielectric stack is a critical reliability issue and that ANO is provided as a candidate for IL consideration of low-temperature dielectric stacks.

Process improvement of 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection

Once fab develops a reliable integration scheme, the next step of process improvement and yield enhancement is very important for semiconductor industry, especially for the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection. In this paper, we discuss the process integration issues of the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene integration. Solutions to the issues were explored and reported. Resist poisoning issue was solved by modifying photoresist and planarizing bottom-anti-reflective-coating (BARC) scheme. As a result there is an increase of 20% electrical yield. The impact of via etch time on interface of via bottom was studied and etch time was optimized for the best electrical performance of via chains. One of major targets of the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene integration is the reliability improvement. It was observed that Cu cap etch results in different via chain profiles. Good profile of via chain is achieved after optimizing of Cu cap etch and via etch. The failure open rate of via chain and the highest dielectric breakdown field were also reported. The impacts of dual damascene cleaning on the reliability of the 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection was studied with splits between batch process and single wafer cleaning. On the whole, we successfully integrated 0.13 μm Cu/Low K (Black Diamond TM) dual damascene interconnection with good electrical and reliability performance after process improvement of patterning, via/Cu cap etch and dual damascene cleaning.

Gate oxideprepared by nanometre silicon wet oxidation at low temperature for Si/SiGe PMOSFET application

A high-quality thin gate oxidefor application in Si/SiGe heterostructure PMOSFETs is prepared bynanometre silicon wet oxidation at 750 °C by taking full advantage of the peculiar phase in polysilicon thermal oxidation. Thecombination of low temperature and a short processing time prevents strain relaxation and Ge outdiffusion in the compressivelystrained SiGe channel. Its structural stability and interfacequality are studied by x-ray double-crystal diffraction.Results of C-V characteristics and breakdown measurementsindicate that the gate oxide exhibits a low fixed oxide charge density and a high dielectric breakdown field. Employing this gateoxide, Si/SiGe PMOSFETs with good output characteristics havebeen successfully fabricated.

Characteristics of polysilicon oxides combining N/sub 2/O nitridation and CMP processes

This paper present a high-quality polysilicon oxide combining N/sub 2/O nitridation and chemical mechanical polishing (CMP) processes. Experimental results indicate that polyoxide grown on the CMP sample exhibits a lower leakage current, higher dielectric breakdown field, higher electron barrier height, less electron trapping rate, higher charge-to-breakdown (Q/sub bd/), and lower density of trapping charge than those of non-CMP samples. In addition, the CMP process enhances nitrogen incorporation at the interface by the N/sub 2/O nitridation, ultimately improving the polyoxide quality. However, the CMP process smooths the surface of polysilicon and this planar surface reduces the out-diffusion of the phosphorous during thermal oxidation.

Characterization of polysilicon oxides thermally grown and deposited on the polished polysilicon films

This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Q/sub bd/) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide.