High-voltage MOS Devices Research Articles

60 V tolerance full symmetrical switch for battery monitor IC**Project supported by the National Natural Science Foundation of China (No. 61334003).

For stacked battery monitoring IC high speed and high precision voltage acquisition requirements, this paper introduces a kind of symmetrical type high voltage switch circuit. This kind of switch circuit uses the voltage following structure, which eliminates the leakage path of input signals. At the same time, this circuit adopts a high speed charge pump structure, in any case the input signal voltage is higher than the supply voltage, it can fast and accurately turn on high voltage MOS devices, and convert the battery voltage to an analog to digital converter. The proposed high voltage full symmetry switch has been implemented in a 0.18 μm BCD process; simulated and measured results show that the proposed switch can always work properly regardless of the polarity of the voltage difference between the input signal ports and an input signal higher than the power supply.

Part I: High-Voltage MOS Device Design for Improved Static and RF Performance

In this paper, for the first time, the key design parameters of a shallow trench isolation-based drain-extended MOS transistor are discussed for RF power applications in advanced CMOS technologies. The tradeoff between various dc and RF figures of merit (FoMs) is carefully studied using well-calibrated TCAD simulations. This detailed physical insight is used to optimize the dc and RF behavior, and our work also provides a design window for the improvement of dc as well as RF FoMs, without affecting the breakdown voltage. An improvement of 50% in $R_{\mathrm{{\scriptscriptstyle ON}}}$ and 45% in RF gain is achieved at 1 GHz. Large-signal time-domain analysis is done to explore the output power capability of the device.

Impacts of the Drain-side nWell Adding on ESD Robustness in 0.25-μm LV/HV nMOSTs

An n-channel MOS transistor (nMOST) no matter what low or high voltage processes are often used in I/O pads as ESD protection components. However, the contact spiking is a common caused leakage problems which deeply affect the ESD reliability capability of protection devices. Therefore, in this work, we proposed systematic experiments on the drain side: by adding an n-type Well (nWell) structure in the drain area for 0.25-μm low voltage (LV)/ high voltage (HV) processes. After measurement and analysis, it is found that for this LV process adding the nWell in drain side is bad for the It2 robustness of ESD capability, such as the lowest ESD capability condition (S= 9-μm) as compared with the reference group (none with the nWell) is decreased up to 42%, so in the ESD protection application should be avoided to add this structure; in the same token adding the nWell structure in the drain side of an HV nLDMOS, it was found that can expand an ESD current conduction cross-sectional area, which will not dissipate a lot of heat on the surface of the device led to burn, and then enhancing the ESD capability. Meanwhile, the ESD capability of a DUT with S= 9-μm as compared with the reference group (none with the nWell) is increased up to 8%, so adding an nWell structure in the drain side is good for ESD capability (It2 value) of HV MOS devices.

Modelling technique for high-voltage MOS devices with BSIM3v3

A new technique is presented for modelling high-holtage (HV) MOS devices accurately with the BSIM3v3 SPICE model. Physical meanings different from those of the original BSIM3v3 are assigned to some parameters but without changing its model equations; this method can be applied to any SPICE simulator on which the BSIM3v3 model runs.

Design and characterization of submicron BiCMOS compatible high-voltage NMOS and PMOS devices

This paper investigates the feasibility of integrating high-voltage blocking capability into a state-of-the-art submicron BiCMOS process using existing processing steps. High-voltage MOS devices fully compatible with an existing 5 V, 0.8 /spl mu/m BiCMOS process have been designed and studied through extensive two-dimensional (2-D) process and device simulations. The device layout parameters in proposed high-voltage NMOS (HV-NMOS) and high-voltage PMOS (HV-PMOS) devices are optimized to achieve highest performance possible in terms of breakdown voltage and specific on-resistance with the constraints of full process compatibility. The optimized HV-NMOS and HV-PMOS devices using minimized unit-cell pitches of 7.8 and 7.3 /spl mu/m achieved breakdown voltages of 129 V and specific on-resistances of 0.9 and 11.5 mn cm/sup 2/, respectively. Due to their full compatibility with the existing process the high-voltage MOS devices presented in this paper can be implemented without increasing manufacturing cost. The integration of the high-voltage blocking capability into the submicron BiCMOS process can expand its application field to include high-voltage input and output (I/O) functions on the same chip with high-speed analog and high-density digital signal processing circuitry.

Process and device design of a 1000-V MOS IC

High-voltage MOS devices and logic N-MOS circuits have been integrated on the same chip by using a silicon-gate isoplanar process that is compatible with present N-MOS LSI technology. The electrical characteristics of high-voltage MOS devices are modeled and characterized in terms of channel length, drift-layer length, drift-layer ion dose, and extended source field-plate effect. The theoretical calculations of on-resistanee, saturation drain current, and pinchoff voltage agree well with the experimental results. Based on the experimental and theoretical results, the device structure and the process parameters are optimized to obtain maximum drain saturation current with a low on-resistance and a drain breakdown of 1000 V. The optimized high-voltage MOS device can perform with a saturation drain current as high as 84 mA with an on-resistance as low as 300 Ω within an area of 520 µm × 1320 µm while maintaining a drain breakdown of 1000 V.