High-voltage IC Research Articles

Integrated MOSFET Inverter Module for Low-Power Drive System

This paper introduces a new MOSFET inverter module for driving small brushless dc motors used in fans and water-pump applications. The proposed power module integrates six MOSFETs and three dedicated gate-driving high-voltage integrated circuits (HVICs) in a transfer-molded full-pack package. It provides optimized loss and epoxy molding compound characteristics by using particularly designed MOSFET and dedicated HVIC. This paper describes the package design, the MOSFET, and the HVIC of the proposed module used in motor-drive applications, where power dissipation, electromagnetic interference, and noise immunity are primary concerns.

Robustness of Self-Isolation High-Voltage Integrated Circuits against the Voltage Surge during Conductivity Modulation Delay in Free-Wheeling Diode

In this paper, we report on the robustness of self-isolation high-voltage integrated circuits (HVICs) against a voltage surge during a conductivity modulation delay in a free-wheeling diode (FWD) for the first time. Two types of voltage surge that have a negative voltage against the ground potential are applied to HVICs simultaneously in the conventional switching mode. The voltage surge activates parasitic bipolar transistors that may destroy the HVICs. In this study, the operation of parasitic bipolar transistors induced by the surge and the suppression of the action of these transistors were investigated, and the robustness of the self-isolation 1200 V HVICs against surge was verified experimentally.

Complete System for Wireless Powering and Remote Control of Electrostatic Actuators by Inductive Coupling

This paper proposes a successful asynchronous remote powering and control of electrostatic microactuators, organized in two distributed micro motion systems (DMMS) with the aim of realizing a wireless microrobot. Remote powering of the integrated circuit (IC) and the microelectromechanical systems (MEMS) components is obtained by inductive coupling at 13.56 MHz, and the digital transmission is created by modulating the carrier amplitude by 25%. The system includes a high-voltage controller IC. It provides a link between the power and data on the receiver antenna on one side, and the actuators of the microrobot on the other. The micromachined antenna is designed to optimize the inductive coupling. The main IC building blocks, such as the received signal rectifier/amplifier, the integrated digital processing and the DMMS actuation voltage generation are given in detail. The demonstrator has successfully achieved the remote control and asynchronous operation under 100 V of two arrays of 1700 electrostatic actuators, having a capacity of 2 nF each

High-voltage power IC technology with nVDMOS, RESURF pLDMOS, and novel level-shift circuit for PDP scan-driver IC

A novel high-voltage (HV) CMOS IC technology using 25-/spl mu/m-thick epitaxy layer based on 1.2-/spl mu/m standard CMOS process for color plasma display panel (PDP) scan-driver ICs has been developed. In this technology, HV n-channel vertical double diffused MOS (nVDMOS), reduced surface field p-channel lateral double diffused MOS (pLDMOS), and the low-voltage CMOS (LVCMOS) are integrated together. The p/sup +/n junction isolation is used to isolate nVDMOS from the pLDMOS, LVCMOS, and other nVDMOSs. A novel level-shift circuit has also been suggested in the PDP scan-driver IC. The experimental results show that the breakdown voltages of the presented nVDMOS and pLDMOS both exceed 200V whether in the OFF or ON state. The rise and fall times of the proposed PDP scan-driver IC are about 270 and 50ns, respectively, which are two important performances to the high response speed of PDPs. The power consumption of the proposed PDP scan-driver IC with the novel level shift circuit has been reduced by about 20% compared with that of the PDP scan-driver IC with the conventional level shift circuit. Furthermore, the cost can be greatly saved using the presented bulk-silicon fabrication technology compared with the silicon-on-insulator technology.

Experimental and Numerical Studies on dV/dt Robustness of 1200 V High-Voltage Integrated Circuits Using Self-Isolation Structure

Experimental results on the high-voltage level shifter and dV/dt robustness of 1200 V high voltage integrated circuits (HVICs) using a self-isolation (SI) structure are reported for the first time. Generally, because high dV/dt stress is applied to HVICs during insulated gate bipolar transistor (IGBT) switching, significant displacement current flows through a high-voltage isolation capacitance. This current acts as the base current of parasitic pnp and npn transistors, and causes a potential drop in their base region. In the worst case, this parasitic operation causes device destruction. In this study, not only the normal operation of HVICs but suppression of the parasitic transistors under high dV/dt condition are experimentally demonstrated by considering a high-side layout design and back diverter electrode.

Method of dissipating heat generated in high-voltage CMOS driver IC

A method of dissipating the heat generated in a high-voltage CMOS driver IC, which is designed for use with a flat panel display, is proposed. It utilises a charge pump circuit to reduce the voltage across the driver IC when its output stages change their status. It can reduce the power consumption and relieve the thermal problems of driver ICs.

World in motion

Household appliances can contribute significantly to global energy savings. The latest motor drives promise full-scale conversion from electromechanical to variable speed electronic motor control. An integrated design platform can also simplify a design by integrating more of the digital, analogue, high voltage IC and also making use of recently developed control algorithms.

Double Snapback Characteristics in High-Voltage nMOSFETs and the Impact to On-Chip ESD Protection Design

The double snapback characteristic in the high-voltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.

Investigation of A 450 V Rating Silicon-On-Insulator Lateral-Double-Diffused-Metal–Oxide– Semiconductor Fabrication by 12/25/5/40 V Bipolar-Complementary Metal–Oxide–Semiconductor Double-Diffused Metal–Oxide–Semiconductor Process on Bulk Silicon Substrate

In this study, traditional bipolar-complementary metal oxide semiconductor (CMOS)-double diffused metal oxide semiconductor (DMOS) (BCD) technology, which is designed for only lateral bipolar (Bipolar, 12 V BVCEO and 25 V BVCBO), complementary metal oxide semiconductor (CMOS, 1.2 V threshold voltage) and double diffused metal oxide semiconductor (DMOS, 40 V breakdown voltage) transistors on the bulk silicon wafer, has been successfully utilized directly in silicon on insulator lateral double diffused metal oxide semiconductor (SOI LDMOS) for the first time without changing any trial parameters. To simultaneously display the characteristics of high-power, high-speed and high-frequency, the results of output characteristics, switch and microwave performance must be moderate instead of optimum. In addition, according to the experimental results, it is proved that Bulk-BCD technology simultaneously enables high-speed, high-frequency and high-blocking-voltage applications–such as those in high-voltage integrated circuit switches (ns-range) and RF power amplifiers (MHz range to GHz range)–using a SOI wafer.

Dual gate lateral inversion layer emitter transistor for power and high voltage integrated circuits

The Dual Gate Lateral Inversion Layer Emitter Transistor (DGLILET) is a versatile device with controlled carrier injection and ultra fast switching capability. The DGLILET has an improved trade off between the on-state and turn off losses enabling the performance of High Voltage Integrated Circuits (HVICs) to be enhanced by reducing overall losses at switching frequencies over approximately 10 kHz. This paper focuses on the use of the DGLILET in these applications and demonstrates experimental results of the fabricated devices confirming the enhanced performance.

Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product

Latchup failure induced by electrostatic discharge (ESD) protection circuits occurred anomalously in a high-voltage IC product. Latchup issues existed at only three output pins, two of which belonged to the top and the other to the side. The layouts of top and bottom output pins are identical, and side output pins have another identical layouts. In our experiments it was found latchup of two top output pins were originated from the latchup of the side output pin, and therefore heat-induced latchup aggravation issue must be noticed during latchup test. Furthermore, large power line current (Idd) existed during triggering this side output pin and led to subsequent latchup. After thorough layout inspection, the layout of this side output pin is identical to all other side output pins except that it has an additional N-well (NW) resistor of gate-triggered high-voltage PMOS beside. It was later proved by engineering experiments that this NW resistor is the origin of inducing latchup in this product, and a new mechanism was proposed for this latchup failure. Improvements and solutions were also provided to successfully solve the latchup issues of these three output pins.

Design and optimization of double-resurf high-voltage lateral devices for a manufacturable process

A simple method for determining the optimal charge balance and processing window of double-reduced surface field (RESURF) lateral devices is presented. The technique is based on the use of simple two test structures that are widely used in ICs, no special test structures are required. The optimal processing window is determined from the bounds over which RESURF is maintainable, and hence, high breakdown voltage is achievable. Using the technique, device designers can set and choose the process conditions of the device's critical layers to yield a manufacturable process prior to actual device layout, and therefore preserves the ability for layout design optimization independent of process optimization. The proposed technique also maximizes the benefits of double-RESURF processing for achieving the lowest on-resistance while maintaining the desired breakdown voltage. Using the technique, the process design and optimization guidelines for a double-RESURF LDMOS built in a high voltage IC technology are discussed and supported with experimental results.

DC Modeling of Lateral High-Voltage MOSFETs for High-Voltage Integrated Circuits

We have developed a physically based circuit-model of lateral high-voltage MOSFETs for design optimization of high-voltage integrated circuits (HVICs). The carrier density and the potential distribution in the channel surface and in the drift region depend on the structure of HV MOSFETs, such as the drift region and the field plate, and the voltage applied to the gate, the field plate, and the n drain. The developed DC model is comprised of five carrier-transport equations, one for the channel region and four for the drift region, which are the drift region overlapped with the gate, the drift region with a cylindrical junction, the drift region under the field plate, and the drift region without the field plate. The developed model is applicable to LDMOSFETs and EDMOSFETs, and the simulations with the model agree with the measurements for SOI EDMOSFETs within a tolerance of 3 %.

Automotive HID headlamps producing compact electronic ballasts using power ICs

Incandescent halogen lamps have been the standard for automotive headlamps; however, metal halide high-intensity discharge (HID) lamps have slowly begun to be commercially used since the mid-1990s. The lighting system of the metal halide HID headlamp makes a great contribution to energy savings, longer lamp life and better visibility in traffic zones compared with halogen lamps. (Lamp life is lengthened because it prevents the loss of sodium metal as plus ions through the quartz of the lamp bulb.) This article describes power ICs consisting of full bridge inverters and their drivers in detail. Market requirements for electronic ballasts include more compact size, lighter weight, and lower cost. On the other hand, lamp manufacturers recommend that automotive metal halide HID lamps should be operated at negative voltage potential to the body of automotive headlight fixture in order to lengthen lamp life. In order to meet these requirements, a new multichip power integrated circuit (IC) for electronic ballast of automotive HID headlamps has been developed. Discrete power metal-oxide-semiconductor field-effect transistors (MOSFETs) are used for the inverter of the HID electronic ballast. It contains a high-voltage driver IC including a P-channel lateral double diffused MOSFET (LDMOS) to control the full bridge power MOSFETs.

High-voltage power integrated circuit technology using SOI for driving plasma display panels

A new high-voltage (HV) power IC technology using high-performance p-LDMOS transistors and an excellent dielectric isolation technology has been proposed to apply the scan driver of color plasma display panel (C-PDP) system. This novel technique reduces over 40 process steps and results in smaller chip size area of the developed scan driver than that of conventional driver using conventional power IC technology. The chip size and the rise time of the PDP scan driver IC developed by this technology could be reduced by 35% and 60%, respectively, compared with the conventional design.

High-Voltage SOI Power IC Technology with non-RESURF n-LDMOSFET and RESURF p-LDMOSFET for PDP Scan-Driver Applications

mCMOS on a single chip was developed to apply to PDP scan-driver ICs. The developed power IC technique can reduce production cost and increase the process margin compared with conventional technique. The breakdown voltages of n- and p-LDMOSFETs were larger than 250 V, and their specic on-resistances were 50 m cm 2 and 140 m cm 2 , respectively. The PDP scan-driver IC fabricated by the proposed power IC technology showed good operation up to 250 V. The rising and the falling times of the PDP scan-driver IC were less than 110 nsec under Vdd=200 V and CL=100 pF.

Plugging the global power leak

Standby mode is a convenient but extremely wasteful feature of many electronics products. The authors describe how the GreenChip family is helping to produce a more environmentally friendly switched mode power supply. The new ICs implement an extensive set of power management functions focused on improving the efficiency of the standard flyback supply in standby mode. They achieve this by introducing three special modes of operation, referred to as burst-mode, off-mode and low-frequency mode. Use of GreenChip devices can typically reduce standby power to 2-3 W, and for a slight increase in cost this can be brought down to less than 500 mW. Along with these green features, the ICs have been designed to simplify the design task and reduce the component count, thereby addressing environmental concerns while reducing overall product costs. A new development in high-voltage IC technology based on a thin-layer silicon-on-insulator (SOI) process has been announced by Philips Semiconductors. This technology, known as EZ-HV-SOI, is expected to allow significant improvements and enhancements in the next generation of GreenChip controllers.

A novel insulation technique for smart power switching devices and very high voltage ICs above 10 kV

In this paper we will present a new CMOS compatible integration technique which will allow an integration of smart power switching devices and HV ICs with operating voltages above 10 kV. With an improved etching technique on standard silicon wafers all devices (low voltage and high voltage) can be integrated in the same silicon substrate at the same time. Since yet other researchers have integrated HV ICs in SOI films or in high resistive material with maximum blocking voltages of 1400 V so far [1]. High voltage switching devices are only available with switching currents above several amperes on a large device area. Measurements of our monolithicaly integrated low current HV devices with blocking voltages of more than 10 kV on a small chip area of about 45 mm 2 will be presented.

1200 V fully implanted JI technology

A novel 1200 V fully implanted junction isolation technology for high voltage integrated circuits (HVICs) is proposed. This technique employs the variation in lateral doping (VLD) technique to achieve change in the thickness as well as the concentration of the drift region in a lateral power device to enable effective distribution of the electric field and low on-state resistance. Detailed 2D numerical simulations clearly validate this new approach and show enhancement performance of a lateral MOSFET in comparison to a device with a uniformly doped drift region.

Application of a Semi‐insulating Amorphous Hydrogenated Silicon Nitride Film as a Resistive Field Shield and Its Reliability

In order to develop reliable high voltage integrated circuits (HVICs), the characteristics of semi‐insulating plasma‐deposited amorphous silicon nitride (a‐SiN:H) films as resistive field shields, are examined, the reliability of their application to HVICs are studied. The surfaces of these semi‐insulating films were unstable, and it was concluded that these films must be covered with a final passivation film such as an insulating plasma‐deposited a‐SiN:H film. The transverse electrical conduction mechanism of these films is briefly discussed.