High-voltage Electrostatic Discharge Protection Research Articles

Enhanced asymmetric DDSCR with high robustness for high-voltage ESD protection

ABSTRACT This paper proposes an enhanced asymmetric dual directional silicon controlled rectifier (EADDSCR) for the applications of bidirectional electrostatic discharge (ESD) protection. The ADDSCR and EADDSCR were prepared in a 0.18 µm Bipolar CMOS DMOS (BCD) process and measured with the transmission line pulsing tester. By adding N+ injection regions in the cathode and anode, a new vertical SCR path is formed in EADDSCR, so that the failure current of EADDSCR can reach twice as much as that of ADDSCR with only a small increase in the area of EADDSCR. Moreover, the FoM of EADDSCR can be increased to more than 81.19 µA/µm. Finally, the improved device possesses a smaller on resistance and is more suitable for high-voltage circuit applications.

An electronically programmable Off-State breakdown voltage in LDMOS transistor with dual-dummy-gate for high voltage ESD protection

A simulation study of the Off-State breakdown characteristics for a dual-dummy-gate SOI-LDMOS transistor is presented. The proposed device is a modification of a bulk-LDMOS transistor with a single dummy gate and two different diffused layers in the drift region. It introduces two additional dummy gates in the drift region, apart from the gate and extended drain electrode in the conventional device. The dummy gates need to be optimally biased to maximise the breakdown (VBR) and snapback voltages. 1D model modifying the 2D Poisson's equation has been proposed to analyse the 2D phenomena arising due to the perpendicular electric field originating from the dummy gate and extended-drain voltages and optimize the two dummy-gates bias. This approach provides an analytical solution for the Off-State VBR under the depletion condition. The model is verified with the TCAD simulations. The simulation results provide an insight into the electric field, potential distributions, and carrier concentrations in the drift region that characterizes the device performance. The impact ionization and current density contours are also included. It is found that the introduction of the two dummy gates enhances the maximum achievable VBR while it eliminates the need to have two different diffused regions that necessitate additional masks. Also, the proposed device has an intrinsic structural advantage of the reduced gate to drain capacitance due to the shielding effect of dummy gates. As the performance of the proposed device is controlled externally by the applied dummy gate voltage, the VBR is user programmable as per the requirement in electrostatic discharge (ESD) protection circuits for a sub-100 V application.

A Dual-MOS-Triggered Silicon-Controlled Rectifier for High-Voltage ESD Protection

A dual-MOS-triggered silicon-controlled rectifier (DMTSCR) has been firstly developed for high-voltage (HV) electrostatic discharge (ESD) protection. Compared to the reported SCRs with modified structures, the DMTSCR harvests a series of advantages such as a high holding voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> ), a strong ESD robustness, and a low <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{t1}$ </tex-math></inline-formula> , thanks to its embedded structures including a gate-to-VDD PMOS, a gate-grounded NMOS, and a modified SCR. Thus, the DMTSCR has the largest figure of merit as high as 1.8 mA/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula> . By further optimizing the layout and the key spacing between the embedded PMOS and NMOS of DMTSCR, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> increased from 8.4 to 17.4 V, the turn-on resistance remarkably decreased to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.4~\Omega $ </tex-math></inline-formula> , and the turn-on voltage was clamped at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{h}$ </tex-math></inline-formula> . The optimized DMTSCR with a small chip area possesses an ESD robustness of 3000 V evaluated by the human body model. Meanwhile, the operation mechanism simulated by Sentaurus exhibited good agreements with the theoretical circuit analysis, and the simulated electrical characteristics were consistent with those measured from the experimental devices. The layout-optimized DMTSCR with good clamping ability and zero snapback voltage is a promising solution for stacking to meet various HV ESD protection requirements.

Design of a cascade-MOS-triggered SCR with high holding-voltage for high-voltage ESD protection

A parallel-MOS-triggered silicon-controlled rectifier (PMTSCR) is firstly proposed and verified in a 0.25-μm Bipolar-CMOS-DMOS process, aiming to prevent the latch-up effect of SCR in the electrostatic discharge (ESD) protection. Comparing to the conventional SCR, the trigger voltage (Vt1) of the PMTSCR decreases because of the effect of PMOS embedded in the N-well, and the holding voltage (Vh) increases because of the attribution of the NMOS embedded in the P-well. By shortening the SCR current conduction path and designing a special metal connection, the modified-PMTSCR (M-PMTSCR) is obtained. The failure current of the M-PMTSCR remarkably increases from 1.8 to 4.8 A. However, M-PMTSCR exhibits a lower Vh and a higher Vt1. By further optimizing the location and connection of the embedded PMOS and NMOS, the obtained cascade-MOS-triggered SCR (CMTSCR) possesses a high Vh of 8.4 V and a strong ESD robustness of 6000 V in a small chip area. Meanwhile, the operation mechanism simulated by Sentaurus was consistent with the theoretical circuit analysis and transmission line pulse measurements. Thus the proposed CMTSCR with the good latch up immunity and temperature stability is a promising device to meet the requirements of high voltage ESD protection.

Drain-Extended FinFET With Embedded SCR (DeFinFET-SCR) for High-Voltage ESD Protection and Self-Protected Designs

This article presents device design insights and design challenges for drain-extended FinFET devices with embedded silicon-controlled rectifier (SCR) (DeFinFET-SCR), which can be used as an electrostatic discharge (ESD) protection device and a self-protected high-voltage switch/driver for system-on-chip applications. The tradeoff between maximizing ESD robustness without hindering the transistor’s operation is discussed in detail. An interplay between parasitic p-n-p turn-on and space charge modulation (SCM) is revealed, which strongly influences the strength of parasitic SCR and its turn-on efficiency during ESD and DC operations. Developed physical insights show that engineering p-n-p turn-on and onset of SCM are the key to maximize ESD robustness without causing early SCR turn-on during transistor operation. Based on new findings and developed physical insights, design guidelines have been derived for ESD robust DeFinFET-SCR.

Design of a Gate Diode Triggered SCR for Dual-Direction High-Voltage ESD Protection

A novel gate diode triggered silicon-controlled rectifier (GDTSCR) with dual-direction high-voltage (HV) electrostatic discharge (ESD) protection and a low snap-back voltage is proposed and investigated. Compared to conventional MOS triggered SCR (MTSCR), the GDTSCR has two gate diodes and one additional n-p-n. Superior to the MTSCR, the GDTSCR exhibits a high holding voltage of 15 V, a small trigger voltage of 17 V, and a strong ESD robustness of 6000 V in an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1600~\mu \text{m}^{\textsf {2}}$ </tex-math></inline-formula> , benefitting from the gate-controlled field effect diodes and the weakened regenerative feedback of the SCR. As such, the proposed GDTSCR is an attractive device for constructing effective and latch-up immune solutions for HV ESD protection.

A New High Holding Voltage Dual-Direction SCR With Optimized Segmented Topology

While silicon controlled rectifiers (SCRs) are highly robust electrostatic discharge (ESD) protection devices, they typically are not suited for high-voltage ESD protection due to their inherently low holding voltage and thus vulnerability to latch-up threat. In this letter, a new high holding voltage dual-direction SCR (NHHVDDSCR) with a small area and optimized topology is developed in a 0.18- $\mu \text{m}$ CMOS technology. The results of the NHHVDDSCR and other SCR devices measured from the transmission line pulsing are compared and discussed. It is shown that the NHHVDDSCR can possess a relatively high and adjustable holding voltage, as well as an acceptable failure current for robust ESD protection of high voltage applications.

Design and optimization of LDMOS-SCR devices with improved ESD protection performance

The lateral diffusion metal-oxide semiconductor embedded silicon controlled rectifier (LDMOS-SCR) devices with optimized structures and layouts for improving the electrostatic discharge (ESD) protection ability have been proposed. The devices are designed and fabricated in 0.25-μm, 0.35-μm and 0.5-μm Bipolar-CMOS-DMOS processes. Firstly, by designing an appropriate stripe resistance in series with the source of the LDMOS-SCR, the holding voltage of the proposed high resistance LDMOS-SCR (HRLDMOS-SCR) increases. Secondly, by inserting a floating Zener-diode into the LDMOS-SCR, the trigger voltage of the modified Zener-diode triggered LDMOS-SCR (ZTLDMOS-SCR) decreases. Finally, the ZTLDMOS-SCR is further optimized by using a ring layout and incorporating a square source resistance, resulting in a significantly improved figure of merit in comparison to traditional LDMOS-SCR devices. The optimized ZTLDMOS-SCR devices are very attractive for constructing effective and latch-up immune high voltage ESD protection solutions in power integrated circuits.

Investigation on LDMOS-SCR with high holding current for high voltage ESD protection

We investigate a novel lateral diffused metal-oxide semiconductor (LDMOS) device embedded in silicon controlled rectifier (SCR) and resistance-capacitance circuit (LDMOS-SCR-RC). The internal RC-coupling effect helps to increase the holding current (Ih), resulting in the enhanced latch-up immunity of electrostatic discharge (ESD) protection device in high voltage integrated circuits (HV ICs). Transmission line pulse testing results show that the proposed LDMOS-SCR-RC has the largest Ih and smallest trigger voltage (Vt1), comparing to the conventional LDMOS-SCR and LDMOS-SCR embedded a resistance. When key parameters such as the gate-length and resistance are optimized, the Ih increases further from 1.1A to 1.5A, while the Vt1 changes insignificantly. The detailed internal mechanism of LDMOS-SCR-RC with regard to key parameters is analyzed numerically by the SENTAURUS simulation. Results confirm that the increased Ih is mainly due to the enhanced RC-coupling effect. Finally, DC measurements conducted with a semiconductor curve tracer also confirm that the LDMOS-SCR-RC with small device area is effective for avoiding latch-up risks. The optimized LDMOS-SCR-RC provides a useful latch-up immune ESD protection solution for HV ICs input/output ports.

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

A novel substrate trigger semiconductor control rectifier-laterally diffused metal–oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal–oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

Robust dual-direction SCR with low trigger voltage, tunable holding voltage for high-voltage ESD protection

An LDNMOS-based and an LDPMOS-based dual direction silicon controlled rectifier (DDSCR) devices have been designed and fabricated in a 0.5-μm 5V/18V high voltage (HV) CDMOS process. These devices can be used to protect pins with a voltage range that goes above and below the ground by discharging electrostatic current in both positive and negative directions. A 2-dimension (2D) device simulation and a transmission line pulse (TLP) measurement were used to predict and characterize the ESD performance of the two DDSCR devices. Compared to LDNMOS-based DDSCR, LDPMOS-based DDSCR is excellent for its relatively low trigger voltage of 33V and strong electrostatic discharge (ESD) current handling capability of 87mA/μm. Furthermore, the holding voltage of LDPMOS-based DDSCR can be elevated by tuning layout parameter. Such a device has been applied to I/O bus terminals of a data interface circuit for its on-chip ESD protection.

Novel Capacitance Coupling Complementary Dual-Direction SCR for High-Voltage ESD

A novel capacitance coupling complementary dual-direction silicon-controlled rectifier (SCR) (CCCDSCR) for high-voltage electrostatic discharge protection is proposed and verified in 0.5-μm BCD process. The trigger voltage of CCCDSCR can be adjusted by coupling capacitance to meet different protection requirements. Compared with traditional lateral double-diffusion NMOS, LDSCR, stacked field-oxide device, and stacked low-voltage-triggering SCR devices, the CCCDSCR has appropriate low trigger voltage of 27.3 V, high holding voltage of 24.3 V, and highest figure of merit (FOM) according to our defined FOM.

PLDD/NHALO-assisted low-trigger SCR for high-voltage tolerant ESD protection in foundry CMOS process without extra mask

A new semiconductor-controlled rectifier (SCR) is proposed and realised in the foundry 0.18 µm CMOS process for electrostatic discharge (ESD) protection. Without using an extra mask or trigger circuits, the new p-type lightly-doped-drain and n-type halo (NHALO) assisted SCR has a trigger voltage as low as 7 V and an ESD robustness exceeding 50 mA/µm to provide an effective protection. Compared with traditional LVTSCR, the new structure not only has a lower trigger voltage, but can also be more suitable for high-voltage tolerant applications without the gate-oxide reliability issue.