High-voltage Devices Research Articles

Design and Fabrication of Non-Uniform Spacing Multiple Floating Field Limiting Rings for 6500V 4H-SiC JBS Diodes

Designed for 6500V 4H-SiC JBS diodes, a highly-efficient termination structure of a non-uniform multiple floating field limiting rings (MFFLR) featuring with a non-uniform ring spacing and a multiple region division is studied and purposed. For each region, ring spacing is modulated independently by a multiplication factor and a linear increment factor. The non-uniform MFFLR structure is simulated and optimized for a better electric field distribution and a higher breakdown voltage. Based on the simulation results, 4H-SiC JBS diodes with the optimized non-uniform termination designs are fabricated. Experimental results show that the SiC JBS diode with optimized non-uniform MFFLR termination structure can achieve a breakdown voltage of up to 7800 V, and its termination efficiency is about 94% of an ideal parallel-plane junction’s. Our results demonstrate that the optimized non-uniform MFFLR termination structure is capable for SiC JBS diodes with breakdown voltage of 6500V and above. Our results can provide a valuable design methodology of edge termination structures for other high-voltage SiC devices.

Identification of internal stresses may improve transistor fabrication in high-voltage components

Experimental observation of internal stresses produced during deep trench fabrication in high-voltage devices indicates ways to optimize the manufacturing process.

Costs and quality of care optimization in the remote monitoring of cardiac implantable electronic devices (CIEDs). A picture from Veneto, Northern Italy

Abstract Background Remote control/monitoring (RC/M) of cardiac implantable electronic devices (CIEDs) is still underutilized, with a significant heterogeneity of use across and within countries. Not all models are equivalent in terms of effectiveness and efficiency. Purpose This cost comparative study aimed to analyse different models of following patients with CIEDs in three districts (four implanting facilities) merged into the same administrative area, to assess the impact of RC/M on expenditure, and to propose a common practice with the objectives of standardisation of approach, optimisation of efficiency, and future capillary implementation of RC/M. Methods The workload related to CIED-patient follow-ups was assessed in four public hospitals reflecting three different models with different proportions of patients followed by RC/M and different modus operandi. All CIED-patients in charge were scrutinized at 31/08/2019. The workload analysis was based on one-year data, collected retrospectively. Costs were calculated in terms of nursing and physician hours and based on public tariffs. Five variables, identified as drivers of costs, were tested by the simulation model. The main outcome was a total expenditure and cost per patient followed by RC/M compared to the standard care (SC) (in-office only). Results A total of 6830 patients with CIEDs were followed, 34.8% by RC/M (five platforms, 19.7% high voltage devices). An additional 25.8% had monitorable devices. The proportion of RC/M-patients across centres was 63.3%, 60.6%, 51% and 2.65%. RC/M resulted more costly than SC in all hospitals. Modelling demonstrated the overall cost in the year 2018 to be €228,075. No single factor optimisation tested separately (number of transmissions, nursing time for each transmission revision, doctor time for transmission processing, nursing time for phone calls, time for single enrolment) was able to reduce the cost per patient below the cost of SC. Providing monitoring to all compatible patients increased the costs of total care to €248,785. After the optimisation of other factors, the additional benefit of extending RC/M to compatible devices was achieved, with the final result of a total expenditure of €128,181 and of €15.97 per RC/M-patient per year vs. €27.93 per SC-patient, below the reimbursement tariff of monitoring recently approved in Veneto (€25.55 per patient/year). Conclusion Real-world data from an unselected population confirmed the huge inconsistency in managing patients with CIEDs. RC/M was associated with a significant specific workload. RC/M may be cost-saving compared to the standard in-office follow-up; however, organisation needs to be optimised. Improvement can be achieved by implementing new standards for RC/M procedures using Lean Management tools. A common platform might be of help. Centralisation could represent a further step to ensure high quality service and to save money at the same time. Funding Acknowledgement Type of funding source: None

Investigations of internal stresses in high-voltage devices with deep trenches

Deep trenches, as essential elements of silicon chips used in electronic high-power and high-frequency devices, are known as starting points for dislocation generation under the influence of internal mechanical stresses resulting mainly from the difference in the thermal expansion coefficients between silicon and silicon dioxide. Since the electrical insulation of the devices requires a sequence of mechanical, chemical, and high-temperature processes during the preparation of the deep trenches, including the formation of an amorphous SiO2 edge layer, the emergence of the internal stresses is hardly avoidable. The method of cross correlation backscattered electron diffraction in the scanning electron microscope is used here to quantitatively determine the magnitude and local distribution of internal stresses in silicon around the deep trenches after four different process steps. For this purpose, Kikuchi diffraction images are recorded of the wafer cross section areas along lines perpendicular and parallel to the deep trenches. After Fourier transformation, these images are cross correlated with the Fourier transform of the diffraction image from a stressfree reference sample site. The well-established numerical evaluation of cross correlation functions provides the complete distortion tensor for each measuring point of the line scan, from which the stress tensor can be calculated using Hooke's law. It is found that the in-plane normal stress component σ11 perpendicular to the long edges of the deep trench is larger than the other stress components. That means it essentially determines the magnitude of the von-Mises stress, which was determined as a general stress indicator for all measuring points, too. A characteristic feature is the local distribution of the stress component σ11 with maximum tensile stresses of some hundred megapascals at transition between Si and amorphous SiO2 on the long edges of the deep trench, and with even higher maximum compressive stresses immediately below the bottom of the deep trench. At a distance of about 2 μm from the edges of a single deep trench, all stress components decrease to negligibly small values so that steep stress gradients occur. The range and distribution of tensile and compressive stresses are in accordance with finite element simulations; however, the measured stresses are higher than expected for all investigated states so that dislocation formation seems to be possible. The influence of the electron acceleration voltage on the determination of the internal stresses is discussed as well.

A 115× Conversion-Ratio Thermoelectric Energy-Harvesting Battery Charger for the Internet of Things

This article presents a high-conversion-ratio (HCR), high-voltage-tolerant (HVT) energy-harvesting battery charger using 0.18-μm standard CMOS for Internet of Things (IoT). To reduce conversion ratio (CR) of inductive power converter and optimize overall power efficiency, the proposed charger cascades a boost converter and reconfigurable charge pump. Different from the high-voltage device, the standard CMOS process has lower parasitic capacitance and on-resistance; therefore, it can reduce switching and conduction loss. The reconfigurable charge pump dynamically changes the number of pumping stages according to the output voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> ) by automatic configuration selector (ACS). To manage the limited power from a thermoelectric generator (TEG), the converter works under the discontinuous conduction mode (DCM). The zero-current detector (ZCD) employs an analog comparator with digital offset compensator and digital comparator to control off-time (T <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> ) quickly and accurately. The self-idle constant on-time (SI-COT) and idle mode both control the mechanism, helping to further reduce static power dissipation. As a result, the proposed converter can achieve peak efficiency of up to 76% at a 92× conversion ratio with output power ranging from 10 μW to 1.9 mW. The available input voltage ranges are 40 to 400 mV, and the dual output voltage ranges are 1 to 1.6 V and 2 to 4.6 V for V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BOOST</sub> and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OUT</sub> , respectively.

A Highly Linear 10-Bit DAC of Data Driver IC Using Source Degeneration Load for Active Matrix Flat-Panel Displays

This brief proposes a highly linear digital-to-analog converter (DAC) of the data driver IC for active matrix flat-panel displays (AMFPDs). The proposed 10-bit two-stage DAC is realized with an upper 6-bit decoder and a lower 4-bit DAC-embedded amplifier. The decoder in the first stage selects two adjacent voltages from among the reference voltages of the R-string according to the upper 6-bit. The DAC-embedded amplifier in the second stage employs a source degeneration load to have the output current proportional to the input voltage, thus achieving the consistent transconductance of the input differential pairs, resulting in a high linearity. To verify the performance of the proposed DAC, a data driver IC with the proposed 10-bit DAC was fabricated using an 80 nm standard CMOS process with 8 V high-voltage devices. The measurement results show that the worst differential nonlinearity and integral nonlinearity are +0.26/-0.31 LSB and +0.57/-0.58 LSB, respectively. The measured worst inter-channel deviation of voltage outputs is 1.65 mV. Therefore, the proposed highly linear DAC is suitable for data driver ICs in high image quality AMFPD applications.

Improved Deep Trench Super-junction LDMOS Breakdown Voltage By Shielded Silicon-Insulator-Silicon Capacitor

Deep trench LDMOS is widely used in high-voltage level power devices. This paper proposes and optimizes a deep trench super-junction LDMOS with triangular charge compensation layer (TCCL DT SJ LDMOS), which solves the problem of charge imbalance in the super-junction region due to the Silicon-Insulator-Silicon (SIS) capacitance at both ends of the trench and improves the Breakdown Voltage (BV) of the device. This structure also helps to deplete the drift region at the bottom of the deep trench by adding P-buffer under the N-Pillars, which improves the doping concentration and reduces the specific on-resistance of the device. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the TCCL DT SJ LDMOS has been increased from 498V to 730V, and the power figure of merit (FOM) has increased by 12.8 MW / cm2(FOM = BV2 / Ron, sp).

Quantifying Dynamic On-State Resistance of GaN HEMTs for Power Converter Design via a Survey of Low and High Voltage Devices

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

Growth of α- and β-Ga2O3 epitaxial layers on sapphire substrates using liquid-injection MOCVD

Ga2O3, a wide-bandgap semiconductor material, offers a great potential for power and high-voltage electronic devices. We report on the growth of undoped α- and β-phase Ga2O3 using liquid-injection metal-organic chemical vapor deposition (LI-MOCVD) on sapphire substrates. Using the same precursor (gallium acetylacetonate) and deposition temperature of 700 °C, the phase selection was controlled by the sapphire substrate orientation, where the growth of α- and β-phase Ga2O3 was achieved on m- and c-plane surface, respectively. As deduced from x-ray diffraction, α-Ga2O3 films show epitaxial character, while β- Ga2O3 films exhibit highly textured structure. Oxygen flow was also found to have a strong impact on the phase purity of α-Ga2O3 for the flow rates examined. Optical and electrical properties of the layers grown at different oxygen flow rates were also studied systematically. LI-MOCVD growth of α-phase Ga2O3 layers at relatively high deposition temperature widens the high-temperature processing of the Ga2O3-based electronic and optoelectronic devices.

Accelerated Aging Stability of β-Ga2O3-Titanium/Gold Ohmic Interfaces.

Stable ohmic contacts are critical to enable efficient operation of high-voltage electronic devices using ultrawide bandgap semiconductors. Here we perform, for the first time, thermally accelerated aging of Ti/Au ohmic interfaces to (010) β-Ga2O3. We find that a heavily doped semiconductor, doped n-type by Si-ion implantation, treated with reactive ion etch (RIE), results in a low specific contact resistance of ∼10-5 Ω cm2 that is stable upon accelerated thermal aging at 300 °C for 108 h. The low resistance interface is due to thermionic field emission of electrons over an inhomogeneous barrier. Scanning/transmission electron microscopy indicates that the multi-layered structure and elemental distribution across the contact interface, formed during a 1 min 470 °C post-metallization anneal, do not change noticeably over the aging period. A ∼1 nm interfacial layer is observed by high-resolution microscopy at the Ti-TiOx/Ga2O3 interface on all samples exposed to RIE, which may contribute to their excellent stability. In addition, longer-range facet-like interfacial features are observed, which may contribute to the inhomogeneous barrier. In contrast, Ti/Au junctions to moderately doped (010) Ga2O3 made with no RIE treatment exhibit a high contact resistance that increases upon accelerated aging, along with a partially lattice-matched interface. The methods used here to understand the process, structure, and electrical property relationships for Ti/Au contact interfaces to β-Ga2O3 can be applied to assess and tune the stability of a variety of other oxide-semiconductor interfaces.

Design and optimization of asymmetric supercapacitors assembled by Platanus acerifolia seeds and ZIF-67 as precursors

Effective utilization of waste biomass has been a fascinating topic for the development of sustainable energy. An effective alkaline hydrothermal/pyrolysis process was designed to prepare highly porous carbons noted as HK-PSC800 using waste Platanus acerifolia seeds as precursors. A symmetric supercapacitor (SSC) device based the same two HK-PSC800 electrodes owns the high specific energy density (30.9 Wh kg−1 at a low power density of 500 W kg−1) with excellent rate capability. To further optimize the energy density of the device, two types of asymmetric supercapacitors (ASC) with a working potential window of 1.5 V are designed and assembled by using HK-PSC800 and Co3O4 derived from zeolitic imidazolate framework-67 as electrode materials. The specific energy density of as-fabricated ASC (Co3O4//HK-PSC800) with pure Co3O4 materials as the positive electrode is nearly the same as the SSC (HK-PSC800//HK-PSC800). However, the specific energy density of the other ASC (Co3O4@HK-PSC800//HK-PSC800) can be improved by 18.8% when 28 wt% Co3O4 is in-situ grown in HK-PSC800 as the positive electrode. This research proves that the suitable composition of ASC electrode materials helps us to develop biomass based carbons materials for application in the high-voltage and high-energy devices.

Thermal conductivity of rutile germanium dioxide

Power electronics seek to improve power conversion of devices by utilizing materials with a wide bandgap, high carrier mobility, and high thermal conductivity. Due to its wide bandgap of 4.5 eV, β-Ga2O3 has received much attention for high-voltage electronic device research. However, it suffers from inefficient thermal conduction that originates from its low-symmetry crystal structure. Rutile germanium oxide (r-GeO2) has been identified as an alternative ultra-wide-bandgap (4.68 eV) semiconductor with a predicted high electron mobility and ambipolar dopability; however, its thermal conductivity is unknown. Here, we characterize the thermal conductivity of r-GeO2 as a function of temperature by first-principles calculations, experimental synthesis, and thermal characterization. The calculations predict an anisotropic phonon-limited thermal conductivity for r-GeO2 of 37 W m−1 K−1 along the a direction and 58 W m−1 K−1 along the c direction at 300 K where the phonon-limited thermal conductivity predominantly occurs via the acoustic modes. Experimentally, we measured a value of 51 W m−1 K−1 at 300 K for hot-pressed, polycrystalline r-GeO2 pellets. The measured value is close to our directionally averaged theoretical value, and the temperature dependence of ∼1/T is also consistent with our theory prediction, indicating that thermal transport in our r-GeO2 samples at room temperature and above is governed by phonon scattering. Our results reveal that high-symmetry UWBG materials, such as r-GeO2, may be the key to efficient power electronics.

Developing 13-kV 4H-SiC MOSFETs: Significance of Implant Straggle, Channel Design, and MOS Process on Static Performance

13-kV 4H-SiC MOSFETs were successfully fabricated on a 125- $\mu \text{m}$ -thick epitaxial layer on 6-in, N+ SiC substrates. Both lateral and longitudinal straggles from the P-well implant were investigated to optimize the JFET width and thus to avoid channel pinching in the JFET region. Channel lengths and channel mobilities were varied to investigate the effect of channel portions in determining the ON-state resistance of the 13-kV MOSFETs. It was discovered that the low channel mobility limits the transconductance, such that the MOSFETs cannot offer full current at reasonable gate voltages ( ${V}_{\text {gs}} = \sim \,\,20$ V). Even in high voltage MOSFETs, it is essential to have a reasonably high channel mobility to reduce ON-state power loss. Therefore, channel design and process are also important aspects of high voltage devices. A superior blocking capability of 13.2 kV was demonstrated using a ring-based edge termination structure. It is important to note that the straggling effect due to ion implantations should also be taken into account when designing an edge termination structure. Static electrical characteristics, scanning electron microscope (SEM) imaging, secondary ion mass spectrometry (SIMS) analysis, and 2-D simulation of the 13-kV MOSFETs were employed to support this reasoning.

On-Chip Fully Integrated Field Emission Arrays for High-Voltage MEMS Applications

Vacuum-sealed fully integrated diode and triode field emission arrays based on Ti Spindt-type field emitters have been developed in a scalable, CMOS-compatible process directly on Si. Diode characterization in air demonstrates effective vacuum sealing and field emission conduction, with current drivability that scales with array size. Triode characterization in vacuum demonstrates gate-modulated field emission of the output current and highlights new effects observed in a fully integrated geometry with closely spaced electrodes. Demonstrating up to 200-V blocking voltage and similar magnitude punchthrough voltages, the arrays can be utilized as high-voltage devices in CMOS applications or with microelectromechanical systems (MEMS) technologies using post-CMOS MEMS integration techniques. Low-temperature measurements reveal areas of improvement for electrode isolation; combined with the use of improved cathode materials, these devices have the potential to be used in high-power applications.

Trap-Mediated Avalanche in Large-Area 1.2 kV Vertical GaN p-n Diodes

This work studies the avalanche characteristics of the 1.2 kV vertical GaN p-n diodes with implanted edge termination, based on quasi-static current-voltage ( I-V ) sweeps and unclamped inductive switching (UIS) tests. The UIS tests reveal a ~1.7 kV avalanche breakdown voltage ( $BV_{{\text {AVA}}}{)}$ , 51 A maximum avalanche current ( ${I}_{{\text {AVA}}}{)}$ , and 63 mJ maximum avalanche energy ( ${E}_{{\text {AVA}}}$ ). The ${I}_{{\text {AVA}}}$ and ${E}_{{\text {AVA}}}$ are the highest reported in high-voltage GaN power devices. A lower $BV_{{\text {AVA}}}$ is observed in the I-V curves and a trap mediated avalanche model is proposed to explain it. The $BV_{{\text {AVA}}}$ in I-V curves is believed to be induced by avalanche-assisted trap-filling in the edge termination region, while the $BV_{{\text {AVA}}}$ in the UIS test reflects the robust avalanche at the main p-n junction. These results provide important new insights on the avalanche breakdown in GaN devices and address some seemingly contrary observations of vertical GaN p-n diodes published recently.

Electromagnetic Disturbance Characteristics and Influence Factors of PETT Oscillation in High-Voltage IGBT Devices

Plasma extraction transit time (PETT) oscillation occurs when insulated gate bipolar transistor (IGBT) devices turn off, whose frequency can reach hundreds of MHz. This high-frequency oscillation can induce electromagnetic interference problems and may exceed relevant IEC limits for electromagnetic emission. As one of the electromagnetic disturbance sources from internal IGBT, the PETT oscillation has not attracted much attention in the electromagnetic compatibility (EMC) problems of application and development of high-voltage IGBT devices yet. In this article, the detailed characteristics of PETT oscillation, i.e., oscillation frequency, duration time, and oscillation peak, in high-voltage IGBT devices are systematically investigated by experiments. From the results, oscillation frequency increases with the increase of reverse voltage, whereas decreases with the increase of the temperature. Then, more complex dependencies of the PETT oscillation characteristics on IGBT's commutation conditions are presented. It is shown that its characteristics vary greatly under different reverse voltage, forward current, and temperature. The hazard of PETT oscillation to electronic components is discussed as well. PETT oscillation occurs during the turn-on process, which is first reported. Based on the experiment results, the EMC test related to PETT oscillation is suggested to be performed under different commutation conditions.

Modeling and Compensation for Dead-Time Effect in High Power IGBT/IGCT Converters with SHE-PWM Modulation

Research on applying selective harmonic elimination pulse width modulation (SHE-PWM) to high power converters has drawn tremendous interest, due to the advantages of low switching frequency and high output harmonic performance. In the fields of high power converters such as variable speed traction motor drives and static synchronous compensators (STATCOM), the adoption of high voltage but slow speed semiconductor devices, i.e., IGBT/IGCT, results in a longer dead time of several microseconds, which leads to a motor vibration in the former case or the distortion of grid current in the latter case. This paper analyzes in detail the mechanism of the dead-time effect on 3-level SHE-PWM with different operating conditions considered. For the first time, a general mathematical model describing the relationship between the dead time and harmonic distribution of SHE-PWM wave is established. Based on which an open-loop compensation method by inserting a margin time into the effective switching angles is proposed. Furthermore, a closed-loop controller that implements online adaptive adjustment of the margin time is designed in case of a variable frequency application. The effectiveness of the proposed method in different scenarios is verified through simulation results.

Polyethylene Oxide-Based Composites as Solid-State Polymer Electrolytes for Lithium Metal Batteries: A Mini Review.

Solid-state polymer electrolytes (SPEs) have great processing flexibility and electrode–electrolyte contact and have been employed as the promising electrolytes for lithium metal batteries. Among them, poly(ethylene oxide) (PEO)-based SPEs have attracted widespread attention because of easy synthesis, low mass density, good mechanical stability, low binding energy with lithium salts, and excellent mobility of charge carriers. In order to overcome the low room-temperature ionic conductivity and the poor thermodynamic stability in high-voltage devices (>4.2 V) of the PEO materials, composition modulations by incorporating PEO with inorganic and/or organic components have been designed, which could effectively enable the applications of PEO-based SPEs with widened electro-stable voltage ranges. In this mini review, we describe recent progresses of several kinds of PEO composite structures for SPEs, and we compare the synthesis strategies and properties of these SPEs in lithium batteries. Further developments and improvements of the PEO-based materials for building better rechargeable batteries are also discussed.

High-permittivity dielectric edge termination for vertical high voltage devices

A novel edge-termination concept using extreme permittivity dielectrics is proposed to effectively manage electric fields in vertical power-devices. This method is expected to be particularly significant for wide band-gap semiconductors, where field termination is a significant challenge due to material and process limitations. Detailed two-dimensional device simulation is used to prove the efficacy of this idea, and to demonstrate that peak electric fields are significantly reduced by this method. We also show an analytical model that gives an intuitive picture into the mechanism of high-permittivity dielectric field plate. Low process complexity and flexibility in the design of power devices can be achieved. We show that junction termination efficiency can be increased from 22.7% (no junction termination) and 50% (conventional field plate) to 73% (high-permittivity-terminated device).

Medium Voltage Soft-Switching DC/DC Converter With Series-Connected SiC MOSFETs

Nowadays, due to the growing demands of data centers, the traditional line frequency transformer based data center power distribution system (DC-PDS) is becoming bulky and inefficient. Although SST-based DC-PDS dramatically improves the system efficiency, the traditional multicell SST with input-series output-parallel architectures has limitations. Using high-voltage devices to develop single-cell SST improves system performance, however, its application is limited by high-voltage power devices. As an alternative solution, achieving high blocking voltage through the series connection of low-voltage devices brings several advantages. Nevertheless, the series connection brings about two main problems, namely the voltage imbalance among devices and the increment of switching loss. This article proposes a medium voltage series resonant converter (MVSRC) with series-connected SiC MOSFETs. By adding snubber capacitor to each SiC MOSFET and working at LLC resonant soft-switching mode, the voltage imbalance is reduced and switching loss is decreased. Due to snubber capacitors, there are differences between MVSRC and traditional LLC converter, hence the analytical model of MVSRC is established. Moreover, the voltage imbalance model is established and the voltage imbalance sensitivity is defined to guide the snubber parameter selections. Then, a design example of the 99% efficient 5-kV/400-V prototype is presented. Last, the experimental results show that the voltage imbalance is reduced effectively and the switching loss is decreased dramatically, verifying the validity of proposed methods and the accuracy of analysis.