High-voltage CMOS Research Articles

Image sensor for spectral‐domain optical coherence tomography on a chip

This Letter presents a global shutter image sensor based on PIN photodiodes intended to be used for optical coherence tomography (OCT) in the spectral domain, where the light is brought to the photodiodes via optical waveguides monolithically integrated on top of electronics in a photonic layer. Photodiodes are optimised to have the peak responsivity in the wavelength range between 800 and 900 nm, while the main features of electronics are high signal-to-noise ratio, high frame rate, low-power consumption and low noise. The sensor is designed using 0.35 µm high voltage CMOS and employing low doped epitaxial starting material in order to improve the detector efficiency by enabling fully depleted photodiodes and lowering the crosstalk. Image sensor parameters are obtained using the photon-transfer curve method and compared with commercial cameras for OCT.

Test results of ATLASPIX3 — A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is 2.0×2.1 cm2 with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of 150×50μm2 and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.

Self-Aging-Prognostic GaN-Based Switching Power Converter Using TJ -Independent Online Condition Monitoring and Proactive Temperature Frequency Scaling

To mitigate unique aging and failure challenges encountered in GaN technology, this article develops the techniques that reinforce the reliability of GaN power circuits. In particular, an online condition monitoring scheme is developed to prognose the current collapse induced aging and failures in GaN power switches, using the devices' dynamic on-resistance rDS_ON, as the real-time precursor. As rDS_ON is temperature-dependent in general, a gate-leakage based junction temperature TJ sensor is developed to assist in removing temperature effect from rDS_ON reading, achieving TJ-independent condition monitoring. To improve the device longevity, a proactive temperature frequency scaling scheme is implemented to balance the power circuit performance and reliability. To validate the design concepts, a power converter IC prototype was designed and fabricated using an 180 nm high-voltage CMOS process. With all e-mode GaN power switches, it operates at 10 MHz switching frequency with a flexible input supply voltage ranging from 5 to 40 V and delivers a maximum power of 6 W. Experimental results demonstrate that the TJ-independent online condition monitoring reduces the false monitoring rate by 19 times over a temperature range from 0 to 125 °C. Meanwhile, the temperature frequency scaling engine reduces the TJ of the GaN switches by up to 16 °C, while striving for an optimal operation between performance and thermal stress.

Measurement results on capacitively coupled particle detector with PHOTON readout chip

A sensor chip for a capacitively coupled pixel detector (CCPD53) has been designed and produced in a 180 nm high voltage CMOS (HVCMOS) technology on a high resistivity wafer with deep p-well option. Capacitively coupled pixel detectors are a simple and low-cost alternative to classical hybrid detectors. They rely on capacitive signal transmission between the sensor chip and the readout chip. A pixel detector with small pixel size can be made without small pitch bumps. The CCPD53 sensor chip contains a pixel matrix of 64 × 40 pixels, each 25 μm × 50 μm in size. The digital output signals of a group of 16 pixels are encoded and the 8-bit output is connected to signal transmission pads arranged with pitch of 50 μm. The pad geometry has been chosen in a way to fit the geometry of the pixel readout ASIC developed by RD53 collaboration at CERN. The PHOTON readout chip has been implemented in the UMC 180 nm CMOS technology. It allows counting and integration of charge signals. The chip consists of a matrix of 32 × 30 identical square pixels with 150 μm × 150 μm size. In this paper the sensor and the readout chip will be described and the measurement results presented.

Study of CMOS strip sensor for future silicon tracker

Monolithic silicon sensors developed with High-Voltage CMOS (HV-CMOS) processes have become highly attractive for charged particle tracking. Compared with the standard CMOS sensors, HV-CMOS sensors can provide larger and deeper depletion regions that lead to larger signals and faster charge collection. They can provide high position resolution, low material budget, high radiation hardness and low cost that are desirable for high performance tracking in harsh collision environment. Various studies have been conducted to explore the technology feasibility for the large-area tracking systems at future collider experiments.CHESS (CMOS HV/HR Evaluation for Strip Sensor) sensor series have been developed as an alternative solution to the conventional silicon micro-strip detectors for the ATLAS inner tracker upgrade. The first prototype (named CHESS1) was to evaluate the diode geometry and the in-pixel analog electronics. Obtained test results were used to optimize the second prototype (named CHESS2). CHESS2 was implemented with a full digital readout architecture and realized as a full reticle sized monolithic sensor. In this paper, the basic characteristics of the CHESS2 prototype sensors and their performance in response to different input signals are presented.

A Hybrid LED Driver With Improved Efficiency

A high-efficient hybrid light-emitting diode (LED) driver is introduced in this article. By combining the merits of conventional switching-converter-based and inductor-less driving solutions, the proposed topology fully utilizes the input power from the ac mains without causing considerable switching loss or excessive voltage stress. With the help of a small-size inductor and the hybrid scheme, the proposed driver automatically alternates between switching mode and linear mode as the rectified input voltage changes. In addition, the driver can be configured either in a single stage for a high power factor (PF) and high efficiency or in the second stage of a two-stage solution for alleviating harmful low-frequency flicker. The proposed driver-integrated circuit is implemented in a 0.35-μm high-voltage CMOS process and tested under 110-VAC 60-Hz input. Measurement results show that, when operating in the high PF configuration, the proposed driver achieves 95.1% power efficiency and 0.986 PF. For the low flicker configuration, it achieves 92% efficiency and 15% flicker while maintaining a 0.918 PF.

Fully integrated optical receiver using single-photon avalanche diodes in high-voltage CMOS

A monolithic optical receiver containing four single-photon avalanche diodes (SPADs) fabricated in 0.35-μm high-voltage (HV) CMOS is introduced and compared with two 4-SPAD receivers realized in pin-photodiode CMOS belonging to the same process family. This HV-CMOS SPAD receiver achieves sensitivities of −55.1 dBm at 50 Mbit / s and −52.0 dBm at 100 Mbit / s, both with digital processing, a bit error rate (BER) of 2 × 10 − 3, and return-to-zero coding using a wavelength of 642 nm. Also at 143 Mbit / s, this BER is achievable. This receiver is especially interesting for applications in which low light intensities can be expected, such as quantum key distribution, optical communications from deep space, and visible light communication for short-range consumer applications.

Low Flicker Dimmable Multichannel LED Driver With Matrix-Style DPWM and Precise Current Matching

A low flicker dimmable four-channel LED driver with precise current balancing is proposed in this paper. It is able to achieve highly linear dimming and low lighting flicker at the same time by utilizing a new matrix-style digital pulsewidth modulation (DPWM) along with LED string rotation. Only one LED string needs to be modulated to reduce the total LED current variation and switching loss. To avoid color shift and reduce the effect of subharmonic flicker, a fourth-order common centroid layout is applied to match the current-controlling MOSFETs for precise current balancing. Low-voltage and high-temperature protection circuits as well as a temperature-compensated relaxation oscillator are all integrated to complete the driver design and reduce the overall cost for practical applications. The chip is designed in a TSMC 0.25-μm 1P3M 60-V high-voltage CMOS process with a chip size of 1.76 × 1.37 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The current mismatch among LED strings is measured to be only ±0.28% along with four times reduction in lighting flicker.

PIN photodiode-based active pixel for a near-infrared imaging application in 0.35-μm CMOS

We present an active pixel for a spectral domain optical coherence tomography sensor on a chip, where optical components are realized in a photonic layer and monolithically integrated with the electronics, whereby light is brought to the pixels using waveguides. The core of the pixel is an amplifier with capacitive feedback (so-called capacitive transimpedance amplifier), apart from that, a correlated double sampling circuit is implemented within the pixel. The proposed active pixel is based on a PIN photodiode and fabricated in 0.35-μm high-voltage CMOS technology. We use three different epitaxial starting material thicknesses (20, 30, and 40 μm) in order to find the device with best performance. The pixel is optimized for high efficiency in a spectral range between 800 and 900 nm. We explain advantages in the spectral responsivity and crosstalk of this pixel over conventional p / n photodiode-based pixels in standard CMOS processes and over the pinned photodiode-based pixel. We also present measured pixel parameters and give comparison with prior work.

A high-efficiency charge pump with charge recycling scheme and finger boost capacitor

A 16-phase 8-branch charge pump with finger boost capacitor is proposed to increase the power efficiency and it is implemented in a 0.35 μm high-voltage CMOS IC technology. Compared with the standard capacitor, the finger capacitor can significantly reduce the parasitic capacitance. By combining the charge recycling method and the finger capacitor, the proposed four-stage charge pump can achieve an efficiency of 47.2% and an output voltage of 13.7 V from a 3 V power supply. The proposed charge pump also has better current driving ability and the area of the chip is 2.32 mm × 0.28 mm.

CACTUS: a depleted monolithic active timing sensor using a CMOS radiation hard technology

The planned luminosity increase at the Large Hadron Collider in the coming years has triggered interest in the use of the particles' time of arrival as additional information in specialized detectors to mitigate the impact of pile-up. The required time resolution is of the order of tens of picoseconds, with a spatial granularity of the order of 1 mm. A time measurement at this precision level will also be of interest beyond the LHC and beyond high energy particle physics. We present in this paper the first developments towards a radiation hard Depleted Monolithic Active Pixel Sensor (DMAPS), with high-resolution time measurement capability. The technology chosen is a standard high voltage CMOS process, in conjunction with a high resistivity detector material, which has already proven to efficiently detect particles in tracking applications after several hundred of Mrad of irradiation.

Siwa: A custom RISC-V based system on chip (SOC) for low power medical applications

This work introduces the development of Siwa, a RISC-V RV32I 32-bit based core, intended as a flexible control platform for highly integrated implantable biomedical applications, and implemented on a commercial 0.18 μm high voltage (HV) CMOS technology. Simulations show that Siwa can outperform commercial micro-controllers commonly used in the medical industry as control units for implantable devices, with energy requirements below the 50 pJ per clock cycle.

Development of 2T-SONOS Cell Using a Contamination-Free Process Integration for a Highly Reliable Code Storage eNVM

We report a low-cost and highly reliable 2T-SONOS embedded nonvolatile memory (eNVM) using a novel contamination-free process integration. The proposed 2T-SONOS cell is fabricated on a 90-nm high-voltage CMOS process for a touch screen controller embedded display driver IC applications. For a code storage purpose, eNVM with moderate memory density, simple integration, platform logic and process compatibility, and sufficient retention lifetime are critically important. Thanks to the contamination-free charge trap layer and optimized junction, we have achieved enough retention lifetime without using any special materials for the charge trap layer. The 120 °C data retention lifetime of over 10 years is verified using 77 $\times \,\,{3}$ samples of 32-kB memory density intellectual property. By correlating high-temperature retention bake results with technology computer-aided design simulations, we can understand long-term charge redistribution behavior inside trap nitride, which is significantly different from floating gate type NVM.

Highly Integrated Guidewire Ultrasound Imaging System-on-a-Chip.

In this article, we present a highly integrated guidewire ultrasound (US) imaging system-on-a-chip (GUISoC) for vascular imaging. The SoC consists of a 16-channel US transmitter (Tx) and receiver (Rx) electronics, on-chip power management IC (PMIC), and quadrature sampler. Using a synthetic aperture imaging algorithm, a Tx/Rx pair, connected to capacitive micromachined ultrasound transducers (CMUTs), can be activated at any time. The Tx generates acoustic waves by driving the CMUT, while the Rx picks up the echo signal and amplify it to be delivered through an interconnect that is driven by a buffer. On-chip logic controls the pulsers that generate the high-voltage (HV)-pulse for Tx. An on-chip PMIC provides 1.8-, 5-, 39-, and 44-V supplies and a clock signal from the two interconnects besides GND. A quadrature sampler down-converts the Rx echo signal to baseband, reducing its bandwidth requirement for the output interconnect. The system design, including transimpedance amplifier (TIA) optimization, based on the equivalent circuit of a specific CMUT is presented. The SoC was fabricated by a 0.18-μm HV CMOS process, occupying 1.5-mm2 active area and consuming 25.2 and 44 mW from 1.8 to 44 V supplies, respectively. The US Tx and Rx show bandwidths of 32-42 and 32.7-37.5 MHz, respectively. The input-referred noise of the system was measured as 9.66 nA in band with 2-m-long 52 American Wire Gauge (AWG) wire interconnects. The functionality of the GUISoC was verified in vitro by imaging wire targets.

RRAM-based non-volatile SRAM cell architectures for ultra-low-power applications

Static Random-Access Memories (SRAMs) have flourished in the memory market relying on their speed, power consumption and compatibility with standard CMOS process technology. Conventional SRAMs are characterized by volatility, limiting their role in applications where non-volatility is essential. Non-Volatile SRAMs (NVSRAMs) represent an appealing solution, where Resistive RAM (RRAM) can act as a non-volatile element for SRAM. RRAM relies on the basic physical phenomenon of operation called resistive switching. This paper presents different NVSRAM structures, while exploring their principle of operation. Also, a comparison in terms of area, speed, power consumption and design complexity is presented for three NVSRAM memory cells implemented in a 130-nm high voltage CMOS technology from STMicroelectronics.

High resolution 3D characterization of silicon detectors using a Two Photon Absorption Transient Current Technique

The Two Photon Absorption Transient Current Technique (TPA-TCT) is a tool to characterize semiconductor detectors using a spatially confined laser probe. Excess charge carriers are produced by the simultaneous absorption of two sub-bandgap photons in the material. The current induced by the motion of carriers is studied using well known TCT systems. Differently to standard TCT where the energy deposition (pair creation) is continuous along the beam, TPA-TCT reduces this region to an ellipsoidal volume, achieving thus, true 3D spatial resolution. This paper gives an overview of the technique and shows its performance in irradiated detectors, in particular diodes and High Voltage CMOS detectors.

A Continuous-Time Delta-Sigma Modulator Using a Modified Instrumentation Amplifier and Current Reuse DAC for Neural Recording

The use of continuous-time delta-sigma modulators (CTDSM) as a replacement of traditional analog sensor front ends has become an increasingly popular choice. The absence of traditional sensor interface circuits, such as instrumentation amplifiers (IAs), reduces area and power consumption at the cost of robustness offered by these circuits. Selection of the integrator type in the CTDSM is a selection of the ADC properties. This article presents a current feedback CTDSM with high input impedance, wide linear operating range, and large-signal common-mode rejection as a neural recorder front end. We propose the modification of an IA for operation as an integrator in a delta-sigma modulator and the current reuse of the feedback DAC current to bias this integrator stage. Deploying the current reuse technique, the total power consumption of the modulator is reduced by 22%. The ASIC is developed in a 180-nm high-voltage CMOS technology and the analog front end achieves a dynamic range of 90 dB and a total harmonic distortion (THD) of 0.005% when configured for a full-scale input signal of 208 mVpp. A common-mode rejection ratio (CMRR) of 90 dB is measured for a common-mode disturbance of 325 mVpp while the analog power consumption per channel is 23 $\mu \text{W}$ .

Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch

Abstract Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on 180nm high-voltage CMOS silicon was heterogeneously integrated with a single-pole four-terminal (SP4T) RF switch on 180nm CMOS silicon-on-insulator (SOI). The primary objective of this study was to determine the manufacturability of this System-in-Package (SiP) design, which is proven at time zero through survival of the MEMS device based on acceptable MEMS performance metrics. In addition, the RF SOI switch provides high-voltage electrostatic discharge (ESD) protection for the MEMS device. Capacitive MEMS structures are particularly sensitive to unpredictable electrostatic charging scenarios, such as handling after package assembly and printed circuit board (PCB) surface mount processing. Consequently, resistance to dielectric breakdown by means of robust ESD protection is a very desirable quality. Integrating the RF switch in close proximity with the MEMS device not only enables the ability to withstand charging scenarios in excess of 1kV (human body model), it mitigates the impact of parasitics on RF performance by minimizing interconnect lengths and complexity.

Performance of the ATLASPix1 pixel sensor prototype in ams aH18 CMOS technology for the ATLAS ITk upgrade

Monolithic active pixel sensors (MAPS) based on commercial high-voltage CMOS processes are an exciting technology that is considered as an option for the ATLAS Inner Tracker upgrade. Particles are detected using deep n-wells on a p-type substrate as sensor diodes with the depleted region extending into the silicon bulk. With readout electronics and sensor integrated on the same device, the detector complexity and the material budget are greatly reduced. The ATLASPix1 pixel sensor prototype is a large-scale MAPS prototype that implements the full readout chain on a single physical chip. It features a large in-pixel sensor electrode and is produced using the ams aH18 high voltage technology. Three pixel matrices with different readout architectures, triggered and untriggered, and pixel designs are implemented. We show the performance of one of the pixel matrix variants for samples irradiated up to 1015 1MeV meq/cm2.

A data acquisition system for HV-CMOS sensor research and development in the upgrade of ATLAS experiment.

In the high luminosity Large Hadron Collider upgrade of the A Toroidal LHC ApparatuS (ATLAS) experiment in 2026, the new inner tracker detector will be installed. As a promising candidate for the outer layer of the inner tracker detector, the High Voltage CMOS (HV-CMOS) pixel sensors are being investigated by the ATLAS collaboration. A Front-End LInk eXchange (FELIX) based Data Acquisition (DAQ) system is developed for the R&D of the HV-CMOS sensors. A FELIX card with a Peripheral Component Interconnect express interface in the back-end is used to control, monitor, calibrate, and read out the front-end electronics. In the front-end, a Xilinx evaluation board ZC706 works as the interface between the back-end and the custom boards with HV-CMOS sensors and the readout Application-Specific Integrated Circuit. The DAQ system was successfully deployed for the testbeam experiment at CERN. The design of the DAQ system, the tuning of sensors, and the testbeam results will be described in details.