High-throughput Implementation Research Articles

The use of sequential window acquisition of all theoretical fragment ion spectra (SWATH), a data-independent acquisition high-resolution mass spectrometry approach, in forensic toxicological regimes: A review.

Sequential window acquisition of all theoretical fragment ion spectra (SWATH) is a type of high-resolution mass spectrometry that uses data-independent acquisition. Compared with more targeted acquisition schemes, the power behind this data-independent acquisition technique comes from its ability to mitigate interferences via the use of SWATH acquisition windows (Q1 quadrupole isolation windows) while still obtaining all accurate mass information. However, consistent with high-resolution mass spectrometry techniques, its routine and high throughput implementation in forensic toxicology is limited due to the complex processing power required to effectively manage the large amount of acquired data. It is therefore pivotal to create an efficient and validated identification criterion that confidently reports suspected positive detections as a confirmational technique for final reporting. This review examines all publications that implemented SWATH in a forensic toxicological framework with suggestive best practices and commonly used criteria. Seventeen publications were reviewed for extraction, liquid chromatography and mass spectrometry parameters, and more specifically for all SWATH applicable characteristics including spray voltages, collision energies and spreads, mass error, isotopic ratio difference, retention time error, and library score thresholds. Notwithstanding the challenges SWATH implementation faces for a laboratory, the technique demonstrates its potential to be utilized in routine forensic toxicology testing regimes and aids in the detection of both common and emerging novel drugs simultaneously.

Abstract 6786: Assessment of immune cell infiltration and cancer metastatic potential in Akura™ Immune Flow Chip - A microfluidic 3D spheroid system

Abstract Evaluation of novel therapeutics often fails to reliably predict severe complications in patients, especially when circulating cells are involved. The reasons may include inter-species differences upon using animal models or the lack of relevant in vitro systems. Moreover, existing in vitro systems mostly rely on static investigations of different cell types leading to overestimation of effects due to non-representative cell-tissue interactions. The incorporation of medium flow may facilitate to mimic physiological conditions more closely. To tackle current limitations of perfused organ-on-chip approaches, we developed a microfluidic chip and operation concept, which prevents undesired sedimentation and accumulation of cells in suspensions. The Akura™ Immune Flow platform was designed to study flow-dependent recruitment of circulating cells to different tissue spheroids via gravity-driven perfusion over several days. The Akura™ Immune Flow platform features standardized formats for co-culturing up to seven spheroids with suspended cells in each microfluidic channel. On-chip staining protocols enabled monitoring of the co-culture. The system allowed for application and extractions of cellular components and liquid for further off-chip analysis. Primary tissue and cell line spheroids (liver and tumor) could be retained in the respective chambers and remained viable over six to 14 days. Circulating cells were kept viable and in suspension for up to six days (PBMCs) and14 days (Prostate Cancer (PCa) cells) respectively. PBMCs were not activated by flow-induced shear forces. Unspecific stimulation of T-cells led to physiological expression of early and late activation markers (CD69 and CD25), which were detected by flow cytometry in periodically collected cells. Multi-photon microscopy imaging confirmed that PBMCs interacted with and infiltrated into 3D tumor spheroids. Application of PCa cells to primary liver spheroids, cultured in Akura™ Immune Flow chips allowed for assessment of their invasive potential. Confocal imaging revealed adhesion of cancer cells to the liver spheroids and offers the potential to study the ability of tissue invasion at later time points. The simple design of the chip facilitates user-friendly operation and high-throughput implementation in cancer research and drug testing. The selected applications support the relevance of using flow solutions for physiologically more complex processes. This work constitutes an important step towards device application as a tool for basic research as well as for efficacy studies of immunotherapeutic drug candidates Citation Format: Tamara Häfeli, Silas Riss, Christian Lohasz, Dzhansu Hasanova, Svenja Lützow, Lisa Hölting, Michal Rudnik, Franziska Linke, Wytske M van Weerden, Laure-Anne Ligeon, Andreas Hierlemann, Mario Modena, Olivier Frey. Assessment of immune cell infiltration and cancer metastatic potential in Akura™ Immune Flow Chip - A microfluidic 3D spheroid system [abstract]. In: Proceedings of the American Association for Cancer Research Annual Meeting 2024; Part 1 (Regular Abstracts); 2024 Apr 5-10; San Diego, CA. Philadelphia (PA): AACR; Cancer Res 2024;84(6_Suppl):Abstract nr 6786.

High-Performance Hardware Implementation of the Saber Key Encapsulation Protocol

Information is pivotal in contemporary society, highlighting the necessity for a secure cryptographic system. The emergence of quantum algorithms and the swift advancement of specialized quantum computers will render traditional cryptography susceptible to quantum attacks in the foreseeable future. The lattice-based Saber key encapsulation protocol holds significant value in cryptographic research and practical applications. In this paper, we propose three types of polynomial multipliers for various application scenarios including lightweight Schoolbook multiplier, high-throughput multiplier based on the TMVP-Schoolbook algorithm and improved pipelined NTT multiplier. Other principal modules of Saber are designed encompassing the hash function module, sampling module and functional submodule. Based on our proposed multiplier, we implement the overall hardware circuits of the Saber key encapsulation protocol. Experimental results demonstrate that our overall hardware circuits have different advantages. Our lightweight implementation has minimal resource consumption. Our high-throughput implementation only needs 23.28 μs to complete the whole process, which is the fastest among the existing works. The throughput rate is 10,988 Kbps and the frequency is 416 MHz. Our hardware implementation based on the improved pipelined NTT multiplier achieved a good balance between area and performance. The overall frequency can reach 357 MHz.

Design and high-throughput implementation of MALDI-TOF/MS-based assays for Parkin E3 ligase activity

Parkinson's disease (PD) is a progressive neurological disorder that manifests clinically as alterations in movement as well as multiple non-motor symptoms including but not limited to cognitive and autonomic abnormalities. Loss-of-function mutations in the gene encoding the ubiquitin E3 ligase Parkin are causal for familial and juvenile PD. Among several therapeutic approaches being explored to treat or improve the prognosis of patients with PD, the use of small molecules able to reinstate or boost Parkin activity represents a potential pharmacological treatment strategy. A major barrier is the lack of high-throughput platforms for the robust and accurate quantification of Parkin activity invitro. Here, we present two different and complementary Matrix-Assisted Laser Desorption/Ionization Time-Of-Flight Mass Spectrometry (MALDI-TOF/MS)-based approaches for the quantification of Parkin E3 ligase activity invitro. Both approaches are scalable for high-throughput primary screening to facilitate the identification of Parkin modulators.

Development of monoclonal antibody-based blocking ELISA for detecting SARS-CoV-2 exposure in animals.

The global pandemic of severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2) poses a significant threat to public health. Besides humans, SARS-CoV-2 can infect several animal species. Highly sensitive and specific diagnostic reagents and assays are urgently needed for rapid detection and implementation of strategies for prevention and control of the infection in animals. In this study, we initially developed a panel of monoclonal antibodies (mAbs) against SARS-CoV-2 nucleocapsid protein. To detect SARS-CoV-2 antibodies in a broad spectrum of animal species, an mAb-based blocking enzyme-linked immunosorbent assay (bELISA) was developed. Test validation using a set of animal serum samples with known infection status obtained an optimal percentage of inhibition cut-off value of 17.6% with diagnostic sensitivity of 97.8% and diagnostic specificity of 98.9%. The assay demonstrates high repeatability as determined by a low coefficient of variation (7.23%, 4.89%, and 3.16%) between-runs, within-run, and within-plate, respectively. Testing of samples collected over time from experimentally infected cats showed that the bELISA was able to detect seroconversion as early as 7 days post-infection. Subsequently, the bELISA was applied for testing pet animals with coronavirus disease 2019 (COVID-19)-like symptoms and specific antibody responses were detected in two dogs. The panel of mAbs generated in this study provides a valuable tool for SARS-CoV-2 diagnostics and research. The mAb-based bELISA provides a serological test in aid of COVID-19 surveillance in animals. IMPORTANCE Antibody tests are commonly used as a diagnostic tool for detecting host immune response following infection. Serology (antibody) tests complement nucleic acid assays by providing a history of virus exposure, no matter symptoms developed from infection or the infection was asymptomatic. Serology tests for COVID-19 are in high demand, especially when the vaccines become available. They are important to determine the prevalence of the viral infection in a population and identify individuals who have been infected or vaccinated. ELISA is a simple and practically reliable serological test, which allows high-throughput implementation in surveillance studies. Several COVID-19 ELISA kits are available. However, they are mostly designed for human samples and species-specific secondary antibody is required for indirect ELISA format. This paper describes the development of an all species applicable monoclonal antibody (mAb)-based blocking ELISA to facilitate the detection and surveillance of COVID-19 in animals.

High-Throughput Assay of Cytochrome P450-Dependent Drug Demethylation Reactions and Its Use to Re-Evaluate the Pathways of Ketamine Metabolism.

In a search for a reliable, inexpensive, and versatile technique for high-throughput kinetic assays of drug metabolism, we elected to rehire an old-school approach based on the determination of formaldehyde (FA) formed in cytochrome P450-dependent demethylation reactions. After evaluating several fluorometric techniques for FA detection, we chose the method based on the Hantzsch reaction with acetoacetanilide as the most sensitive, robust, and adaptable to high-throughput implementation. Here we provide a detailed protocol for using our new technique for automatized assays of cytochrome P450-dependent drug demethylations and discuss its applicability for high-throughput scanning of drug metabolism pathways in the human liver. To probe our method further, we applied it to re-evaluating the pathways of metabolism of ketamine, a dissociative anesthetic and potent antidepressant increasingly used in the treatment of alcohol withdrawal syndrome. Probing the kinetic parameters of ketamine demethylation by ten major cytochrome P450 (CYP) enzymes, we demonstrate that in addition to CYP2B6 and CYP3A enzymes, which were initially recognized as the primary metabolizers of ketamine, an important role is also played by CYP2C19 and CYP2D6. At the same time, the involvement of CYP2C9 suggested in the previous reports was deemed insignificant.

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption

The increasing ubiquity of big data and cloud-based computing has led to increased concerns regarding the privacy and security of user data. In response, fully homomorphic encryption (FHE) was developed to address this issue by enabling arbitrary computation on encrypted data without decryption. However, the high computational costs of homomorphic evaluations restrict the practical application of FHE schemes. To tackle these computational and memory challenges, a variety of optimization approaches and acceleration efforts are actively being pursued. This paper introduces the KeySwitch module, a highly efficient and extensively pipelined hardware architecture designed to accelerate the costly key switching operation in homomorphic computations. Built on top of an area-efficient number-theoretic transform design, the KeySwitch module exploited the inherent parallelism of key switching operation and incorporated three main optimizations: fine-grained pipelining, on-chip resource usage, and high-throughput implementation. An evaluation on the Xilinx U250 FPGA platform demonstrated a 1.6× improvement in data throughput compared to previous work with more efficient hardware resource utilization. This work contributes to the development of advanced hardware accelerators for privacy-preserving computations and promoting the adoption of FHE in practical applications with enhanced efficiency.

Efficient Implementation of Complex Multipliers on FPGAs Using DSP Slices

In this paper, we propose two efficient implementations of complex multipliers on field-programmable gate arrays (FPGAs) using DSP slices. The first implementation aims for high throughput and the second one for low area. By mapping these circuits to the DSP slices in the FPGA, the proposed implementations have the advantage that they only require three DSP slices. Experimental results show that the proposed high-throughput implementation saves hardware resources with respect to previous approaches, while reaching the highest achievable clock frequency. Alternatively, the proposed low-area implementation reduces the amount of hardware resources even further at the cost of reducing the clock frequency.

Rapid Enantiomeric Excess Measurements of Enantioisotopomers by Molecular Rotational Resonance Spectroscopy.

Recent work in drug discovery has shown that selectively deuterated small molecules can improve the safety and efficacy for active pharmaceutical ingredients. The advantages derive from changes in metabolism resulting from the kinetic isotope effect when deuterium is substituted for a hydrogen atom at a structural position where rate limiting C-H bond breaking occurs. This application has pushed the development of precision deuteration strategies in synthetic chemistry that can install deuterium atoms with high regioselectivity and with stereocontrol. Copper-catalyzed alkene transfer hydrodeuteration chemistry has recently been shown to have high stereoselectivity for deuteration at the metabolically important benzyl C-H position. In this case, stereocontrol results in the creation of enantioisotopomers-molecules that are chiral solely by virtue of the deuterium substitution-and chiral analysis techniques are needed to assess the reaction selectivity. It was recently shown that chiral tag molecular rotational resonance (MRR) spectroscopy provides a routine way to measure the enantiomeric excess and establish the absolute configuration of enantioisotopomers. High-throughput implementations of chiral tag MRR spectroscopy are needed to support optimization of the chemical synthesis. A measurement methodology for high-throughput chiral analysis is demonstrated in this work. The high-throughput ee measurements are performed using cavity-enhanced MRR spectroscopy, which reduces measurement times and sample consumption by more than an order-of-magnitude compared to the previous enantioisotopomer analysis using a broadband MRR spectrometer. It is also shown that transitions for monitoring the enantiomers can be selected from a broadband rotational spectrum without the need for spectroscopic analysis. The general applicability of chiral tag MRR spectroscopy is illustrated by performing chiral analysis on six enantioisotopomer reaction products using a single molecule as the tag for chiral discrimination.

Low-density parity-check codes: Highway to channel capacity

Low-density parity-check (LDPC) codes are not only capacity-approaching, but also greatly suitable for high-throughput implementation. Thus, they are the most popular codes for high-speed data transmission in the past two decades. Thanks to the low-density property of their parity-check matrices, the optimal maximum a posteriori probability decoding of LDPC codes can be approximated by message-passing decoding with linear complexity and highly parallel nature. Then, it reveals that the approximation has to carry on Tanner graphs without short cycles and small trapping sets. Last, it demonstrates that well-designed LDPC codes with the aid of computer simulation and asymptotic analysis tools are able to approach the channel capacity. Moreover, quasi-cyclic (QC) structure is introduced to significantly facilitate their high-throughput implementation. In fact, compared to the other capacity-approaching codes, QC-LDPC codes can provide better area-efficiency and energy-efficiency. As a result, they are widely applied in numerous communication systems, e.g., Landsat satellites, Chang'e Chinese Lunar mission, 5G mobile communications and so on. What's more, its extension to non-binary Galois fields has been adopted as the channel coding scheme for BeiDou navigation satellite system.

Low area and high throughput implementation of advanced encryption standard hardware accelerator on FPGA using Mux‐Demux pair

AbstractNow‐a‐days advanced cryptographic algorithms are needed in order to improve data security and confidentiality. One such algorithm used prominently is advanced encryption standard (AES) algorithm. AES is a complex algorithm with multiple rounds of processing data and occupies more space or area when implemented on hardware. Since each sub‐step of computation has a similar structure, the proposed method employs the novel idea of using the same hardware to implement the AES functionality. Hence the number of logical units occupied are leveraged. The proposed scheme, Mux‐Demux pair method (MDP), uses a mux‐demux structure. It is implemented on Virtex‐7 and ZynQ7000 FPGAs and the code is written in Verilog HDL language in the Vivado software. The proposed work when simulated on Virtex‐7 occupies an area of 1932 slices, giving an optimized throughput of 10.167 Gbps while the work simulated on ZynQ7000 occupies an area of 3253 slices, resulting in a throughput of 23.858 Gbps.

An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology

Nowadays, hyperspectral imaging is recognized as cornerstone remote sensing technology. The explosive growth in image data volume and instrument data rates, compete with limited on-board storage resources and downlink bandwidth, making hyperspectral image data compression a mission critical on-board processing task. The Consultative Committee for Space Data Systems (CCSDS) extended the previous issue of the CCSDS-123.0 Recommended Standard for multi- and hyperspectral image compression to provide with Near-Lossless compression functionality. A key feature of the CCSDS-123.0-B-2 is the improved Hybrid Entropy Coder, which at low bit rates, provides substantially better compression performance than the Issue 1 entropy coders. In this paper, we introduce a high-throughput hardware implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder. The introduced architecture exploits the systolic design pattern to provide modularity and latency insensitivity in a deep and elastic pipeline achieving a constant throughput of 1 sample/cycle with a small FPGA resource footprint. This architecture is described in portable VHDL RTL and is implemented, validated and demonstrated on a commercially available Xilinx KCU105 development board hosting a Xilinx Kintex Ultrascale XCKU040 SRAM FPGA, and thus, is directly transferable to Xilinx Radiation Tolerant Kintex UltraScale XQRKU060 space-grade devices for space deployments. Moreover, state-of-the-art SpaceFibre (ECSS-E-ST-50-11C) serial link interface and test equipment were used in the validation platform to emulate an on-board deployment. The introduced CCSDS-123.0-B-2 Hybrid Entropy Encoder achieves a constant throughput performance of 305 MSamples/s. To the best of our knowledge, this is the first published fully-compliant architecture and high-throughput implementation of the CCSDS-123.0-B-2 Hybrid Entropy Coder, targeting space-grade FPGA technology.

High Throughput Implementation of Post-Quantum Key Encapsulation and Decapsulation on GPU for Internet of Things Applications

Internet of Things (IoT) sensor nodes are placed ubiquitously to collect information, which is then vulnerable to malicious attacks. For instance, adversaries can perform side channel attack on the sensor nodes to recover the symmetric key for encrypting IoT data. Refreshing the symmetric key frequently can reduce the risk of compromised keys. However, the number of sensor nodes connected to the gateway and cloud server is massive. Refreshed symmetric keys need to be sent to gateway devices and cloud server frequently with a secure key encapsulation mechanism (KEM), which is time-consuming. In this article, novel and efficient implementation techniques are proposed to accelerate Kyber, a post-quantum KEM, on a Graphics Processing Unit (GPU). Fully parallel implementation of number theoretic transform (NTT) with combined levels is presented, which is 2.65× faster than state-of-the-art result on a GPU. Other proposed techniques include parallel rejection sampling, central binomial distribution with coalesced memory access and parallel fine-grain AES-256. These techniques enable high throughput performance with 162760 encapsulations/second and 107631 decapsulations/second on an RTX2060 GPU. This is also the first fine grain implementation of post-quantum KEM (Kyber) on a GPU, which can be used to offer key encapsulation/decapsulation as a service to reduce the burden on IoT systems.

Mesowestern Blot: Simultaneous Analysis of Hundreds of Submicroliter Lysates.

Western blotting is a widely used technique for molecular-weight-resolved analysis of proteins and their posttranslational modifications, but high-throughput implementations of the standard slab gel arrangement are scarce. The previously developed Microwestern requires a piezoelectric pipetting instrument, which is not available for many labs. Here, we report the Mesowestern blot, which uses a 3D-printable gel casting mold to enable high-throughput Western blotting without piezoelectric pipetting and is compatible with the standard sample preparation and small (∼1 μL) sample sizes. The main tradeoffs are reduced molecular weight resolution and higher sample-to-sample CV, making it suitable for qualitative screening applications. The casted polyacrylamide gel contains 336, ∼0.5 μL micropipette-loadable sample wells arranged within a standard microplate footprint. Polyacrylamide % can be altered to change molecular weight resolution profiles. Proof-of-concept experiments using both infrared-fluorescent molecular weight protein ladder and cell lysate (RIPA buffer) demonstrate that the protein loaded in Mesowestern gels is amenable to the standard Western blotting steps. The main difference between Mesowestern and traditional Western is that semidry horizontal instead of immersed vertical gel electrophoresis is used. The linear range of detection is at least 32-fold, and at least ∼500 attomols of β-actin can be detected (∼29 ng of total protein from mammalian cell lysates: ∼100–300 cells). Because the gel mold is 3D-printable, users with access to additive manufacturing cores have significant design freedom for custom layouts. We expect that the technique could be easily adopted by any typical cell and molecular biology laboratory already performing Western blots.

EAPOTc: An integrated empirical interatomic potential optimization platform for compound solids

The extension of interatomic potentials from elemental solids to compound ones causes a bottleneck in atomistic simulations of multi-component solids such as intermetallic compounds and solid solutions. In contrast to several extensive tools released to construct elemental potentials, such as MEAMfit and ATOMICREX, very little software has been specifically designed for multi-component solids. Herein, we extend our recently proposed software EAPOTs (Empirical interAtomic POTentials for single elemental solids) to interatomic potentials of compound solids. This new software-termed as EAPOTc or the integrated Empirical interAtomic POTential optimization platform for compound solids-provides robust multi-level objective optimization strategies with various cross potential functions and extensive combinations of multiple targets such as energy, stress, force, and elasticity. Compatibility with published elemental potentials was also implemented in EAPOTc to ensure seamless combinations of different sources of elemental potentials by using the transformation invariance rules without reliability loss for the original elemental potentials. Similar to our EAPOTs code, a high-throughput (HT) scheme was designed based on automatic communication using first-principles code (e.g., VASP) to retrieve the derived properties based on energy, stress, force, and elasticity; in addition, multiple objective optimization procedures were included. The efficiency and flexibility of EAPOTc were critically validated and tested for various metallic and covalent compound systems, including HT implementation and applicability testing for extreme scenarios. Our software demonstrated several advantages, such as a concise and user-friendly graphical user interface, extensive compatibility between elemental potentials, robust optimization schemes, and a high degree of functional integration.

TensorCrypto: High Throughput Acceleration of Lattice-Based Cryptography Using Tensor Core on GPU

Tensor core is a newly introduced hardware unit in NVIDIA GPU chips that allows matrix multiplication to be computed much faster than in the integer and floating-point units. In this paper, we show that for the first time, tensor core can be used to accelerate state-of-the-art lattice-based cryptosystems. We employed tensor core to speed up polynomial convolution, which is the most time consuming operation in lattice-based cryptosystems. Towards that aim, several parallel algorithms are proposed to allow the tensor core to handle flexible matrix sizes and ephemeral key pairs. Experimental results show that the polynomial convolution computed using the tensor core is at least <inline-formula> <tex-math notation="LaTeX">$2\times $ </tex-math></inline-formula> faster than the version implemented with conventional integer units of the NVIDIA GPU. The proposed tensor-core-based polynomial convolution technique was applied to NTRU, one of the finalists in NIST post-quantum cryptography (PQC) standardization. It achieved <inline-formula> <tex-math notation="LaTeX">$2.02\times /1.98\times $ </tex-math></inline-formula> (encapsulation) and <inline-formula> <tex-math notation="LaTeX">$1.56\times /1.90\times $ </tex-math></inline-formula> (decapsulation) higher throughput on two parameter sets (ntruhps2048509 and ntruhps2048677), compared to the conventional integer-based implementations on a GPU. In particular, the proposed implementation techniques achieved throughput up to 793651 key encapsulations per second and 505051 decapsulations per second on a RTX2060 GPU. To demonstrate the flexibility of the proposed technique, we extend the implementation to other lattice-based cryptosystems that have a small modulus: LAC and two variant parameter sets in FrodoKEM. Considering that the IoT gateway devices and cloud servers need to handle massive connections from the sensor nodes, the proposed high throughput implementation on GPU is very useful in securing the IoT communication.

SPaMD studio: An integrated platform for atomistic modeling, simulation, analysis, and visualization

An integrated platform for custom and modular atomistic modeling, high-throughput implementation of various functional simulations, robust atomic topological analysis, and high-fidelity processing and visualization was developed in this study, called the Scalable Parallel Molecular Dynamics (SPaMD) studio. The modular modeling system provides a fast and direct means of constructing specific models such as those of nanostructures, dislocations, and cracks, as well as complex models such as those of bilayers, multilayers, and nanocomposites. Further, the custom modeling system enables consecutive nested processing of selections and operations with a comprehensive workflow to obtain arbitrary models with complicated geometry. Various high-throughput schemes were designed for functional simulations through the integration of automatic modeling tools, load-balanced task allocation systems, adaptive real-time data analysis, and visualization methods, as well as a robust logic feedback system. In addition, the atomistic analysis supports both on-the-fly and post-quantification for crystal structure, orientation, and dislocation by integrating AACSD and AADIS codes. To facilitate processing and simulation, a user-friendly graphical user interface was designed for SPaMD, which also supports highly efficient rendering for tens of millions of atoms. To demonstrate the efficiency and functionalities of this platform, it was critically validated by conducting several evaluations and tests, which provide guidance for and confidence in its potential applications in targeted atomistic simulations.

Low-latency area-efficient systolic bit-parallel GF(2[formula omitted]) multiplier for a narrow class of trinomials

Edge computing in Internet of Things (IoT) requires high-performance as well as cost-effective hardware implementations to accommodate large number of computations. Implementation of security in IoT edge devices is indispensable, and attaining security is possible using Elliptic curve cryptography (ECC) algorithms. Finite field GF(2m) multiplication is a performance-critical operation in these algorithms, hence, it requires efficient hardware implementations. Systolic structures for GF(2m) multiplier are suitable for high-performance applications as they allow high-throughput implementations. Many systolic GF(2m) multipliers have been proposed in the literature that can achieve high throughput rates, however, they require large area and high latency. In this paper, we propose a polynomial basis GF(2m) systolic multiplier applicable for a narrow class of trinomials which includes both the NIST (National Institute of Standards and Technology) recommended trinomials for m=233 and 409 fields. Analytical comparisons with the related multipliers for m=409 show that the multiplier proposed in this paper reduces the latency by 32% and area by 5%. The proposed multiplier is synthesized using synopsis tools targeting for an ASIC implementation and the comparisons are also presented. The proposed low-latency area-efficient multiplier can be used in the implementation of hardware security for low-cost IoT edge devices.

Fully Parallel Implementation of Otsu Automatic Image Thresholding Algorithm on FPGA

This work proposes a high-throughput implementation of the Otsu automatic image thresholding algorithm on Field Programmable Gate Array (FPGA), aiming to process high-resolution images in real-time. The Otsu method is a widely used global thresholding algorithm to define an optimal threshold between two classes. However, this technique has a high computational cost, making it difficult to use in real-time applications. Thus, this paper proposes a hardware design exploiting parallelization to optimize the system’s processing time. The implementation details and an analysis of the synthesis results concerning the hardware area occupation, throughput, and dynamic power consumption, are presented. Results have shown that the proposed hardware achieved a high speedup compared to similar works in the literature.

Secure HIGHT Implementation on ARM Processors

Secure and compact designs of HIGHT block cipher on representative ARM microcontrollers are presented in this paper. We present several optimizations for implementations of the HIGHT block cipher, which exploit different parallel approaches, including task parallelism and data parallelism methods, for high-speed and high-throughput implementations. For the efficient parallel implementation of the HIGHT block cipher, the SIMD instructions of ARM architecture are fully utilized. These instructions support four-way 8-bit operations in the parallel way. The length of primitive operations in the HIGHT block cipher is 8-bit-wise in addition–rotation–exclusive-or operations. In the 32-bit word architecture (i.e., the 32-bit ARM architecture), four 8-bit operations are executed at once with the four-way SIMD instruction. By exploiting the SIMD instruction, three parallel HIGHT implementations are presented, including task-parallel, data-parallel, and task/data-parallel implementations. In terms of the secure implementation, we present a fault injection countermeasure for 32-bit ARM microcontrollers. The implementation ensures the fault detection through the representation of intra-instruction redundancy for the data format. In particular, we proposed two fault detection implementations by using parallel implementations. The two-way task/data-parallel based implementation is secure against fault injection models, including chosen bit pair, random bit, and random byte. The alternative four-way data-parallel-based implementation ensures all security features of the aforementioned secure implementations. Moreover, the instruction skip model is also prevented. The implementation of the HIGHT block cipher is further improved by using the constant value of the counter mode of operation. In particular, the 32-bit nonce value is pre-computed and the intermediate result is directly utilized. Finally, the optimized implementation achieved faster execution timing and security features toward the fault attack than previous works.