High Thermal Budget Research Articles

Impact of UV annealing on the hole effective mobility in SnO pFET

Using ultraviolet (UV) annealing through wide energy bandgap HfO2/SiO2 gate dielectric, nanosheet SnO pFET achieved hole effective mobility (µeff) from 55 cm2/V-s at low hole density (Qh) to 13.38 cm2/V-s at 5 × 1012 cm-2 Qh, compared to that of 9.03 cm2/V-s at 5 × 1012 cm-2 Qh for SnO device without UV annealing. This is the highest µeff among oxide semiconductor pFETs at high Qh, which is required to realize low-power high-density monolithic 3D CMOS logic. This requires excellent surface roughness, good uniformity and free-from grain boundaries that is beyond the thermally-annealed poly-Si. Excellent on-current/off-current (ION/IOFF) value of 1.05 × 105 were measured simultaneously in the UV-annealed SnO pFET, which is due to the ultra-thin 8 nm thick SnO nanosheet channel to pinch off the channel leakage. From X-ray photoelectron spectroscopy (XPS) analysis, the 48% µeff improvement by UV irradiation is due to increased Sn2+ and decreased Sn0. Such high µeff at high Qh, large ION/IOFF, smooth surface, good uniformity and low thermal budget process are the enabling technologies for monolithic 3D CMOS.

Development and Characterization of N2O-Plasma Oxide Layers for High-Temperature p-Type Passivating Contacts in Silicon Solar Cells.

Full-area passivating contacts based on SiOx/poly-Si stacks are key for the new generation of industrial silicon solar cells substituting the passivated emitter and rear cell (PERC) technology. Demonstrating a potential efficiency increase of 1 to 2% compared to PERC, the utilization of n-type wafers with an n-type contact at the back and a p-type diffused boron emitter has become the industry standard in 2024. In this work, variations of this technology are explored, considering p-type passivating contacts on p-type Si wafers formed via a rapid thermal processing (RTP) step. These contacts could be useful in conjunction with n-type contacts for realizing solar cells with passivating contacts on both sides. Here, a particular focus is set on investigating the influence of the applied thermal treatment on the interfacial silicon oxide (SiOx) layer. Thin SiOx layers formed via ultraviolet (UV)-O3 exposure are compared with layers obtained through a plasma treatment with nitrous oxide (N2O). This process is performed in the same plasma enhanced chemical vapor deposition (PECVD) chamber used to grow the Si-based passivating layer, resulting in a streamlined process flow. For both oxide types, the influence of the RTP thermal budget on passivation quality and contact resistivity is investigated. Whereas the UV-O3 oxide shows a pronounced degradation when using high thermal budget annealing (T > 860 °C), the N2O-plasma oxide exhibits instead an excellent passivation quality under these conditions. Simultaneously, the contact resistivity achieved with the N2O-plasma oxide layer is comparable to that yielded by UV-O3-grown oxides. To unravel the mechanisms behind the improved performance obtained with the N2O-plasma oxide at high thermal budget, characterization by high-resolution (scanning) transmission electron microscopy (HR-(S)TEM), X-ray reflectometry (XRR) and X-ray photoelectron spectroscopy (XPS) is conducted on layer stacks featuring both N2O and UV-O3 oxides after RTP. A breakup of the UV-O3 oxide at high thermal budget is observed, whereas the N2O oxide is found to maintain its structural integrity along the interface. Furthermore, chemical analysis reveals that the N2O oxide is richer in oxygen and contains a higher amount of nitrogen compared to the UV-O3 oxide. These distinguishing characteristics can be directly linked to the enhanced stability exhibited by the N2O oxide under higher annealing temperatures and extended dwell times.

Nanocrystalline copper for direct copper-to-copper bonding with improved cross-interface formation at low thermal budget

Direct copper-to-copper (Cu-Cu) bonding is a promising technology for advanced electronic packaging. Nanocrystalline (NC) Cu receives increasing attention due to its unique ability to promote grain growth across the bonding interface. However, achieving sufficient grain growth still requires a high thermal budget. This study explores how reducing grain size and controlling impurity concentration in NC Cu leads to substantial grain growth at low temperatures. The fabricated NC Cu has a uniform nanograin size of around 50 nm and a low impurity level of 300 ppm. To prevent ungrown NC and void formation caused by impurity aggregation, we propose a double-layer (DL) structure comprising a normal coarse-grained (CG) layer underneath the NC layer. The CG layer, with a grain size of 1 μm and an impurity level of 3 ppm, acts as a sink, facilitating impurity diffusion from the NC layer to the CG layer. Thanks to sufficient grain growth throughout the entire NC layer, cross-interface Cu-Cu bonding becomes possible under a low thermal budget, either at 100 °C for 60 min or at 200 °C for only 5 min.

Passivated indium oxide thin-film transistors with high field-effect mobility (128.3 cm2 V−1 s−1) and low thermal budget (200 °C)

Here, we demonstrate a high-mobility indium oxide (In2O3) thin-film transistor (TFT) with a sputtered alumina (Al2O3) passivation layer (PVL) with a low thermal budget (200 °C). The sputtering process of the Al2O3 PVL plays a positive role in improving the field-effect mobility (µ FE) and current on/off ratio (I ON/I OFF) performance of the In2O3 TFTs. However, these enhancements are limited due to the high density of intrinsic trap defects in the In2O3 channels, as reflected in their large hysteresis and poor bias stability. Treating the In2O3 channel with oxygen (O2) plasma prior to sputtering the Al2O3 PVL results in notable improvements. Specifically, a high µ FE of 128.3 cm2V−1 s−1, a high I ON/I OFF over 106 at V DS of 0.1 V, a small hysteresis of 0.03 V, and a negligible threshold voltage shift under negative bias stress are achieved in the passivated In2O3 TFT (with O2 plasma pretreatment), representing a significant improvement compared to the passivated In2O3 TFT (without O2 plasma pretreatment) and the unpassivated In2O3 TFT. The remarkable reduction of intrinsic trap defects in the passivated In2O3 TFT compensated by O2 plasma is the primary mechanism underlying the improvement in µ FE and bias stability, as validated by x-ray photoelectron spectra, hysteresis analysis, and temperature-stress electrical characterizations. Plasma treatment effectively compensates for intrinsic trap defects in oxide semiconductor (OS) channels, when combined with sputter passivation, resulting in a significant enhancement of the overall performance of OS TFTs under low thermal budgets. This approach offers valuable insights into advancing OS TFTs with satisfactory driving capability and wide applicability.

III-V material-based junction-free L-shaped gate normal line tunneling FET for improved performance

In this paper, we introduce a novel III–V compound material-based junction-free (JF) L-shaped gate normal line tunneling field-effect transistor (III–V JF L GNLTFET) for improved output performance at 0.5 V operation. The key design metric, i.e. JF or junctionless design, in our device eliminates issues like random dopant fluctuations (RDF) and high thermal budgets and streamlines the fabrication. The implementation of III–V compound material, i.e. low bandgap compound GaSb, in the source region, combined with the larger area gate normal line tunneling, improves the ON current for our proposed III–V JF L GNLTFET device. Additionally, the utilization of large bandgap GaAs compounds on the drain and channel sides eliminates ambipolarity and further enhances the performance of our proposed device. Meaning that the proposed device simultaneously improves the ON current and suppresses the ambipolarity. Our proposed III–V JF L GNLTFET exhibits enhanced output performance with an ON current of 23.2 μA μm−1 and a minimum and average subthreshold swing of 3.7 mV dec−1 and 15.82 mV dec−1 respectively. Furthermore, the proposed III–V JF L GNLTFET also gives superior RF/analog performance with transconductance (168.65 μS), cut-off frequency (33.52 GHz), gain-bandwidth product (5.11 GHz), and transconductance-frequency product (243.7 GHz).

A symmetric heterogate dopingless electron-hole bilayer TFET with ferroelectric and barrier layers

In this paper, a symmetric heterogate dopingless electron–hole bilayer tunnel field-effect transistor with a ferroelectric layer and a dielectric barrier layer (FBHD-EHBTFET) is proposed. FBHD-EHBTFET can not only avoid random doping fluctuation and high thermal budget caused by doping, but also solve the issue that conventional EHBTFETs are unable to use the self-alignment process during device manufacturing. The simultaneous introduction of the symmetric heterogate and dielectric barrier layer can significantly suppress off-state current (I off). Ferroelectric material embedded in the gate dielectric layer can enhance electron tunneling, contributing to improving on-state current (I on) and steepening average subthreshold swing (SS avg). By optimizing various parameters related to the gate, ferroelectric layer, and dielectric barrier layer, FBHD-EHBTFET can obtain the I off of 1.11 × 10–18 A μm−1, SS avg of 12.5 mV/dec, and I on of 2.59 × 10–5 A μm−1. Compared with other symmetric dopingless EHBTFETs, FBHD-EHBTFET can maintain high I on while reducing its I off by up to thirteen orders of magnitude and SS avg by at least 51.2%. Moreover, investigation demonstrates that both interface fixed charge and interface trap can increase I off, degrading the off-state performance of device. The study on FBHD-EHBTFET-based dynamic random access memory shows that it has the high read-to-current ratio of 1.1 × 106, high sense margin of 0.42 μA μm−1, and long retention time greater than 100 ms, demonstrating that it has great potential in low-power applications.

Exploring the evolution of mass density and thickness of N-doped Ge-rich GeSbTe during multistep crystallization

Among phase change materials, Ge-rich GeSbTe alloys (GGST) are key alloys for the next generation of embedded phase change memories because of their good thermal stability, allowing their use for the automotive applications. Several studies have investigated GGST crystallization, which takes place in several stages, including phase separation in the amorphous material, the crystallization of the cubic Ge and GST phases before a complete crystallization for higher thermal budget. So far, however, no information is available on the possible changes in density and thickness of such alloys. This paper investigates such variations in density and thickness for a N-doped GGST layer (GGSTN) during isothermal annealing, following the four main stages of its multistep crystallization process. X-ray reflectivity (XRR) and X-ray diffraction were employed for analysis. The study reveals that density and thickness exhibit distinct changes during crystallization, with density increasing by approximately 9% during transition from amorphous to crystalline states. These changes are attributed to alterations in layer morphology, particularly at the Ge crystallization temperature and at the onset of GST crystal formation. Additionally, at high thermal budgets, discrepancies between XRR analysis methods suggest the formation of a thin, lower density layer near the top interface of the GGSTN layer. These results provide insights into the structural evolution of the GGSTN layer, which is crucial for phase change random access memory applications.

Metal‐Organic Chemical Vapor Deposition Regrowth of Highly Doped n+ (In)GaN Source/Drain Layers for Radio Frequency Transistors

Herein, epitaxially regrown n+ (In)GaN source/drain layers for radio frequency high electron mobility transistors, addressing material and electrical characterization, are reported. A range of n+ GaN and n+ InGaN layers with indium 4–12 at% and silicon 0–5.1 × 1020 cm−3 are evaluated. The active carrier concentration in n+ InGaN exceeds 2 × 1020 cm−3. The layers exhibit so‐called V‐defects, observed by atomic force microscope and transmission electron microscope (TEM), which are associated with local composition changes. In addition to the high Si doping levels, nitrogen vacancies are also considered to contribute toward their net carrier concentration. Due to its relevance for device processing, selectivity analysis is performed, and the optimal process conditions for selective regrowth are identified. Regrowth under high temperature (800 °C) is found to be conducive to improved selectivity. However, a high thermal budget negatively impacts the overall regrowth process, as reported here for In0.17Al0.83N and Al0.26Ga0.74N barriers: whereas the InAlN barrier suffers from intermixing, the AlGaN barrier demonstrates high‐temperature stability. The impact of intermixing is studied from complementary TEM and DC electrical measurements. A low overall contact resistance of 75 Ω μm is obtained with the regrown n+ InGaN layers.

Patterning Magnonic Structures via Laser Induced Crystallization of Yittrium Iron Garnet

AbstractThe fabrication and integration of high‐quality structures of Yttrium Iron Garnet (YIG) is critical for magnonics. Films with excellent properties are obtained only on single crystal Gadolinium Gallium Garnet (GGG) substrates using high‐temperature processes. The subsequent realization of magnonic structures via lithography and etching is not straightforward as it requires a tight control of the edge roughness, to avoid magnon scattering, and planarization in case of multilayer devices. In this work a different approach is described based on local laser annealing of amorphous YIG films, avoiding the need for subjecting the entire sample to high thermal budgets and for physical etching. Starting from amorphous and paramagnetic YIG films grown by pulsed laser deposition at room temperature on GGG, a 405 nm laser is used for patterning arbitrary shaped ferrimagnetic structures by local crystallization. In thick films (160 nm) the laser induced surface corrugation prevents the propagation of spin‐wave modes in patterned conduits. For thinner films (80 nm) coherent propagation is observed in 1.2 µm wide conduits displaying an attenuation length of 5 µm that is compatible with a damping coefficient of ≈5 × 10−3. Possible routes to achieve damping coefficients compatible with state‐of‐the art epitaxial YIG films are discussed.

Both-Sided TOPCon Solar Cells – Towards a Lean Process Flow for Silicon Bottom Solar Cells

Silicon solar cells with both-side full-area passivating hole and electron contacts are viable candidates for application as bottom cells in tandem architectures. In this contribution, cells with poly-Si based contacts at both sides are investigated as a potential upgrade to the emerging i-TOPCon single junction devices featuring a passivating contact (poly-Si(n)/SiOx) only at the rear side and an alternative to the SHJ technology featuring a-Si based full-area passivating hole and electron contacts. We show that a higher thermal budget is needed to mediate between poly-Si(p)/SiOx hole and poly-Si(n)/SiOx electron contact when the same thermal interfacial SiOx is applied. This is addressed by using a PECVD oxide that is adapted to the needs of the hole and/or the electron contact. We present a proof-of-concept poly-Si(n)/SiOx/c-Si/SiOx/poly-Si(n) device with emphasis on a lean process flow. An all-PECVD process sequence for the hole contact, i.e., plasma oxides+i/p-a-Si deposited at 200°C in the same chamber was applied. With co-annealing of the contacts, no additional hydrogenation, and no edge insulation step, we observe no shunting and obtain efficiencies of up to 20.8% for M2 size cells, so far.

Study on dopant activation and EOT impact in HKMG stacks using microwave annealing with different frequencies

In this paper, we have examined the dopant activation levels in various materials (Si, SiGe, and Ge) annealed using two different microwave annealing (MWA) frequencies, 2.45 GHz and 5.8 GHz, with rapid thermal annealing serving as a comparative counterpart. The aim is to identify a material-specific annealing method that minimizes the high thermal budget typically required in the annealing process. For the dopant activation of Si wafer with B doping, there are two different frequencies (2.45 GHz and 5.8 GHz) MWA methods were compared. As the results of electrical measurement, the high activation level by 5.8 GHz MWA shows the material-targeted annealing method to reduce the thermal budget of the device. Additionally, we fabricated a high-k/metal gate (HKMG) MOSCAP structure, which was annealed using 2.45 GHz and 5.8 GHz MWA as part of the post-metallization annealing process. The results show that MWA at 2.45 GHz is more efficient than HF 5.8 GHz MWA at 3000 W in minimizing the interface trapped charge and the reduction in leakage current density. The highest capacitance (1.73 μF cm−2) was observed for MWA 2700 W at 2.45 GHz. However, there is a slight clear reduction in capacitance as the frequency increased to 5.8 GHz increasing in interfacial layer thickness. The post-metallization annealing of gate-last MOSCAPs using MWA at 2.45 GHz not only inhibits the growth of the equivalent oxide thickness and Al diffusion but also preserves the effects of pre-thermal annealing on doping activation at 5.8 GHz. Due to undesirable effects such as Al diffusion into the dielectric layer, the MWA at 5.8 GHz and 2.45 GHz demonstrates great a potential candidate, respectively as doping activation and as a post-metallization annealing method for HKMG structures.

An inverted T-shaped vertical tunneling InN/InxGa1-xN heterojunction TFET with high current ratio

An inverted T-shaped vertical InN/InGaN tunneling field effect transistor (TFET) with polarization-induced doping and high current ratio is proposed and investigated. An optimal structure of the proposed device is given by comparing on-state current, subthreshold voltage, and on-state/off-state current ratio. The polarization effect in III-N material induces electrons and holes in the source and drain regions, and non-physical doping can avoid random dopant fluctuations (RDFs) and high thermal budget. The InN/InGaN heterojunction TFET shows significant improvement over the homojunction TFET. The inverted T-shaped structure involves line and point tunneling simultaneously, so the proposed device can achieve higher on-state current than the conventional device. In addition, the proposed device shows the suppression of ambipolar current. The simulations reveal that the ION/IOFF of the proposed structure is about 6.91 × 1012. These results indicate that the line tunneling structure is still available in the polarization-induced InN/InGaN TFET.

Dynamic multi-color switching using ultrathin vanadium oxide on aluminum-based asymmetric Fabry–Pérot resonant structure

Vanadium dioxide (VO2) exhibits strong infrared optical switching due to its insulator–metal phase-transition property. However, in the visible wavelengths, its intrinsic optical switching is quite low. Current research explores solutions like multilayering, intricate structural patterning, high thermal budget processes, and costly metals for improved color switching. Nonetheless, the color gamut coverage with these methodologies remains notably limited. This work overcomes these limitations and demonstrates dynamic multi-color switching covering a large color gamut using a simple, unpatterned, ultrathin (∼ λ14, where wavelength λ is taken as 575 nm at the center of the visible spectrum) asymmetric Fabry–Pérot structure of VO2 on aluminum (Al). We use the transfer matrix method to design the VO2/aluminium (Al)/sapphire structure for maximum visible reflectance switching. VO2 films are synthesized using a simple, low thermal budget atmospheric oxidation of vanadium (V). With varying oxidation durations, different colors of the oxidized samples are observed. Consistent and reversible color-switching is observed visibly and in reflectance measurements with the change in temperature from low (RT ∼ 30 °C) to high (HT ∼ 100 °C) or vice versa due to the phase transition property of the VO2 layer in the structure. Compared to the existing studies, this work shows a significant change in chromaticities and covers a large color gamut when plotted on the CIE chromaticity diagram. This work has potential applications in the fields of display, thermochromic structures, and visible camouflage.

Strontium Vanadate Deposited by ALD: Toward a New Synthesis Approach

Transparent conductive oxides (TCOs) have a wide range of potential applications in fields such as photovoltaics, touch screens, and smart windows. The challenging task when developing conventional TCOs like tin-doped indium oxide (ITO) by the traditional method is to make them more conducting by increasing the concentration of charge carriers without compromising the optical transparency [1]. Another novel approach involves increasing the plasma energy to widen the transparency window by increasing the charge carriers' effective mass. This approach has led to growing interest in perovskite transition metal oxides such as CaVO3 and SrVO3 due to their strong electronic correlation, which results in plasma energy shifting to higher energies than classical TCOs [2,3]. However, obtaining a crystallized film in the perovskite SrVO3 phase for optimal electrical conduction and optical transparency is challenging, particularly at low growth temperatures and when deposited on amorphous substrates like glasses [2, 4].As a result, atomic layer deposition (ALD) has emerged as a promising technique for depositing conformal layers on large surfaces with high aspect ratios and low thermal budgets. In this study, we investigated the deposition of strontium vanadium oxide films by ALD using vanadium tri-isopropoxide (VTIP) as the vanadium precursor, strontium bis(isopropylcyclopentadienyl) (Sr(iPr3Cp)2) from Air Liquide company as the strontium precursor, and water as a reagent, respectively. We deposited SrVO3 films on (100) Silicon and glass substrates at 240°C and annealed them under forming gas (95% Ar, 5% H2) at 500°C for one hour. We paid particular attention to the deposition of an anatase TiO2 buffer layer to promote the crystallization of SVO.The unannealed films were found to be completely amorphous whatever the substrate, and regardless of the presence or not of the TiO2 crystallized buffer. The EDX, STEM-HAADF and SIMS analyses revealed that the buffer is a key element to avoid the Si diffusion in SVO layer, before, and even more upon annealing. The annealed samples with a buffer layer deposited on both substrates were crystallized into various SrxVyOz phases according to the Sr amount, controlled by the Sr cycles ratio (RSR) (figure). The XRD data allowed the identification of the Sr3VO8 and Sr2VO4 phases, where the last one favors the higher Sr amount. The influence of the substrate is significant and discussed. Furthermore, we characterized the films' optical properties using spectroscopic ellipsometry in the UV-visible range. We analyzed the refractive index and extinction coefficient behavior according to the Sr amount and evaluated the effect of annealing. We estimated the band gap energy using Tauc-Lorentz and Tauc plot models and discussed it in relation to the Sr amount and the obtained phases.Our study provides not only valuable insights into the deposition and characterization of SrVO3 thin films for potential TCO applications, but also on Sr3VO8 and Sr2VO4 phases, which may be of interest for their transparent oxide optical properties. New ALD growth strategies to improve the SrVO3 phases will be presented as a perspective of this study and as an example of using different V precursor or reactive atmospheres during ALD process.[1] S.C. Dixon, D.O. Scanlon, C.J. Carmalt, I.P. Parkin, "n-Type doped transparent conducting binary oxides: an overview", Journal of Materials Chemistry C, 4, 29 (2016), pp. 6946-6961[2] Zhang, Lei, et al. "Correlated metals as transparent conductors." Nature materials 15.2 (2016): 204-210.[3] Boileau, Alexis, et al. "Highly Transparent and Conductive Indium‐Free Vanadates Crystallized at Reduced Temperature on Glass Using a 2D Transparent Nanosheet Seed Layer." Advanced Functional Materials 32.5 (2022): 2108047.[4] A. Boileau, A. Cheikh, A. Fouchet, A. David, C. Labbé, P. Marie, F. Gourbilleau, U. Lüders, "Tuning of the optical properties of the transparent conducting oxide SrVO3 by electronic correlations", Advanced Optical Materials, 7, 7 (2019), pp. 1801516 Figure 1

Low-Temperature Vapor-Phase Growth of 2D Metal Chalcogenides.

2D metal chalcogenides (MCs) have garnered significant attention from both scientific and industrial communities due to their potential in developing next-generation functional devices. Vapor-phase deposition methods have proven highly effective in fabricating high-quality 2D MCs. Nevertheless, the conventionally high thermal budgets required for synthesizing 2D MCs pose limitations, particularly in the integration of multiple components and in specialized applications (such as flexible electronics). To overcome these challenges, it is desirable to reduce the thermal energy requirements, thus facilitating the growth of various 2D MCs at lower temperatures. Numerous endeavors have been undertaken to develop low-temperature vapor-phase growth techniques for 2D MCs, and this review aims to provide an overview of the latest advances in low-temperature vapor-phase growth of 2D MCs. Initially, the review highlights the latest progress in achieving high-quality 2D MCs through various low-temperature vapor-phase techniques, including chemical vapor deposition (CVD), metal-organic CVD, plasma-enhanced CVD, atomic layer deposition (ALD), etc. The strengths and current limitations of these methods are also evaluated. Subsequently, the review consolidates the diverse applications of 2D MCs grown at low temperatures, covering fields such as electronics, optoelectronics, flexible devices, and catalysis. Finally, current challenges and future research directions are briefly discussed, considering the most recent progress in the field.

Understanding and mitigating resistive losses in fired passivating contacts: role of the interfaces and optimization of the thermal budget

This work presents a study of p-type passivating contacts based on SiCx formed via a rapid thermal processing (RTP) step, using conditions compatible with the firing used to sinter screen-printed metallization pastes in industry. The contributions of the two interfaces (wafer/contact and contact/metal) to the contact resistivity are first decorrelated, identifying tunnelling at the wafer interface as the main contribution. We then investigate the influence of the active dopant concentration on the contact resistivity and the SiCx sheet resistance and propose strategies to reduce both resistances by increasing the thermal budget applied during RTP. Lastly, we discuss potentials and limitations of implementing the investigated stacks as rear side contacts of p-type devices with localized metallization. We demonstrate that increasing the thermal budget during RTP can effectively mitigate resistive losses and enhance contact performance and we show that an oxide layer that can withstand high thermal budgets is the key factor for obtaining simultaneously high passivation quality and good electrical properties. We investigate three different oxide types grown by HNO3 immersion, UV-O3 exposure and N2O plasma oxidation. The latter is demonstrated to be a promising candidate for an application in devices fabricated with high RTP thermal budget.

Design and Performance Optimization of InGaAs/InAlAs Dopingless Tunnel Field-effect Transistor

In this work, an InGaAs/InAlAs dopingless tunnel field-effect transistor is designed and systematically examined through numerical simulations. In line with the charge plasma concept, the proposed device can not only create a p-n-i-n structure without doping to enhance electron tunneling but also effectively overcome issues caused by doping such as random doping fluctuation, high thermal budget, etc. By investigating the effects of the HfO2 length (L H), the source-side channel length (L sc), and the source-drain electrodes structure on the proposed device, it concludes that the best device characteristic can be acquired when L H is located between 110 nm and 128 nm, L sc=4 nm, and double source-drain electrodes are adopted.

Cu-Based Thermocompression Bonding and Cu/Dielectric Hybrid Bonding for Three-Dimensional Integrated Circuits (3D ICs) Application.

Advanced packaging technology has become more and more important in the semiconductor industry because of the benefits of higher I/O density compared to conventional soldering technology. In advanced packaging technology, copper-copper (Cu-Cu) bonding has become the preferred choice due to its excellent electrical and thermal properties. However, one of the major challenges of Cu-Cu bonding is the high thermal budget of the bonding process caused by Cu oxidation, which can result in wafer warpage and other back-end-of-line process issues in some cases. Thus, for specific applications, reducing the thermal budget and preventing Cu oxidation are important considerations in low-temperature hybrid bonding processes. This paper first reviews the advancements in low-temperature Cu-based bonding technologies for advanced packaging. Various low-temperature Cu-Cu bonding techniques such as surface pretreatment, surface activation, structure modification, and orientation control have been proposed and investigated. To overcome coplanarity issues of Cu pillars and insufficient gaps for filling, low-temperature Cu-Cu bonding used, but it is still challenging in fine-pitch applications. Therefore, low-temperature Cu/SiO2, Cu/SiCN, and Cu/polymer hybrid bonding have been developed for advanced packaging applications. Furthermore, we present a novel hybrid bonding scheme for metal/polymer interfaces that achieves good flatness and an excellent bonding interface without the need for the chemical mechanical polishing (CMP) process.

Enhancement of NiOx/Poly‐Si Contact Performance by Insertion of an Ultrathin Metallic Ni Interlayer

Nickel oxide () is a promising hole transport material for perovskite/Si tandem solar cells. Various silicon cell architectures may be used as bottom cells. The polycrystalline (poly‐Si) tunnel diode is expected to be a high‐efficiency interconnection scheme between the two subcells of monolithic tandems in p‐i‐n configuration with a high thermal budget, excellent passivation properties, and low contact resistivity. However, is then interfaced to poly‐Si() and the chemical integrity of the interface due to the necessity of annealing treatments has to be questioned. For this purpose, the /poly‐Si contact resistivity for different annealing temperatures is investigated between 100 and 500 °C, and two different deposition techniques, namely, wet‐chemically applied and sputter‐deposited . The values of more than are obtained. The insertion of a nm‐thin metallic Ni interlayer is shown to enable a tremendous decrease of the contact resistivity by 2–3 orders of magnitude. The formation of is proven by highly resolved (scanning) transmission electron microscopy ((S)TEM) coupled with energy‐dispersive X‐ray spectroscopy (EDXS). This interfacial engineering approach is expected to provide an effective way of improving the contact properties and integrability of into various tandem cell processes.

P-Type Conversion of WS2 and WSe2 by Position-Selective Oxidation Doping and Its Application in Top Gate Transistors.

For the complementary operation of two-dimensional (2D) material-based field-effect transistors (FETs), high-performance p-type FETs are essential. In this study, we applied surface charge-transfer doping from WOx, which has a large work function of ∼6.5 eV, selectively to the access region of WS2 and WSe2 by covering the channel region with h-BN. By reducing the Schottky barrier width at the contact and injecting holes into the valence band, the p-type conversion of intrinsically n-type trilayer WSe2 FET was successfully achieved. However, trilayer WS2 did not show clear p-type conversion because its valence band maximum is 0.66 eV lower than that of trilayer WSe2. Although inorganic WOx boasts high air stability and fabrication process compatibility due to its high thermal budget, the trap sites in WOx cause large hysteresis during back gate operation of WSe2 FETs. However, by using top gate (TG) operation with an h-BN protection layer as a TG insulator, a high-performance p-type WSe2 FET with negligible hysteresis was achieved.