High Temperature Microelectronics Research Articles

Fatigue Testing of Copper Nanoparticle-Based Joints and Bonds

Abstract Fused or sintered Cu nanoparticle structures are potential alternatives to solder for ultrafine pitch flip chip assembly and to sintered Ag for heat sink attach in high-temperature micro-electronics. Meaningful testing and interpretation of test results in terms of what to expect under realistic use conditions do, however, require a mechanistic picture of degradation and damage mechanisms. As far as fatigue goes, such a picture is starting to emerge. The porosity of sintered nanoparticle structures significantly affects their behavior in cycling. The very different sensitivities to parameters, compared to solder, mean new protocols will be required for the assessment of reliability. This study focused on fatigue in both isothermal and thermal cycling. During the latter, all damage occurs at the low-temperature extreme, so life is particularly sensitive to the minimum temperature and any dwell there. Variations in the maximum temperature up to 125 °C did not affect, but a maximum temperature of 200 °C led to much faster damage. Depending on particle size and sintering conditions, deformation and damage properties may also degrade rapidly over time. Our picture allows for recommendations as to more relevant test protocols for vibration, thermal cycling, and combinations of these, including effects of aging, as well as for generalization of test results and comparisons in terms of anticipated behavior under realistic long-term use conditions. Also, the fatigue life seems to vary with the ultimate strength, meaning that simple strength testing becomes a convenient reference in materials and process optimization.

Influence of Self-Heating Effect on I-V Dates of Party Depleted Submicron Silicon-on-Insulator CMOS Transistors at High Ambient Temperatures

To solve the problems of high temperature microelectronics the influence of the self heating effect on the I-V dates partially depleted submicron silicon–on-insulator CMOS transistor in the ambient temperature range from 525 K to 650 K is discussed. Approach consists in combination of experimental data and of computational simulating results. For simulation of electrothermal characteristics of SOI CMOS transistor is considered three-layered structure. Temperature distribution is calculated numerically using iterative algorithm in conjunction with software COMSOL Multiphysics. I-V dates of SOI CMOS transistors are calculated by means of two-dimensional models for n-and p-channel transistors of Sentaurus TCAD developed in the system of instrument and technological modelling. TCAD models are calibrated on experimental characteristics for 525 K. It is shown that with growth of ambient temperature the self-heating mechanism contribution consistently decreases. By results of modeling it is established that self-heating contributions at supply voltages 5.5 V to decreases for n-transistor in 2.8 times, p-transistor in 2.2 times. The relative decline of current n-type transistor for reduced from 11.6% to 5.5% and for p-type with 15% to 9%. However, different dynamics of current recession for n-and p-transistors is significant for analog applications that need to be considered at high-temperature circuit design. The proposed methodology allows to critically assess the contribution of the self-heating mechanism on the I-V dates for a wide range of high temperatures and supply voltages. Underestimating this fact leads to unreasonable values for the maximum temperature and limit of thermal stability for the separate SOI CMOS transistor. In total this can be a prerequisite for a significant simplification of the design of not only the chip construction but also the whole electronic Board.

Enhanced thermal stability by introducing TiN diffusion barrier layer between W and SiC

AbstractThe combination of W and SiC has many applications such as a hot cell of a thermionic energy converter, nuclear material, and high temperature microelectronics. In this study, a 2 µm thick TiN film is introduced as a diffusion barrier between SiC and W to avoid the inter‐diffusion reaction at high temperature. The effect of annealing temperature on the surface morphology and microstructure of the TiN film is studied to explore its high temperature stability. Then 500 nm W film is sputtered on the TiN film to characterize the inter‐diffusion and stability of the W/TiN/SiC multilayer at 1100°C by XRD, Raman spectroscopy and cross‐sectional EDS mapping techniques. The results indicate that the W/TiN/SiC multilayer is very stable even when heated at 1100°C for 25 hours.

Конструктивно-технологические особенности элементов тестовых структур для высокотемпературной микроэлектроники

Конструктивно-технологические особенности элементов тестовых структур для высокотемпературной микроэлектроники

Electrical Performance of a 32-I/O HTCC Alumina Package for High-Temperature Microelectronics

A high-temperature cofired ceramic (HTCC) alumina material was previously electrically tested at temperatures up to 550°C and demonstrated improved dielectric performance at high temperatures compared with the 96% alumina substrate that we used before, suggesting its potential use for high-temperature packaging applications. This article introduces a prototype 32-input/output (I/O) HTCC alumina package with platinum conductor for 500°C low-power SiC-integrated circuits. The design and electrical performance of this package, including parasitic capacitance and parallel conductance of neighboring I/Os from 100 Hz to 1 MHz in a temperature range from room temperature to 550°C, are discussed in detail. The parasitic capacitance and parallel conductance of neighboring I/Os of this package in the entire frequency and temperature ranges measured do not exceed 1.5 pF and 0.05 μS, respectively. SiC-integrated circuits using this package and a compatible alumina circuit board have been successfully tested at 500°C for more than 3,736 h continuously, and at 700°C for more than 140 h. Some test examples of SiC-integrated circuits with this packaging system are presented.

Superior Temperature-Sensing Performance in Cladding-Modulated Si Waveguide Gratings

This paper presents a silicon photonic temperature sensor based on a complementary metal-oxide-semiconductor (CMOS) compatible cladding-modulated (CladMod) grating design on the silicon-on-insulator platform. The resulting device achieves narrow-band reflection (Δλ = 0.63 nm), a high extinction ratio (21 dB), high temperature sensitivity (83.4 pm/°C), and a wide temperature-sensing range. More importantly, this grating design allows stable reflection bandwidth $\rm{(\Delta \lambda / \Delta W}_{\rm{g}}\,\rm{ = 0.013)}$ , Bragg wavelength $\rm{(\lambda }_{\rm{B }}\rm{/ \Delta W}_{\rm{g}}\,\rm{ = 0.002)}$ , and temperature sensitivity $\rm{(\delta \lambda / \delta T/ \Delta W}_{\rm{g}}\,\rm{ = - 1.3\times 10}^{- 5}\rm{ K}^{- 1}\rm{)}$ against variations in grating width. This level of temperature-sensing performance is difficult to achieve using a strip/slab-type grating or microring resonator. The CladMod gratings were further implemented on a polysilicon gate in a standard bulk CMOS process, thereby enabling integration with other microelectronic devices to serve as an on-chip distributed temperature-sensing element This approach shows considerable promise for applications such as future photonic-electronic integrated circuits requiring in situ temperature monitoring for wavelength stabilization, or high-temperature microelectronics where silicon bandgap temperature sensors are unable to operate properly

Thermal Stability and Mechanical Properties of Organo-Soluble and Processable Polyimides for High-Temperature Materials

ABSTRACTA new series of organo-soluble polyimides with pendant groups of methoxy or methyl of azomethine diamine were synthesized through two-step process by chemical imidization. Such polyimides were tested for thermal and mechanical properties. Their thermal stability was studied in terms of temperature at 10% weight loss which ranged between 475 and 498°C with Tg around 240–278°C. Activation energy, enthalpy of the polyimides were calculated and ranged 31.12–43.59 kJmol−1 and 29.46–41.93 kJmol−1. Thermal, mechanical, and thermodynamic parameters demonstrated that the resulting polyimides can hold excellent application in the fields of high-performance, advanced composites, and high-temperature microelectronics.

Конструктивно-технологические решения элементной базы кремниевой высокотемпературной микроэлектроники

Конструктивно-технологические решения элементной базы кремниевой высокотемпературной микроэлектроники

Ni-induced graphitization for enhanced long-term stability of ohmic contact to polycrystalline 3C-SiC

Stable metal contacts for SiC-based devices are required for high temperature microelectronics and microsensor devices. Ni-induced nanocrystalline graphitic carbon is introduced between Pt/Ti and n-type polycrystalline 3C-SiC as a means of forming contacts that are stable at high temperature. With the addition of an alumina protection layer, this metallization scheme is further improved and can maintain low contact resistivity after 500 h at 450 °C in air. The role of the graphitic layer in both the formation and long-term stability of the contact is investigated. Although the formation of an ohmic contact between Pt/Ti and polycrystalline 3C-SiC does not require the graphitic carbon, this interfacial layer is necessary for maintaining low contact resistivity during long-term exposure to elevated temperature.

Thermal stability of copper on Te–Ti thin films

In this letter, we demonstrate the stability of Te–Ti thin films as a barrier against Cu after thermal annealing. Te–Ti chalcogenide glass films of composition Te0.20Ti0.70O0.10 and thickness 35nm are annealed in vacuum for up to 30min at several temperatures up to 600°C. Four-point-probe analysis results show that the Cu layers are stable up to 500°C, with abnormal increases in resistance after annealing at 600°C. The Te–Ti thin film serves as a barrier to thermal Cu diffusion up to 500°C, as revealed using Rutherford backscattering spectrometry. X-ray diffractometry indicates Cu grain growth up to 500°C and phase instability of the Te–Ti barrier at 600°C. These results indicate the potential of Te–Ti thin films as a copper diffusion barrier in high temperature microelectronics and integrated circuits.

Surface Characterization of Silicon Carbide Following Shallow Implantation of Platinum Ions for High Temperature Hydrogen Sensing Applications

ABSTRACTSilicon carbide is a promising wide-bandgap semiconductor intended for use in fabrication of high temperature, high power, and fast switching microelectronics components running without cooling. For hydrogen sensing applications, silicon carbide is generally used in conjunction with either palladium or platinum, both of them being good catalysts for hydrogen. Here we are reporting on the temperature-dependent depth profile modifications of tungsten electrical contacts deposited on silicon carbide substrates.

Single crystal 6H-SiC MEMS fabrication based on smart-cut technique

A new single crystal silicon carbide (SiC) MEMS fabrication process is developed using a proton-implantation smart-cut technique. A 6H-SiC layer with 1.3 µm thickness has been achieved over an oxidized silicon substrate using the proposed technique. TEM analyses of the silicon carbide thin film reveal single crystal characteristics, which is attractive for potential integration of MEMS devices with high-temperature microelectronics in the same structural layer for harsh environment applications. Implant-induced defect density in the silicon carbide can be substantially reduced to a negligible level through high-temperature annealing. Prototype single crystal 6H-SiC MEMS devices, such as strain sensors, have been successfully fabricated as demonstration vehicles for future harsh-environment micro-system implementation.

Surface Characterization of Silicon Carbide Following Shallow Implantation of Palladium Ions

ABSTRACTSilicon carbide is a promising wide-bandgap semiconductor intended for use in fabrication of high temperature, high power, and fast switching microelectronics components running without cooling. For hydrogen sensing applications, silicon carbide is generally used in conjunction with either palladium or platinum, both of them being good catalysts for hydrogen. Here we are reporting on the temperature-dependent surface morphology and depth profile modifications of Au, Ti, and W electrical contacts deposited on silicon carbide substrates implanted with 20 keV Pd ions.

Plasma etching and patterning of CVD diamond at

Oxidation resistance of diamond is an important characteristic to be considered in high-temperature microelectronics and other applications. We have tested the stability of CVD diamond by exposing it to Ground State Atomic Oxygen (GSAO, O) at a temperature of 74°C. Polycrystalline diamond is quite stable at this temperature using O. We have also tested the stability of diamond using Excited State Atomic Oxygen (ESAO, O*). Initially, CVD diamond was exposed to O* for 15 min at 63°C, and diamond etching was observed. We have also carried out the experiments at different time intervals such as 30 and 45 min. The etching rate of the polycrystalline diamond using O* is ≈ 0.2–0.25 m/min at 63°C. We have successfully patterned the diamond (polycrystalline and single crystal) using a Ni mask by exposing the sample to O* for a longer time. O* etched the diamond uniformly in all the directions of the diamond crystal as opposed to the molecular oxygen. Stability of the single crystal diamond has been tested using O* by using Ni mask material. We were able to etch the single crystal diamond (type IIa, 100 orientation) quite uniformly. The etching rate of single crystal diamond using O* was observed to be 0.3 m/min.

Silicon carbide for high-temperature microelectronics: recent advances in material growth via gas source MBE and device research

Thin films of silicon carbide (SiC) have been grown at 1000–1500 °C on vicinal and on-axis α(6H)-SiC(0001) substrates by gas-source molecular beam epitaxy (GSMBE). Growth using only SiH 4 and C 2H 4 resulted in 3C-SiC(111) epilayers under all deposition conditions and substrate orientations. With the addition of H 2, films of 6H-SiC(0001) were deposited on the vicinal substrates at deposition temperatures ≥ 1350 °C. Kinetic analysis showed all depositions to be surface reaction controlled. In situ doping was achieved by intentional introduction of nitrogen and aluminum into the growing crystals. SiC-based microelectronic devices operable at elevated temperatures, including several types of power metal oxide semiconductor field effect transistors (MOSFETs), bipolar transistors, and thyristors have been fabricated. The properties of selected devices and the circuits made from them are described.

Plasma Etching and Patterning of CVD Diamond at

AbstractOxidation resistance of diamond is an important characteristic to be considered in many high temperature microelectronics and other applications. We have tested the stability of CVD diamong by exposing to Ground State Atomic Oxygen (GSAO) at a temperature of 70°C. Polycrystalline diamond is quite stable at this temperature using GSAO. We have tested the stability of diamond using Excited State Atomic Oxygen (ESAO). Initially, CVD diamond was exposed to ESAO for 15 mind at 63°C and noted that the diamond was etched. We have also carried out the experiments at different time intervals such as 30 and mine. Etching rate of the diamond using ESAO is ≈ 0.2 – 0.25 μm/min at 63°C. We have successfully patterned the diamond using a Ni mask by exposing the sample to ESAO for longer time. ESAO has etched the diamond uniformly in all the directions of the diamond crystal as opposed to the molecular oxygen. Stability of the single crystal diamond has been tested using ESAO by using Ni mask material. We were able to etch the single crystal diamond (type Iia, 100 orientation) quite uniformly. An etching rate of single crystal diamond using ESAO was observed to be 0.3 μm/min.

Junction-isolated CMOS for high-temperature microelectronics

Latchup susceptibility over a temperature range of 25-315 degrees C for variations on a 1.2- mu m CMOS process is studied. A special high-performance process, including all refractory metallization, thinner epi, and higher doping levels, resulted in metal-migration immunity and doubling of the latchup holding voltage and current at 300 degrees C.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Laser Photochemical Etching of GaP in KOH Aqueous Solutions

ABSTRACTGallium phosphide is an important III-V semiconductor material for fabricating strained layer superlattices and high-speed and high-temperature microelectronics. Etching of this compound semiconductor with conventional techniques presents problems which may be solved by photon-induced electro-chemistry. We have shown that rapid localized etching of n-GaP in KOH can be driven with the UV lines of an argon-ion laser. The level and type of doping and the laser intensity determine the etch rates, which are nearly 60 nm/sec at 3500 Wcm−2 for n-doped material.