Contact resistances are inherent to any device connected to the outside world. Lowering their contribution is essential for high-performance applications. This is the case for advanced Si CMOS technologies, for which series resistance parasitics become the main performance detractor from the 14 nm node onwards [1-2]. For p-type fin and gate-all-around field effect transistors, focus is placed on Ti contacts to p-Si1-xGex source/drain (S/D) [3].Several non-equilibrium doping techniques have been explored to enhance active doping in S/D regions and decrease contact resistivities (ρc) down to ≤ 1x10-9 Ω.cm2. In most cases, low temperature doping processes are used to favor the incorporation of dopants and their activation [4]. Alternative dopants, with higher solid solubilities and advantageous segregation behaviors favoring the formation of dopant-enriched films at the metal-semiconductor interface, are also evaluated. Very low ρc values have e.g. been reported by combining Ga ion implantation in Si0.4Ge0.6 and ns laser annealing [5]; whereas in situ doping was optimized in Si1-xGex:B [6-9] and Si0.5Ge0.5:B:Ga, grown by chemical vapor deposition using metalorganic (MO) Ga precursors [4,10]. In this contribution, we highlight opportunities and challenges offered by this approach.The maximum solubility of Ga in Ge is more than 100x higher than that of B [11-12]. However, controlling the incorporation and distribution of Ga dopants in Si0.5Ge0.5(:B) is not straightforward. This relates to the tendency for Ga to segregate towards the surface, as reported in [4,10] and shown in Fig. 1(a). We rely on Si0.5Ge0.5:B:Ga co-doped epi layers in which bulk resistivity is lowered thanks to high B-doping concentrations, while contact resistivity minimization is expected from Ga segregation towards the contact region. It appears, however, that Ga surface doping concentrations significantly higher than 3E20 cm-3 are required to efficiently reduce ρc [5,13]. Targeting such high surface concentrations comes with the risk of Ga agglomeration into Ga-rich defects on S/D surfaces. Another detractor lies in the possible consumption of superficial Ga during native oxide removal preceding contact processing. Results presented in Fig. 1(b) suggest such a ~ 10x decrease in Ga concentration close to the S/D surface after native oxide removal. Systematic investigations are underway to clarify this aspect, which could lead us to reconsider our contacting scheme.Activating high levels of Ga dopants in in situ doped epi layers is an additional challenge. Preliminary results indicate that, in the conditions explored in this work, only a small fraction of the dopants incorporated in SiGe:Ga are active. This limitation may be attributed to Ga dopants clustering or to interactions with unwanted C incorporated during growth. Fig. 1(c) illustrates our effort in reducing C incorporation in SiGe:B:Ga by utilizing 2 different Ga MO precursors, namely MO1 and MO2, while keeping all other growth parameters the same. For this test, an undoped SiGe cap was used to separate contributions from adventitious C and C really incorporated in the SiGe:B:Ga layer. Ga profiles appear to be affected by the capping, with part of the Ga dopants migrating towards the top part of the stack. C impurities are on the other hand assumed to be frozen in their original position [14]. While the level of incorporated C is not significantly affected by the choice of precursor, a shorter Ga incorporation delay, materialized by blue arrows in Fig. 1(c), and a larger [Ga] / [C] ratio are extracted from the layer grown with MO2.
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