High Speedup Factor Research Articles

Efficient computation of the geopotential gradient in graphic processing units

Efficient computation of the geopotential gradient is essential for numerical propagators, particularly in scenarios involving low Earth orbits. Conventional geopotential calculations are based on spherical harmonics series, which become computationally demanding as the degree/order increases. This computational burden can be mitigated by means of parallelized algorithms. Additionally, certain situations lend themselves to high parallelization, such as the propagation of space debris catalogs, satellite mega-constellations, or the dispersion of particles resulting from a space collision event. This paper introduces an optimized Graphics Processing Unit (GPU) implementation designed to facilitate extensive parallelization in the geopotential gradient calculation. The formulation developed in this study is not specific to any GPU. However, to illustrate the low-level optimizations necessary for an efficient implementation, we selected the Compute Unified Device Architecture (CUDA) as the dominant and de facto standard in parallel computing. Nevertheless, most of the concepts and optimizations presented in this paper are also valid for other GPU architectures. Built upon the spherical harmonic expansion using the Cunningham formulation, which is well-suited for GPU computations, our implementation offers several variants with different tradeoffs between speed and accuracy. Besides GPU double precision, we introduced a mixed precision arithmetic –a hybrid between single and double precision– that exploits GPU capabilities with a low penalty in accuracy. The proposed algorithm was implemented as a software reusable module, and its performance was evaluated against GMAT, GODOT, and Orekit astrodynamic codes. The algorithm’s accuracy in double precision is comparable to such codes. The mixed precision version showed enough accuracy for LEO satellite propagation, with around 1 m difference in four days. Testing across different CUDA architectures revealed very high speed-up factors compared to a single CPU, reaching a speed-up of 645 for the mixed precision variant and 450 for the double precision one in the propagation of about 3200 objects with a geopotential of degree/order 126 × 126 using an A100 GPU device.

Large-width machine learning algorithm

We introduce an algorithm, called Large Width (LW), that produces a multi-category classifier (defined on a distance space) with the property that the classifier has a large ‘sample width.’ (Width is a notion similar to classification margin.) LW is an incremental instance-based (also known as ‘lazy’) learning algorithm. Given a sample of labeled and unlabeled examples, it iteratively picks the next unlabeled example and classifies it while maintaining a large distance between each labeled example and its nearest-unlike prototype. (A prototype is either a labeled example or an unlabeled example which has already been classified.) Thus, LW gives a higher priority to unlabeled points whose classification decision ‘interferes’ less with the labeled sample. On a collection UCI benchmark datasets, the LW algorithm ranks at the top when compared to 11 instance-based learning algorithms (or configurations). When compared to the best candidate from instance-based learners, MLP, SVM, decision tree learner (C4.5) and Naive Bayes, LW is ranked at second place after only MLP which comes at first place by a single extra win against LW. The LW algorithm can be implemented in parallel distributed processing to yield a high speedup factor and is suitable for any distance space, with a distance function which need not necessarily satisfy the conditions of a metric.

Reduced basis method for managed pressure drilling based on a model with local nonlinearities

AbstractTo circumvent restrictions of conventional drilling methods, such as slow control actions and inability to drill depleted reservoirs, a drilling method called managed pressure drilling (MPD) has been developed. In MPD, single‐phase flow processes can be modeled as a feedback interconnection of a high‐order linear system and a low‐order nonlinear system. These nonlinearities appear locally both inside and at the boundaries of the computational domain. To obtain a fast simulation platform for real‐time purposes (eg, online model‐based controller implementation), model order reduction is required for MPD. However, the local nonlinearities render applying model order reduction techniques challenging. In this study, a new approach is proposed to deal with such nonlinearities within the reduced basis (RB) context and it is successfully tested on a model for MPD. Contrary to the classical RB technique, the proposed approach not only does not generate nonphysical spikes at the locations of these local nonlinearities but also yields high speedup factors. The obtained reduced‐order model can be used for efficient online simulation and controller design for drilling systems with MPD.

Massive parallelization of approximate nearest neighbor search on KD-tree for high-dimensional image descriptor matching

To overcome the high computing cost associated with high-dimensional digital image descriptor matching, this paper presents a massively parallel approximate nearest neighbor search (ANNS) on K-dimensional tree (KD-tree) on the modern massively parallel architectures (MPA). The proposed algorithm is of comparable quality to traditional sequential counterpart on central processing unit (CPU). However, it achieves a high speedup factor of 121 when applied to high-dimensional real-world image descriptor datasets. The algorithm is also studied for factors that impact its performance to obtain the optimal runtime configurations for various datasets. The performance of the proposed parallel ANNS algorithm is also verified on typical 3D image matching scenarios. With the classical local image descriptor signature of histograms of orientations (SHOT), the parallel image descriptor matching can achieve speedup of up to 128. Our implementation will potentially benefit realtime image descriptor matching in high dimensions.

360° video stabilization

We present a hybrid 3D-2D algorithm for stabilizing 360° video using a deformable rotation motion model. Our algorithm uses 3D analysis to estimate the rotation between key frames that are appropriately spaced such that the right amount of motion has occurred to make that operation reliable. For the remaining frames, it uses 2D optimization to maximize the visual smoothness of feature point trajectories. A new low-dimensional flexible deformed rotation motion model enables handling small translational jitter, parallax, lens deformation, and rolling shutter wobble. Our 3D-2D architecture achieves better robustness, speed, and smoothing ability than either pure 2D or 3D methods can provide. Stabilizing a video with our method takes less time than playing it at normal speed. The results are sufficiently smooth to be played back at high speed-up factors; for this purpose we present a simple 360° hyperlapse algorithm that remaps the video frame time stamps to balance the apparent camera velocity.

Implementation and efficiency analysis of parallel computation using OpenACC: a case study using flow field simulations

ABSTRACTThe Open Accelerator (OpenACC) application programming interface is a relatively new parallel computing standard. In this paper, particle-based flow field simulations are examined as a case study of OpenACC parallel computation. The parallel conversion process of the OpenACC standard is explained, and further, the performance of the flow field parallel model is analysed using different directive configurations and grid schemes. With careful implementation and optimisation of the data transportation in the parallel algorithm, a speedup factor of 18.26× is possible. In contrast, a speedup factor of just 11.77× was achieved with the conventional Open Multi-Processing (OpenMP) parallel mode on a 20-kernel computer. These results demonstrate that optimised feature settings greatly influence the degree of speedup, and models involving larger numbers of calculations exhibit greater efficiency and higher speedup factors. In addition, the OpenACC parallel mode is found to have good portability, making it easy to implement parallel computation from the original serial model.

An Analytical Hessian and Parallel-Computing Approach for Efficient Dynamic Optimization Based on Control-Variable Correlation Analysis

The approach of combined multiple-shooting with collocation is efficient for solving large-scale dynamic optimization problems. The aim of this work was to further improve its computational performance by providing an analytical Hessian and realizing a parallel-computing scheme. First, we derived the formulas for computing the second-order sensitivities for the combined approach. Second, a correlation analysis of control variables was introduced to determine the necessity of employing the analytical Hessian to solve an optimization problem. Third, parallel computing was implemented thanks to the nature of the combined approach, because the solutions of model equations and evaluations of both first-order and second-order sensitivities for individual time intervals are decoupled. Because these computations are expensive, a high speedup factor was gained through the parallelization. The performance of the proposed analytical Hessian, correlation analysis, and parallel computing is demonstrated in this articl...

Multilevel MPSoC Performance Evaluation: New ISSPT Model

To deploy the enormous hardware resources available in Multi Processor Systems-on-Chip (MPSoC) efficiently, rapidly and accurately, methods of Design Space Exploration (DSE) are needed to evaluate the different design alternatives. In this paper, we present a framework that makes fast simulation and performance evaluation of MPSoC possible early in the design flow, thus reducing the time-to-market. In this framework and within the Transaction Level Modeling (TLM) approach, we present a new definition of ISS level by introducing two complementary modeling sublevels ISST and ISSPT. This later, that we illustrate an arbiter modeling approach that allows a high performance MPSoC communication. A round-robin method is chosen because it is simple, minimizes the communication latency and has an accepted speed-up. Two applications are tested and used to validate our platform: Game of life and JPEG Encoder. The performance of the proposed approach has been analyzed in our platform MPSoC based on multi-MicroBlaze. Simulation results show with ISSPT sublevels gives a high simulation speedup factor of up to 32 with a negligible performance estimation error margin. DOI: http://dx.doi.org/10.11591/telkomnika.v15i1.8085

The Index-based Subgraph Matching Algorithm with General Symmetries (ISMAGS): exploiting symmetry for faster subgraph enumeration.

Subgraph matching algorithms are used to find and enumerate specific interconnection structures in networks. By enumerating these specific structures/subgraphs, the fundamental properties of the network can be derived. More specifically in biological networks, subgraph matching algorithms are used to discover network motifs, specific patterns occurring more often than expected by chance. Finding these network motifs yields information on the underlying biological relations modelled by the network. In this work, we present the Index-based Subgraph Matching Algorithm with General Symmetries (ISMAGS), an improved version of the Index-based Subgraph Matching Algorithm (ISMA). ISMA quickly finds all instances of a predefined motif in a network by intelligently exploring the search space and taking into account easily identifiable symmetric structures. However, more complex symmetries (possibly involving switching multiple nodes) are not taken into account, resulting in superfluous output. ISMAGS overcomes this problem by using a customised symmetry analysis phase to detect all symmetric structures in the network motif subgraphs. These structures are then converted to symmetry-breaking constraints used to prune the search space and speed up calculations. The performance of the algorithm was tested on several types of networks (biological, social and computer networks) for various subgraphs with a varying degree of symmetry. For subgraphs with complex (multi-node) symmetric structures, high speed-up factors are obtained as the search space is pruned by the symmetry-breaking constraints. For subgraphs with no or simple symmetric structures, ISMAGS still reduces computation times by optimising set operations. Moreover, the calculated list of subgraph instances is minimal as it contains no instances that differ by only a subgraph symmetry. An implementation of the algorithm is freely available at https://github.com/mhoubraken/ISMAGS.

Finite strain viscoelasticity: how to consistently couple discretizations in time and space on quadrature-point level for full order $$p \ge 2$$ and a considerable speed-up

In computational viscoelasticity, the spatial finite element discretization for the global solution of the weak form of the balance of momentum is coupled to the temporal discretization for solving local initial value problems (IVP) of viscoelastic flow. In this contribution we show that this global-local or space-time coupling is consistent, if the total strain tensor as the coupling quantity exhibits the same approximation order $$p$$ in time as the Runge---Kutta (RK) integration algorithm. To this end we construct interpolation polynomials, based on data at $$t_{n+1}$$ , $$t_{n}$$ , $$\ldots $$ , $$t_{n+2-p}$$ , $$p\ge 2$$ , which provide consistent strain data at RK stages. This is a generalization of the idea proposed in (Eidel and Kuhn, Int J Numer Methods Eng 87(11):1046---1073, 2011). For lower-order strain interpolation, time integration exhibits order reduction and therefore low efficiency. For consistent strain interpolation, the adapted RK methods up to $$p=4$$ obtain full convergence order and thus approve the novel concept of consistency. High speed-up factors substantiate the improved efficiency compared with Backward-Euler.

A reduced domain pool based on DCT for a fast fractal image encoding

Fractal image compression is time consuming due to the search of the matching between range and domain blocks. In order to improve this compression method, we propose firstly, in this paper, a fast method for reducing the computational complexity of fractal encoding by reducing the size of the domain pool. This reduction is based on the lowest horizontal and vertical DCT coefficients of domain blocks. The experimental results on the test images show that the proposed method reduce the time computation and reach a high speedup factor without decreasing the image quality. Secondly, we combine our method to the AP2D approach which uses two domain pools in two steps of encoding. A more reduction of encoding time is obtained without decreasing the image quality.

Parallel Data Migration Framework on Linux Clusters

A rapid growth in the storage capacity requirements at a computer center can lead to the installation of additional disk racks. The challenging task is not the installation, but to migrate old data to the new storage pools. A framework to parallelize the data migration process, using Linux clusters connected to Storage Area Network storage, is presented. A Linux tool to efficiently parallelize data migration, utilizing the High Performance Computing environment, is developed. Results show that using multiple nodes and multiple data copying streams per node achieves significant speedup factors over manual copying. The tool is demonstrated on four nodes using 178 data copying streams, achieving a speedup factor close to seven. The tool is scalable and capable of higher speedup factors with more available data moving nodes.

Multi-Level Simulation Platform of Network-on-Chip forDesign Space Exploration

As multi-core architectures scale in size, on-chip networks (NoC) have become the main communication architecture, replacing dedicated interconnections and shared buses. NoC architectures have to deliver good latency-throughput performance in the face of very tight power and area budgets. Live power measurement is necessary for both hardware and software designer, but it requires too much time for simulation, especially for embedded systems. The major contribution of this paper is to present a simple method for rapidly estimating power consumption and find the hotspots in the network-on-chip(NoC) at two different resolutions. In addition to the low-level cycle-accurate simulation, we also build a high-level NoC simulation platform for multi-core SoCs, called TLM-PVT level. The platform, implemented by SystemC, allows early exploration of the performance and power consumption of NoC, which is able to handle arbitrary topologies and routing schemes. In the experiments, we compare the implemented high-level simulation platform with cycle-accurate simulator. The results show that the TLM-PVT simulator gives a high simulation speedup factor with a negligible performance estimation error margin.

Convergence analysis of generalized serial message-passing schedules

Schedule is the order of passing messages between vertices of the bipartite graph defining an LDPC code in the process of decoding. Schedules affect the rate of decoding convergence. New efficient generalized serial schedules are described and analyzed, exhibiting significantly faster convergence compared to previously known schedules. For the proposed schedules, combinatorial and probabilistic analysis is presented, explaining the fast convergence observed in simulations. Using it, LDPC ensembles for which significantly better convergence rates can be achieved are identified. Specific code constructions from lifted graphs are further proposed, efficiently supporting the schedules. Examples based on regular LDPC codes are provided, in which the schedules achieve convergence speedup factors of up to 6 in comparison with the flooding schedule. Higher speedup factors are predicted by the analysis for irregular codes.

Spatial domain method for the design of RF pulses in multicoil parallel excitation

Parallel excitation has been introduced as a means of accelerating multidimensional, spatially-selective excitation using multiple transmit coils, each driven by a unique RF pulse. Previous approaches to RF pulse design in parallel excitation were either formulated in the frequency domain or restricted to echo-planar trajectories, or both. This paper presents an approach that is formulated as a quadratic optimization problem in the spatial domain and allows the use of arbitrary k-space trajectories. Compared to frequency domain approaches, the new design method has some important advantages. It allows for the specification of a region of interest (ROI), which improves excitation accuracy at high speedup factors. It allows for magnetic field inhomogeneity compensation during excitation. Regularization may be used to control integrated and peak pulse power. The effects of Bloch equation nonlinearity on the large-tip-angle excitation error of RF pulses designed with the method are investigated, and the utility of Tikhonov regularization in mitigating this error is demonstrated.

Analysis of an Improved Split-Step Algorithm for Simulating Optical Transmission Systems

The standard Split-Step algorithm for calculating the signal transmission through optical fibres is significantly accelerated without relevant loss of accuracy by applying IIR filters as well as Fourier transformations for the linear operator. Depending on the system topology, high speed-up factors can be achieved by switching back and forth between time and frequency domain algorithms for the linear operator. Two different IIR filters are applied for calculating linear and parabolic dispersion. The efficiency of this algorithm in combination with an innovative step-size allocation method is evaluated.

The token-skipping channel access scheme for bus networks

Abstract A major disadvantage of the standard token-bus network architecture is the delay involved in passing the token through idle stations. A modified token-passing scheme is described that minimizes this overhead by bypassing idle stations. This scheme requires very little additional hardware over the proposed IEEE 802.4 channel-access protocol and has this proposed standard protocol as one of its limiting cases. Simulation studies of this scheme show significant improvement of delay-throughput characteristics for practical load ranges. For example, for throughputs up to about 65%, a network with 100 nodes with Poisson arrivals and symmetric load distribution among nodes has a mean delay of less than half that of a similar network using the conventional token-passing scheme. Under asymmetric load distribution among nodes, even higher speedup factors can be achieved.