High-speed Transistors Research Articles

The Effect оf Laser Radiation оn Functional Properties of MOS Structures

The electrophysical properties of instrument MOSFET structures (capacitor, field-effect transistor with an isolated gate and an induced channel, CMOS integrated circuit) when exposed to unmodulated laser radiation are studied. Static and dynamic characteristics were measured. The theoretical study was carried out using the developed SPICE models and numerical experiments. An expression is obtained for the volt-ampere characteristic of a field-effect transistor operating in a mode with constant optical illumination. It is shown that the characteristics of the structures are determined by the generation and recombination of nonequilibrium charge carriers, the field effect, the photovoltaic effect in p—n junctions, the photo-Dember effect and tunneling of charge carriers through a gate dielectric. The results of the work are of interest from the point of view of creating high-speed transistors and integrated circuits of a new type.

Nanosecond laser-induced crystallization of SiOx/Au bilayers in air and vacuum

High-quality polycrystalline silicon films on low-cost and low-temperature substrates have attracted much attention as promising materials for high-speed thin-film transistors and thin-film solar cells fabrication. To obtain poly-Si films on low temperature substrates, several concepts have been proposed. Usually the amorphous material undergoes crystallization which can be achieved by various methods including solid-phase crystallization, metal-induced crystallization or liquid-phase crystallization. In this work, we tried to combine the advantages of metal-induced crystallization and liquid-phase crystallization. To achieve this we explored the nanosecond laser crystallization of a bilayer structure consisting of Au and SiO0.1 layers with thicknesses of 30 nm and 130 nm, respectively. The study reveals that when exposed to 532 nm wavelength radiation leads to its destruction due to rupture. On the other hand, when subjected to 1064 nm wavelength radiation, no similar material behavior is observed, and the measured modification threshold is 0.15 J/cm2, representing a 40 % reduction compared to SiO0.1 film without gold. It is demonstrated that at laser fluences of 0.35 J/cm2 and higher, the treatedsurfaceinair becomes enriched with silicon dioxidenanoporous coating, attributed to the return of evaporation products to the target surface. Theoretical modeling, assuming thermal evaporation of the coating, suggests that the undesirable nanoporous layer formation can be avoided.

A Novel High-Speed Split-Gate Trench Carrier-Stored Trench-Gate Bipolar Transistor with Enhanced Short-Circuit Roughness.

A novel high-speed and process-compatible carrier-stored trench-gate bipolar transistor (CSTBT) combined with split-gate technology is proposed in this paper. The device features a split polysilicon electrode in the trench, where the left portion is equipotential with the cathode. This design mitigates the impact of the anode on the trench gate, resulting in a reduction in the gate-collector capacitance (CGC) to improve the dynamic characteristics. On the left side of the device cell, the P-layer, the carrier-stored (CS) layer and the P-body are formed from the bottom up by ion implantation and annealing. The P-layer beneath the trench bottom can decrease the electric field at the bottom of the trench, thereby improving breakdown voltage (BV) performance. Simultaneously, the highly doped CS layer strengthens the hole-accumulation effect at the cathode. Moreover, the PNP doping layers on the left form a self-biased pMOS. In a short-circuit state, the self-biased pMOS turns on at a certain collector voltage, causing the potential of the CS-layer to be clamped by the hole channel. Consequently, the short-circuit current no longer increases with the collector voltage. The simulation results reveal significant improvements in comparison with the conventional CSTBT under the same on-state voltage (1.48 V for 100 A/cm2). Specifically, the turn-off time (toff) and turn-off loss (Eoff) are reduced by 38.4% and 41.8%, respectively. The short-circuit current is decreased by 50%, while the short-circuit time of the device is increased by 2.46 times.

Low-Temperature Growth of InGaAs Quantum Wells Using Migration-Enhanced Epitaxy.

The growth of InGaAs quantum wells (QWs) epitaxially on InP substrates is of great interest due to their wide application in optoelectronic devices. However, conventional molecular beam epitaxy requires substrate temperatures between 400 and 500 °C, which can lead to disorder scattering, dopant diffusion, and interface roughening, adversely affecting device performance. Lower growth temperatures enable the fabrication of high-speed optoelectronic devices by increasing arsenic antisite defects and reducing carrier lifetimes. This work investigates the low-temperature epitaxial growth of InAs/GaAs short-period superlattices as an ordered replacement for InGaAs quantum wells, using migration-enhanced epitaxy (MEE) with low growth temperatures down to 200-250 °C. The InAs/GaAs multi-quantum wells with InAlAs barriers using MEE grown at 230 °C show good single crystals with sharp interfaces, without mismatch dislocations found. The Raman results reveal that the MEE mode enables the growth of (InAs)4(GaAs)3/InAlAs QWs with excellent periodicity, effectively reducing alloy scattering. The room temperature (RT) photoluminescence (PL) measurement shows the strong PL responses with narrow peaks, revealing the good quality of the MEE-grown QWs. The RT electron mobility of the sample grown in low-temperature MEE mode is as high as 2100 cm2/V∗s. In addition, the photoexcited band-edge carrier lifetime was about 3.3 ps at RT. The high-quality superlattices obtained confirm MEE's effectiveness for enabling advanced III-V device structures at reduced temperatures. This promises improved performance for applications in areas such as high-speed transistors, terahertz imaging, and optical communications.

Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors

Gaussian DOS Charge-Based DC Compact Modeling of High-Speed Organic Transistors

OPTICALLY PUMPED BIPOLAR TRANSISTOR

The properties of a bipolar npn transistor were studied when exposed to unmodulated incoherent radiation created by a “white” LED. The static and dynamic characteristics of the transistor were measured at various exposure intensities. It is shown that the change in the characteristics of the transistor under optical influence is due to an increase in the lifetime of nonequilibrium charge carriers and the photovoltaic effect in p-n junctions. For these reasons, the gain increases, the switching threshold decreases, and the transistor speed increases. The results obtained are applicable both to the creation of high-speed transistors and integrated circuits of a fundamentally new type.

Low-Pressure CVD Synthesis of Tetragonal Borophene Single-Crystalline Sheets with High Ambient Stability

Being a typical graphene-like two-dimensional (2D) material, borophene has received a lot of attention due to its low density, high electron mobility, large Young’s modulus, and good chemical stability. Compared with the corresponding bulk counterparts, 2D borophene has larger specific surface area, higher conductivity, and smaller work function, finding potential applications in high-speed transistors, optoelectronic detection, field emission (FE), and mechanical enforcement areas. In this paper, 2D tetragonal borophene sheets with high ambient stability have been successfully fabricated on the surface of 1 cm2 copper foil using a developed low-pressure chemical vapor deposition (LPCVD) method. The vapor–solid mechanism was used to comprehend the formation of the tetragonal borophene sheets. The electrical conductivity of individual borophene sheets ranged from 4 to 5 × 10–4 S/cm, and the band gap was about 2.1 eV, suggesting their narrow semiconductive nature. Also, the maximum FE current of individual borophene sheets was close to 1 μA, and their emission properties enhanced with the decreasing sheet thickness, comparable to many other nanomaterials with excellent FE performances. More interestingly, individual borophene sheets were found to retain good enough electrical transport and FE behaviors even if they experienced several days’ atmospheric conservations. Our research results suggest that the LPCVD-grown borophene may be a promising building block for constructing high-performance nanodevices with good ambient stability.

Modulation of Schottky barrier at metal/Ge contacts by phosphoric acid coating and excimer laser annealing

Germanium is an attractive material for advanced devices such as high speed transistors and high efficiency optical devices. To realize the high performance operation, low resistive contacts to Ge are required. However, the Fermi level in Ge at metal/Ge contacts is often pinned near the valance band edge. This Fermi level pinning generates high Schottky barrier heights at metal/Ge contacts regardless the work function of the metals, which results in low resistive contacts to p-type Ge but high resistive contacts to n-type Ge. Thus, a technique for modulating the Schottky barrier heights at metal/Ge contacts is desired. For this purpose, effects of surface treatments of Ge using phosphoric acid coating and excimer laser annealing (LA) were investigated. After LA without phosphoric acid coating, the reverse current of the Al/n-type Ge contacts is increased by an order of magnitude. On the other hand, the reverse current is significantly increased by three orders of magnitude after LA with phosphoric acid coating. Here, the Schottky barrier heights are decreased from 0.56 to 0.50 eV and from 0.59 to 0.49 eV after LA for samples without and with phosphoric acid coating, respectively. These phenomena are attributed to formation of very thin GeOx surface layers and very shallow doped layers having very high P concentrations, respectively. This technique is useful for modulation of the Fermi level pinning for metal/Ge contacts with the low thermal budget.

New Insights Into Noise Characteristics of Hot Carrier Induced Defects in Polysilicon Emitter Bipolar Junction Transistors and SiGe HBTs

Low frequency (LF) noise is a powerful and nondestructive technique for evaluating the oxide-semiconductor interface and an effective evaluating tool in characterizing electronic device’s structure and reliability. In this study, we present a systematic analysis of the striking abnormal 1/f noise behavior of the hot carrier induced defects in highspeed polysilicon emitter bipolar transistors (PE-BJTs) and SiGe HBTs. Here, the comparative results before and after hot carrier degradation reveal that low frequency noise spectra are not correlated with the density and distribution of the interfacial defects, which related to Si dangling bonds reside at the SiO2/Si interface in PE-BJTs and SiGe HBTs.

Design of Polymer-Based Trigate Nanoscale FinFET for the Implementation of Two-Stage Operational Amplifier

The major motivation behind transistor scaling is the requirement for high-speed transistors with lower fabrication costs. When the fin thickness or breadth is smaller than 10 nm in a trigate FET, charges travel in a nonconfined fashion, resulting in the creation of energy subbands and causing volume inversion. In comparison to the carrier near a surface inversion layer, volume inversion experiences less interface scattering. In large-scale integrations, we have focused on developing a 3D model for surface potential by establishing the three-dimensional Poison’s equation and building a unique fin field-effect transistor (FinFET) structure. In this context, there is a growing interest in developing a low-cost, simple solution that combines plastic (polymer) as a substrate and organic materials to create electronics such as monitors and sensors. The research examines characteristics such as silicon width, oxide thickness, doping concentration, metal work-function about gate, and various surface potentials. For different circuit configurations, it also examines the DC and AC characteristics of the FinFET structure. A differential amplifier is built for RF application based on the device specifications. This work is aimed at improving the semiconductor design structure by adjusting device parameters, analyzing the results, establishing the best FinFET device preferences, and selecting an application for the optimized device. The 3D Poisson’s equation may be used to create an analytical model of a trigate nanosize FinFET, which can then be tested using a TCAD simulator. By constructing such a FinFET, we can structure and analyze various electrostatic parameters. To facilitate the creation of FinFET-based circuits, including product development, a novel transistor needs a creative device basis. The infrastructure’s support denotes a computationally advantageous numerical model that accurately depicts a FinFET. The work presents a compact model for semiconductor manufacturing that permits separate IC productions while achieving higher levels of excellence and using less power. The design outperforms the CMOS by 22.7% in gain, 31.48% in power consumption, and 12.72% in CMRR, while operating at a 5 GHz unity gain frequency.

Monolithic Integration, Performance, and Comparison of Self-Aligned and Conventional IGZO Thin-Film Transistors on a Flexible Substrate

Flexible electronics, most prominently thin-film transistors (TFTs) on plastic substrates are considered the prime building block for the realization of innovative wearable systems. Two of the currently most successful fabrication processes of transistors on free standing polymer foils are large-area compatible devices structured by conventional UV lithography and high-speed transistors realized by self-alignment. Here, both processes, based on InGaZnO technology, are combined for the first time. This demonstrates their compatibility, but also showcases the differences between the resulting devices. Concerning the geometry, TFTs with the same nominal designed channel length of 1.5 μm, exhibit real channel length of 1.5 μm (self-aligned) and 4.5 μm (conventional). Furthermore, the integrated side by side fabrication enables the electrical comparison of both types of TFTs excluding external factors. While all TFTs exhibit similar threshold voltages around 0 V and excellent on/off ratios of ≈10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">10</sup> , conventional TFTs are easier to fabricate, and have comparably higher mobilities up to 16 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . At the same time, self-aligned TFTs demonstrate better AC performance, demonstrating a maximum oscillation frequency of 216 MHz. This integration shows new possibilities for the realization of complex systems made from building blocks optimized for reliability and speed.

Decrease in crystallization temperature of β-Ga2O3 in nanowire structure

We have found that Ga2O3 nanowires (NWs) become β-type at about 600 °C, which is much lower than 900 °C known for bulk and thin films. The raw NWs were chemically synthesized at 70 °C in a flask. When the NWs were heat-treated at 400 °C or lower, ε-Ga2O3 was formed, and when heat-treated at 600 °C or higher, β-Ga2O3 was formed. The phase transition from ε-type to β-type occurred at around 500 °C during the temperature rise. Chemical synthesis and heat treatment was found to be low-cost methods for producing β-Ga2O3 NWs, which is expected to be applied to high-speed transistors and high-efficiency sensors.

Modulation Characteristics of High-Speed Transistor Lasers

The spontaneous emission recombination lifetime of carriers in the active region of transistor lasers (TLs) is significantly reduced due to the accelerated carrier transport in the base region under the collector bias. Thus, it has the potential for use as a high-speed optical fiber communication light source. The unique three-electrode structure of TL notably enriches the modulation methods of the light source. As an important parameter to measure the data transfer rate, the modulation bandwidth of TL has been studied extensively. This paper briefly analyzes the inherent characteristics and advantages of TL and then discusses the progress in the research on TL modulation characteristics. Currently, the common methods to increase the modulation rate include optimizing the device structure, intracavity photon-assisted tunneling, and adding external auxiliary circuits. Through these techniques, single quantum well GaAs- based TL can achieve error-free transmission of 22 Gb/s, and simulation data show that for InP- based TL, this can reach 40 Gb/s. Finally, the challenges faced by TL in the area of optical fiber communication are elucidated.

Cascaded Multilevel Inverter-Based Asymmetric Static Synchronous Compensator of Reactive Power

The topology of the static synchronous compensator of reactive power for a low-voltage three-phase utility grid capable of asymmetric reactive power compensation in grid phases has been proposed and analysed. It is implemented using separate, independent cascaded H-bridge multilevel inverters for each phase. Every inverter includes two H-bridge cascades. The first cascade operating at grid frequency is implemented using thyristors, and the second one—operating at high frequency is based on the high-speed MOSFET transistors. The investigation shows that the proposed compensator is able to compensate the reactive power in a low-voltage three-phase grid when phases are loaded by highly asymmetrical reactive loads and provides up to three times lower power losses in the compensator as compared with the situation when the compensator is based on the conventional three-level inverters implemented using IGBT transistors.

Graphene FET on Diamond for High-Frequency Electronics

Transistors operating at high frequencies are the basic building blocks of millimeter-wave communication and sensor systems. The high velocity and mobility of carriers in graphene can open way for ultra-fast group IV transistors with similar or even better performance than can be achieved with III-V based semiconductors. However, the progress of high-speed graphene transistors has been hampered due to fabrication issues, influence of adjacent materials, and self-heating effects. Here, we report a graphene field-effect transistor (FET) on a diamond substrate, with a $f_{max}$ up to 54 GHz for a gate length of 500 nm. The high thermal conductivity of diamond provides an efficient heat-sink, and its relatively high optical-phonon energy improves saturation velocity of carriers in the graphene channel. Moreover, we show that graphene FETs on diamond, with different gate lengths, exhibit excellent scaling behavior. These results indicate that graphene FETs on diamond technology can reach sub-terahertz frequency performance.

Ab-initio simulation of hydrogenated graphene properties

Ab-initio simulation of hydrogenated graphene properties was performed. At present, graphene is considered one of the most promising materials for the formation of new semiconductor devices with good characteristics. Graphene has been the subject of many recent investigations due to its peculiar transport, mechanical and others properties [1]. The chemical modification of graphene named as graphane has recently entered the investigation as a possible candidate to solve problems connected with the lack of a graphene bandgap. Graphane is a compound material consisting of two-dimensional graphene bonded by some atoms of hydrogen. The investigation shows that graphane has the three valley Г-М-K band structure with the Г valley, which has the smallest energy gap between the conductivity zone and the valence zone. The calculation of relative electron masses and non-parabolic coefficients in Г, М and K valleys was performed. Based on the obtained characteristics, it is possible to implement a statistical multi-particle Monte Carlo method to determine the characteristics of electron transfer in heterostructure semiconductor devices. A research on modified graphene structures is important for fundamental science and technological applications in high-speed transistor structures operating in the microwave and very high frequency ranges.

High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters

High-speed SOI junctionless transistor based on hybrid heterostructure of Si/Si0.5Ge0.5 and asymmetric spacers with outstanding analog/RF parameters

Г-L intervalley separation and electron mobility in GaAsSb grown on InP: Transport comparison with the GaInAs and GaInAsSb alloys

GaAs0.51Sb0.49 is lattice-matched to InP and finds electron transport applications in base or absorber layers in high-speed heterostructure bipolar transistors or photodiodes, because its staggered (“type-II”) band alignment with InP favors electron injection across abrupt heterojunctions. Little remains known about electron transport properties and band structure details of GaAsxSb1−x near x = 0.5. Particularly, based on the Γ-L intervalley separation in binary constituents (ΔΓL = 84 meV in GaSb and 290 meV in GaAs at 300 K), interpolation suggests a low Γ-L separation in GaAs0.51Sb0.49 before considering energy gap bowing effects. To gain insight into electron transport in GaAs0.51Sb0.49, we characterized experimental Hall electron mobilities vs carrier concentration at 300 and 77 K in n-type GaAs0.51Sb0.49, Ga0.47In0.53As, and Ga0.76In0.24As0.67Sb0.33 alloys nearly matched to InP. In marked contrast to the other two alloys, GaAs0.51Sb0.49 exhibits a sharp rise in 77 K electron mobility, which evidences L-valley de-population for lower electron concentrations. A two-band transport analysis reveals a Γ-L valley separation ΔΓL = 91 meV at 77 K, significantly lower than values recommended in the literature. Based on the reported temperature variations of ΔΓL in GaAs and GaSb, 84 &amp;lt; ΔΓL &amp;lt; 95 meV is expected at 300 K. The corresponding GaAsxSb1−x L-valley bowing parameter is cL = 1.63 eV, significantly higher than the 1.1–1.2 eV recommended in the literature. In contrast to GaAsxSb1−x, GaInAsSb grown on InP displays a strong alloy scattering, which limits its low-temperature electron mobility.

Epitaxial type-I and type-II InAs-AlAsSb core–shell nanowires on silicon

Low-bandgap semiconductor nanowires (NWs) attract considerable interest for mid-infrared (MIR) photonics and optoelectronics, where ideal candidate materials require surface-passivated core–shell systems with large tunability in band offset, lineup, and emission wavelength while maintaining close lattice-matching conditions. Here, we propose and demonstrate epitaxial InAs–AlAsSb core–shell NW arrays on silicon (Si) that offer exceptional control over both the internal strain close to lattice-matching as well as band lineups tunable between type-I and type-II, with almost no analogue in the III–V materials family. We develop direct monolithic growth of high-uniformity InAs–AlAsSb NWs with wide tunability in shell composition and employ correlated Raman scattering and micro-photoluminescence spectroscopy to elaborate the interplay among hydrostatic strain, band lineup, and emission energy of the NW core luminescence tuned from ∼0.4 to 0.55 eV. Electronic structure calculations further support the experimentally observed tunability between type-I and type-II band lineups. The Si-integrated InAs-AlAsSb NW materials system holds large prospects not only for on-chip MIR photonics but also for other applications including high-speed transistors and NW-based hot carrier solar cells.

A New High-Performance 4-Bit Code Converter and Parity Checker Using Mixed Logic Design

In modern communications, code converters and accurate data transmission are essential. This paper presents a new code converter (i.e., Binary to Gray and Gray to Binary) and Parity Checker using mixed logic design. Mixed modeling will be better to achieve low power, high speed and fewer transistors instead of considering a single logic style for array structures. It is important to note that additional metal layers are required for implementation. The HSPICE simulations have been done on these circuits with various supply voltages and frequencies. The existing circuits are compared with mixed logic design circuits and found that the proposed designs show better performance. Especially when compared with FS_XOR1 (which produces better results than others), the power consumption of Mixed logic design is reduced by 5.40%, the speed is improved by 14.89% and PDP is also decreased by 19.48% in the case of Binary to Gray. Moreover, significant improvements can be seen with other existing designs.