A New High-Performance 4-Bit Code Converter and Parity Checker Using Mixed Logic Design

Abstract

In modern communications, code converters and accurate data transmission are essential. This paper presents a new code converter (i.e., Binary to Gray and Gray to Binary) and Parity Checker using mixed logic design. Mixed modeling will be better to achieve low power, high speed and fewer transistors instead of considering a single logic style for array structures. It is important to note that additional metal layers are required for implementation. The HSPICE simulations have been done on these circuits with various supply voltages and frequencies. The existing circuits are compared with mixed logic design circuits and found that the proposed designs show better performance. Especially when compared with FS_XOR1 (which produces better results than others), the power consumption of Mixed logic design is reduced by 5.40%, the speed is improved by 14.89% and PDP is also decreased by 19.48% in the case of Binary to Gray. Moreover, significant improvements can be seen with other existing designs.