High-speed Static Random Access Memory Research Articles

Design of power efficient and reliable hybrid inverter approach based 11 T SRAM design using GNRFET technology

Designing a power efficient and high-speed static random-access memory (SRAM) cell with improved noise stability using traditional complementary metal oxide semiconductor (CMOS) devices is an arduous task. Owing to balanced electrical properties of graphene nanoribbon field-effect transistor (GNRFET), its capability to realize high performance SRAM cells need a keen exploration. This article proposes an 11-transistor GNRFET SRAM cell which deploys hybrid inverter scheme. The hybrid inverter scheme encompasses two distinct inverters, based on stacked transistors and Schmitt trigger (ST) techniques. The simulations conducted using 16 nm GNRFET model in HSPICE simulator show that proposed SRAM cell has write power, hold power, read power, write static noise margin, hold static noise margin, read static noise margin, write delay and read delay of 0.445 nW, 0.978 µW, 1.8 nW, 225 mV, 222.8 mV, 225.1 mV, 24 pS and 49.6 pS, respectively. The results obtained for proposed SRAM cell have been found to be encouraging in contrast to previously reported SRAM cells implemented using 16 nm GNRFET model. Besides this, the effect of variation in various parameters of GNRFET on performance of proposed SRAM cell has been investigated in this article. The outstanding performance results of SRAM makes its suitable for developing high performance memories devices for biomedical digital gadgets, internet of things (IoT), artificial intelligence (AI) and smart agricultural applications.

An efficient common source sense amplifier for single ended SRAM

Sense amplifiers (SA) play a vital role in supporting the read performance of static random-access memory (SRAM). Single ended SRAM has attracted importance due to low leakage current and absence of time margin compared to differential SA. This paper proposes a common source sense amplifier (CSSA) for low power single ended SRAM for read operation. The sense amplifier performs dual task by charging the bit line during pre-charge phase and amplifying the bit line during evaluation phase. The proposed CSSA shows good improvement in sensing time and power at higher number of cells per bit line (CpBL). The proposed CSSA exhibits 53%, 48%, 24%, 23%, and 41% lower sensing time for 256 CpBL and 52%, 51%, 50%, 37%, and 47% lesser power consumption than the conventional domino sensing scheme (DSS), AC coupled sense amplifier (ACSA), non-strobed regenerative sense amplifier (NSRSA), switching PMOS sense amplifier (SPSA) and trip point bit line pre-charge sensing scheme (TBPSS). The proposed CSSA occupies 18%, 25%, 53%, 61%, and 37% lesser area compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA has 88%, 88%, 85%, 91%, and 87% lesser APDP (area power delay product) compared to DSS, ACSA, SPSA, NSRSA, and TBPSS. The proposed CSSA sensing scheme is implemented and simulated in Cadence Virtuoso tool with 45 nm technology. The simulation results of CSSA prove that the proposed CSSA sense amplifier is suitable for high speed and low power SRAM architecture.

Design of high stability, low power and high speed 12 T SRAM cell in 32-nm CNTFET technology

Many researchers are trying to create a low power, high stability, and high-speed static random access memory (SRAM) cell. This paper introduces an SRAM cell consisting of 12 transistors (12 T) developed by carbon nanotube field-effect transistor (CNTFET) to support such an endeavor and be a milestone in creating a better SRAM cell. The proposed 12 T CNTFET SRAM cell is a modified Schmitt-trigger (ST)-based SRAM cell design. The ST-based SRAM cell feedback-cutting and single-ended read decupled techniques are introduced to improve the SRAM cell’s static noise margin (SNM) and access time. The presence of stacked N-CNTFETs reduces the proposed cell’s power consumption. In addition to conventional 6 T [9] and 8 T [10] SRAM cells, it has been compared with some of the existing SRAM cells such as 12 T SRAM [11], 12 T SRAM [12], 12 T SRAM [13] and 12 T SRAM [14], for calculating the relative performance of the proposed 12 T CNTFET SRAM cell design in terms of fundamental design metrics. The simulation results at 0.9 V show that compared to the afromentioned bit cells, the proposed design accomplishes low power consumption while writing, reading, and holding modes of operation. It has a high SNM during all the operations. The proposed cell has the least read access time. The power, SNM, and access time performance of the bit cells are evaluated for the variation of CNTFET parameters and reported in this article. The proposed cell is also implemented using MOSFET, and the performance of MOSFET and CNTFET is compared. The simulation is done with the HSPICE simulation tool using the Stanford University 32 nm CNTFET model.

Physics-Based Device-Circuit Cooptimization Scheme for 7-nm Technology Node SRAM Design and Beyond

This article presents a comprehensive assessment on the 6T static random access memory (SRAM) cell with 7-nm FinFET technology by implementing quantum physics-based device-circuit cooptimization. Seven key device design parameters and their multiple impacts on a 6T SRAM cell are systematically evaluated, focusing on materials band engineering, device design, circuit parameters tradeoff, and variation control. The area of SRAM cell under the same Fin quantization scheme remains constant in all evaluations. To the best of our knowledge, the most comprehensive discussion about circuit optimization from multiple device design parameters perspective is presented. Based on our cooptimization scheme, a SRAM cell is effectively designed. For a low-power and robust SRAM cell design, we achieve 56.7% reduction in leakage, 7.9% improvement in hold noise margin (HNM), 8.6% improvement in read noise margin (RNM), and 10.8% improvement in write margin (WM) at the expense of 19.3% increase in delay under design space of gate length (Lg) and spacer thickness (TSPC). For a high-speed SRAM cell design, we recommend focusing on the optimization of architecture and peripheral circuits. This framework not only has the advantages of easy implementation, technology-friendly, and high accuracy, but also suitable for path-finding researches on 5-nm node and beyond.

A Precise Implementation of Random Access Time Measurement for Embedded SRAM

With the development of semiconductor process technology and circuit design capabilities, operating frequency of random access memory has been improved dramatically. Accurate measurement of embedded memory random access time is becoming a challenge, especially for low-density embedded memory. Traditional timing measurement which connects the external ports directly to the internal ports of memory is not feasible for its low efficiency and very low precision. A new method which applied the built-in test circuit to memory access timing measurement is presented in this paper. With high-speed static random access memory testing chip fabricated with 28 nm logic process, the proposed access timing measurement circuit has been verified and proved to be accurate.

Proficient Static RAM design using Sleepy Keeper Leakage Control Transistor & PT-Decoder for handheld application

Due to their large storage capacity and small access time static random access memory (SRAM) has become a vital part in numerous VLSI chips. Low power adequate memory configuration is a standout among the most challenging issues in SRAM design. As the technology node scaling down, leakage power utilization has turned into a noteworthy issue. In this paper a novel power gating technique, namely sleepy keeper leakage control transistor technique (SK-LCT) is proposed for a handheld gadget application. The SRAM architecture has two primary components, specifically SRAM cell and sense amplifier. The proposed SK-LCT technique is applied in both SRAM cell and sense amplifier for a new low power high speed SRAM architecture design. The outline of SRAM architecture utilizing pass transistor decoder (PT-Decoder) gives better outcomes in term of power. Simulation is done using Tanner EDA tool in 180nm technology and the results demonstrate a noteworthy change in leakage power utilization and speed.

Design and investigation of variability aware sense amplifier for low power, high speed SRAM

Reducing the input referred offset voltage of a sense amplifier (SA) provides remarkable returns in terms of reliability and energy conservation in static random access memory (SRAMs), which consume dominating portion of total power in modern ICs. High-reliability-applications benefit significantly from a low offset SA which can operate at high speed. However, low offset SAs tend to have significant overheads in terms of area, speed and complexity. In this paper we introduce a high speed SA that employs a self correction scheme to greatly minimize its input referred offset. Minimal calibrating circuitry limits the area and energy overheads. Sensing and failure mechanisms have been described for the first time in terms of resistance states of critical paths in SA, to provide a new and more basic dimension in the analysis of the offset problem. We implemented a CMOS logic- compatible, 4 Kb SRAM macro, in commercial UMC 65nm, using the proposed SA namely, self correcting sense amplifier (SCSA). Performance analysis reveals a 60% reduction in standard deviation of input referred offset in SCSA compared to conventional current latch sense amplifier (CLSA). Compared to another modern low offset alternative, SCSA have a 78% lower sensing delay and 19% lower active power consumption resulting in 82% reduction in the power delay product.

High-speed reduced-leakage SRAM memory cell design techniques for low-power 65 nm FD-SOI/SON CMOS technology

The paper presents a detailed study on the sub-1V high speed operation with reduced leakage design techniques for conventional 6T Static Random Access Memory (SRAM) on fully depleted Silicon-on Insulator (FD-SOI) and fully depleted Silicon-on-Nothing (FD-SON) technology. Performance of SON MOSFET is found to be significantly better both in terms of power and speed from its equivalent SOI device. Future devices with advanced technology are promising for low-power application. The most promising high-speed, low-power operation techniques are introduced, analyzed and compared into 65nm low-power FD-SOI/SON technology. Hspice simulations conclude Drive Source Line (DSL) architecture as the best option for high speed operation in sub 100nm technology without affecting the Static Noise Margin (SNM) of the cells.

A Novel Low-Power and High-Speed SOI SRAM With Actively Body-Bias Controlled (ABC) Technology for Emerging Generations

An actively body-bias controlled (ABC) silicon-on-insulator (SOI) static random access memory (SRAM) connecting the bodies of the access and the driver transistors with the word line is proposed to realize high-speed and low-voltage operation. We developed the direct body contact to apply forward biases to the bodies without increases in the area penalty and the parasitic gate capacitance. An increase of the standby current does not occur because the body biases are not applied when the word-line voltage is low level. It is demonstrated that a significant speed improvement and a reduction of performance variations for the SRAM are achieved by applying the body bias. Neutron-accelerated soft-error tests reveal that the ABC structure suppresses soft-error events due to the body-tied SOI structure. In summary, the ABC SOI technology is one of the countermeasures for emerging generations.

New Current-Mirror Sense Amplifier Design for High-Speed SRAM Applications

This study presents a new current-mirror sense amplifier (CMSA) design for high-speed static random access memory (SRAM) applications. The proposed CMSA can directly sense the current of memory cell and only needs two transistor stages cascaded from VDD to GND for achieving the low-voltage operation. Moreover, the sensing speed of the proposed CMSA is independent of the bit-line capacitances and is only slightly sensitive to the data-line capacitances. Based on the simulation with using the TSMC 0.25-μm 2P4M CMOS process parameter, the proposed CMSA can effectively work at 500 MHz--1 GHz with working voltage as low as 1.5 V. Simulated results show that the proposed CMSA has a much speed improvement compared with the conventional sense amplifiers. Also, the effectiveness of the proposed CMSA is demonstrated with a read-cycle-only memory system to show the good performance for SRAM applications.

Fast detection of data retention faults and other SRAM cell open defects

Detection of open defects in static random access memory (SRAM) cells, including those causing data retention faults (DRFs), is known to be difficult and time consuming. This paper proposes a novel design-for-test (DFT) technique that allows SRAMs to be tested at full speed for these defects. As a result, it achieves not only significant test time reduction but also full coverage of open defects, including those undetectable to previous solutions. The proposed technique is referred to as predischarge write test mode (PDWTM). Implementation of the proposed technique requires little design effort and imposes negligible hardware and performance penalties. Furthermore, the proposed technique can be easily merged with any March algorithm, thus resulting in full DRF and other SRAM cell open defect coverage. The proposed technique has been validated by SPICE simulation using both low-power and high-speed SRAM cells.

An Analysis of Size Effect on the Performances of Low-Leakage 0.10 µm Complementary Metal Oxide Semiconductor for 5-GHz Band Low-Power RF-ICs and Static Random Access Memory Applications

In this paper, we demonstrate the size effect on the DC and RF performances of 0.10 µm RF metal–oxide–semiconductor field effect transistors (MOSFETs) for 5-GHz band low-power radio-frequency integrated circuits (RF-ICs) and high-speed static random access memory (SRAM) applications. It was found that either one of the increase of device's width, the increase of gate-source voltage (when its corresponding transconductance (gm) is smaller than the maximum gm), and the decrease of measurement temperature can enhance the kink effect of both scattering parameters S11 and S22 because of the increase of gm. A device with larger gate-width exhibits better RF noise and power performances because of higher gain and the lighter effect of parasitic extrinsic elements. In addition, the directly extracted equivalent Pucel's noise parameters P, R, and C of the MOSFETs can be used to calculate the noise figures of LNA's/mixers and the phase noise of oscillators, and thus is very helpful in the design of RF circuits.

A 4-ns 4K*1-bit two-port BiCMOS SRAM

The authors introduce a two-port BiCMOS static random-access memory (SRAM) cell that combines ECL-level word-line voltage swings and emitter-follower bit-line coupling with a static CMOS latch for data storage. With this cell, referred to as a CMOS storage emitter access cell, it is possible to achieve access times comparable to those of high-speed bipolar SRAMs while preserving the high density and low power of CMOS memory arrays. The memory can be read and written simultaneously and is therefore well-suited to applications such as high-speed caches and video memories. A read access time of 3.8 ns at a power dissipation of 520 mW has been achieved in an experimental 4K*1-bit two-port memory integrated in a 1.5- mu m 5-GHz BiCMOS technology. The access time in this prototype design is nearly temperature-insensitive, increasing to only 4 ns at a case temperature of 100 degrees C. >