High-speed Processing Research Articles

Graphene-enhanced polarization-insensitive all-optical wavelength conversion based on four-wave mixing.

All-optical wavelength conversion technology based on four-wave mixing (FWM) effect is a promising development need of the modern high-speed optical signal processing system. In this work, we report on the polarization insensitive four-wave mixing based on graphene for all optical wavelength conversion. To overcome the polarization sensitivity of FWM, a dual-pump configuration was proposed based on the combination of graphene and the optical fibers. Our experimental results illustrate that by using the dual pump configuration, the FWM-based wavelength conversion efficiency, can be enhanced by graphene with about 8 dB when the state of polarization of the two pumps are parallel. This proposed all-optical wavelength converter based on graphene may provide a new approach for the next generation optical communications and signal processing.

Performance Optimization of CNC Machine Tool System Based on Sensor Data

CNC machine tools have been popularized in the development of the manufacturing industry because of their high precision, high speed, high efficiency, and safe and reliable processing. The numerical control system and the measurement system of the machine tool are the key components of the modern numerical control machine tool, especially the measurement system of the machine tool, which is a prerequisite to ensure the high precision of the machine tool. The sensor is an important part of the measurement system. Sensors are devices that can sense the measurement objects within the measurement range and convert them into output signals and information according to certain rules. They are mainly used to detect the operating objects, system status, and operating environment status of the machine tool system and effectively control the normal operation of the machine tool system. Accurate and reliable information is provided. This study takes the CNC machine tool control system as the research object and studies the optimization measures of the sensor data to its performance. First, a model of the CNC machine tool control system was built based on MATLAB/Simulink, and then, based on this model, an open-loop (without sensor) and closed-loop (with speed and position sensors) control systems were built and were finally verified by simulation. The research results show that when there are sensors, the CNC machine tool control system has better stability and robustness.

FPGA-based methods for high-speed processing of video images with large brightness scatter

FPGA-based methods for high-speed processing of video images with large brightness scatter

NAND and NOR logic-in-memory comprising silicon nanowire feedback field-effect transistors

The processing of large amounts of data requires a high energy efficiency and fast processing time for high-performance computing systems. However, conventional von Neumann computing systems have performance limitations because of bottlenecks in data movement between separated processing and memory hierarchy, which causes latency and high power consumption. To overcome this hindrance, logic-in-memory (LIM) has been proposed that performs both data processing and memory operations. Here, we present a NAND and NOR LIM composed of silicon nanowire feedback field-effect transistors, whose configuration resembles that of CMOS logic gate circuits. The LIM can perform memory operations to retain its output logic under zero-bias conditions as well as logic operations with a high processing speed of nanoseconds. The newly proposed dynamic voltage-transfer characteristics verify the operating principle of the LIM. This study demonstrates that the NAND and NOR LIM has promising potential to resolve power and processing speed issues.

WCQMV : Design of A Wavelet Compression Based Quadratic Model for EEG Classification Using Multivariate Analysis

Electroencephalogram (EEG) signals represent functioning of the brain, and assist in identification of multiple brain-related disorders including Epilepsy, Alzheimer’s disease, emotional states, Parkinson’s disease, strokes, etc. To design such models, a wide variety of machine learning & deep learning approaches are proposed by researchers. But these approaches use a black-box generic model for EEG classification, due to which their scalability is limited. To enhance this scalability, a novel feature augmented extraction model is proposed in this text. The model uses wavelet compression on input EEG data, and processes the compressed signal using a variance-based selection approach. Due to which, the model is capable of low-delay, and high accuracy classification for different brain-diseases. It evaluates wavelet-based features from input EEG data, and performs ensemble feature selection for improving feature variance. The wavelet features are able to convert input EEG data into different directional components, which assists in improving efficiency of feature representation & model training for different signal types. The proposed model uses a quadratic Neural Network (QNN) classification engine, and is capable of achieving an accuracy of 96.5% for different EEG classes. These classes include 3 types of Epilepsy, presence of Alzheimer’s disease, & evaluation of brain strokes. Due to use of feature variance-based classification, the proposed WCQMV model outperforms existing feature selection & classification models by 4% in terms of accuracy when averaged over multiple datasets. Moreover, the proposed model also improves speed of classification by 4.9% when compared with these models, thus making it useful for high-speed EEG processing applications. This performance improvement is possible due to effective feature reduction, which assists in identification of different EEG signal types. The model was tested on various EEG datasets including, IEEE Port Epileptic dataset, and BNCI dataset for Alzheimer & brain strokes. It was observed that the proposed model was capable of high-performance classification on each dataset, thereby indicating high-scalability across multiple EEG applications.

Laser techniques for dissimilar joining of aluminum alloys to steels: A critical review

The use of multi-materials structures is nowadays one of the most sought solutions to decrease weight and reduce both emission of greenhouse gases and fuel consumption in the automotive industry. Dissimilar joining of aluminum (Al) alloys to steels by fusion-based welding technologies is often difficult to achieve as a result of the significant mismatch in these materials’ physical and chemical properties. Moreover, when mixed in the liquid state, hard and brittle intermetallic compounds are easily formed. Due to characteristics that include high processing speed, flexibility and energy density, multiple attempts have been made to join Al to steel using laser-based processes. This thorough review article provides a comprehensive and exhausting analysis of the recent achievements and progress on joining of Al alloys to steel by various laser-based joining processes, including laser keyhole welding, laser welding-brazing, laser-arc welding, laser-assisted friction stir welding, laser roll pressure welding and joining based on laser additive manufacturing. This paper also evaluates the joining conditions, filler materials, phase constitution, microstructure, mechanical properties and joining mechanisms associated to each process. Furthermore, special emphasis is given to factors affecting the joint strength such as welding defects, joint geometry, intermetallic compounds formation and interfacial strength. The review is then concluded with an outlook providing the summary and future trends of this field.

A High-Speed NMS Coprocessor for Lightweight Ship Detection Algorithm

With the development of artificial intelligence research, the convolutional neural networks (CNN) triumphantly continue to conquer diverse visual tasks, with lots of technical and practical problems emerging. When the detection networks need to meet the high-speed processing requirement and the low power consumption constraint in edge computing, dedicated circuits and algorithm optimization are necessary. In this brief, we propose a non-maximum suppression (NMS) coprocessor that cooperated with a Vision Processor (VP) to speed up the detection. It contains a parallel process unit and dynamic memory management to accelerate NMS processing. Meanwhile, the software workflow provides a comprehensive method to convert the one-stage detection network to our processor in a post-training manner. The experimental results show that our co-design solution reaches 166 FPS to run a MobileNet-SSD, promising to deploy in edge-computing scenarios. Moreover, the detection accuracy on the Airbus dataset is 88.6%, favorable in practical applications.

A novel robust reset controller implemented through field programmable gate array for oxygen ratio regulation of proton exchange membrane fuel cell

This paper considers the nonlinear proton exchange membrane fuel cell model to precisely describe the system dynamics and presents a robust reset control method for regulating oxygen rate and optimizing the operation of the fuel cell system during fast load variations. The proposed reset law eliminates overshoot, shortens settling time, and thus improves the behavior of the closed-loop system, while achieving these goals is impossible by any linear controller. Due to the ability of field programmable gate array (FPGA) in providing high speed and efficient processing through software as well as near-real-time performance verification, the proposed control method is implemented through FPGA to confirm operational capability and high speed flexibility of controller. The results of the implementation of the proposed method and comparison with the hybrid fuzzy proportional integral derivative method exhibit smooth dynamic response, error reduction in terms of various criteria and better capability in tracking the desired oxygen rate despite the drastic changes in load current.

Design of high‐speed software defined radar with GPU accelerator

Software defined radar (SDRadar) systems have become an important area for future radar development and are based on similar concepts to Software defined radio (SDR). Most of the processing like filtering, frequency conversion and signal generation are implemented in software. Currently, radar systems tend to have complex signal processing and operate at wider bandwidth, which means that limits on the available computational power must be considered when designing a SDRadar system. This paper presents a feasible solution to this potential limitation by accelerating the signal processing using a GPU to enable the development of a high speed SDRadar system. The developed system overcomes the limitation on the processing speed by CPU-only, and has been tested on three different SDR devices. Results show that, with GPU accelerator, the processing rate can achieve up to 80 MHz compared to 20 MHz with the CPU-only. The high speed processing makes it possible to run in real-time and process full bandwidth across the WiFi signal acquired by multiple channels. The gains made through porting the processing to the GPU moves the technology towards real-world application in various scenarios ranging from healthcare to IoT, and other applications that required significant computational processing.

DYNAMIC PROCESSES ANALYSIS IN HIGH-SPEED SPINDLE ASSEMBLIES OF MACHINES TOOL WITH ACCOUNT DIFFERENT TYPES NONLINEARITY

The productivity and accuracy machine parts often depend on the dynamic processes during machine and cutting operation. The increase requirements for machining operation and quality machine parts leads to the need to evaluate and take into account all the capabilities of the technological processing system (TS) to ensure the stability of the cutting process and increase speed. One of the features emergence and existence of self-oscillating processes, the least studied and dangerous in terms of the effect on sustainability ТS is the nonlinearity parameters elastic system of the machine tool and the processes occurring during cutting operation. Therefore, to assess the conditions for implementation of the cutting process with a steady limited amplitude of oscillations, it is necessary to analyze and take into account the main nonlinearities dynamics of the TS. The article considers dynamic processes in high-speed processing systems on the example of high-precision spindle assemblies, with analysis and following review of their different types nonlinearity. The machine tool spindle unit for the case of high-speed processing according to the working conditions approaches the scheme of the rotor system which self-oscillations can be caused by the action of non-conservative circulation-type forces that are not associated with external periodic loads or any resonant relationships: internal friction forces, hydrodynamic forces in sliding bearings and seals, electrodynamic and electromagnetic forces in the electrical components of motor-spindles. It is shown that if the nonlinearity is associated only with internal external friction and coefficients of friction forces do not depend on frequency, the amplitude and frequency of self-oscillations (unlike linear system) will depend only on relationship of friction forces.

Compact electro-optic modulator on lithium niobate

Fast electro-optic modulators with an ultracompact footprint and low power consumption are always highly desired for optical interconnects. Here we propose and demonstrate a high-performance lithium niobate electro-optic modulator based on a new 2 × 2 Fabry–Perot cavity. In this structure, the input and reflected beams are separated by introducing asymmetric multimode-waveguide gratings, enabling TE 0 − TE 1 mode conversion. The measured results indicate that the fabricated modulator features a low excess loss of ∼ 0.9 dB , a high extinction ratio of ∼ 21 dB , a compact footprint of ∼ 2120 μm 2 , and high modulation speeds of 40 Gbps OOK and 80 Gbps PAM4 signals. The demonstrated modulator is promising for high-speed data transmission and signal processing.

Deep Neural Network Based Reconciliation for CV-QKD

High-speed reconciliation is indispensable for supporting the continuous-variable quantum key distribution (CV-QKD) system to generate the secure key in real-time. However, the error correction process’s high complexity and low processing speed limit the reconciliation speed. Therefore, reconciliation has also become the bottleneck of system performance. In this paper, we proposed a high-speed reconciliation scheme that uses the deep neural network to optimize the decoding process of the low-density parity-check (LDPC) code. We first introduced a network structure of decoding implementation based on the deep neural network, which can be applied to decoding algorithms of parallel strategy and significantly reduce the decoding complexity. Subsequently, we proposed two improved decoding algorithms based on this structure, named linear fitting algorithm and deep neural network-assisted decoding algorithm. Finally, we introduced a high-speed reconciliation scheme based on the CPU-GPU hybrid platform. Simulation results show that the proposed reconciliation scheme reduces the complexity and enables us to realize the high-speed CV-QKD system. Furthermore, the improved decoding algorithm can also reduce the FER, thereby increasing the secret key rate.

Hosting Capacity Calculation Deploying a Hybrid Methodology: A Case Study Concerning the Intermittent Nature of Photovoltaic Distributed Generation and the Variable Nature of Energy Consumption in a Medium Voltage Distribution Network

The main methods employed for Hosting Capacity (HC) calculations are basically classified into deterministic, stochastic and time series. In this scenario, the authors herein propose a hybrid methodology, which shows efficiency and ease of implementation. Besides the method presented, it is also calculated a hosting capacity of a real feeder which was modeled and analyzed taking into consideration variations in load and power injected by distributed generation sources. The proposed hybrid method deploys just one time series with the feeder power demand data, which are easily obtained from the feeder’s origin substation. Low voltage loads were modeled by the ratio between their maximum demands and the feeder maximum demand, making easier to start up the grid model implementation. Hence, the advantages of the proposed methodology can be summarized in: (a) easy to obtain the input parameters; (b) agility in implementing the study; (c) higher processing speed and (d) results consistent with the time series method. Finally, in view of the advantages and obtained results, the proposed hybrid methodology shows itself as a promising and attractive tool for the studies of hosting capacity by the utilities.

A Heterogeneous Architecture for the Vision Processing Unit with a Hybrid Deep Neural Network Accelerator.

The vision chip is widely used to acquire and process images. It connects the image sensor directly with the vision processing unit (VPU) to execute the vision tasks. Modern vision tasks mainly consist of image signal processing (ISP) algorithms and deep neural networks (DNNs). However, the traditional VPUs are unsuitable for the DNNs, and the DNN processing units (DNPUs) cannot process the ISP algorithms. Meanwhile, only the CNNs and the CNN-RNN frameworks are used in the vision tasks, and few DNPUs are specifically designed for this. In this paper, we propose a heterogeneous architecture for the VPU with a hybrid accelerator for the DNNs. It can process the ISP, CNNs, and hybrid DNN subtasks on one unit. Furthermore, we present a sharing scheme to multiplex the hardware resources for different subtasks. We also adopt a pipelined workflow for the vision tasks to fully use the different processing modules and achieve a high processing speed. We implement the proposed VPU on the field-programmable gate array (FPGA), and several vision tasks are tested on it. The experiment results show that our design can process the vision tasks efficiently with an average performance of 22.6 giga operations per second/W (GOPS/W).

Image encryption using spatial nonlinear optics

Optical technologies have been widely used in information security owing to its parallel and high-speed processing capability. However, the most critical problem with current optical encryption techniques is that the cyphertext is linearly related with the plaintext, leading to the possibility that one can crack the system by solving a set of linear equations with only two cyphertext from the same encryption machine. Many efforts have been taken in the last decade to resolve the linearity issue, but none of these offers a true nonlinear solution. Inspired by the recent advance in spatial nonlinear optics, here we demonstrate a true nonlinear optical encryption technique. We show that, owing to the self-phase modulation effect of the photorefractive crystal, the proposed nonlinear optical image encryption technique is robust against the known plaintext attack based on phase retrieval. This opens up a new avenue for optical encryption in the spatial nonlinear domain.

Design and characteristic analysis of an all-optical AND, XOR, and XNOR Y-shaped MIM waveguide for high-speed information processing.

All-optical logic gates are exceptionally suited for Boolean ultrahigh-speed operation and logical computing. This study presents a plasmonic model that uses a Y-shaped metal-insulator-metal waveguide structure that realizes the ultrafast all-optical AND, XOR, and XNOR gate operation that is developed at a footprint of 6.6µm×3.4µm with a wavelength of 1.55 µm. This construction relies on the notion of linear interference. The insertion loss and extinction ratio of the model are observed as 1.49 dB and 21.49 dB for AND, 1.03 dB and 18.97 dB for XOR, and 2.06 dB, and 10.92 dB for XNOR, respectively. The transmission efficiency, response time, and speed of the structure also are calculated and are used to improve the performance of any complex circuit in the future. The theoretical analysis of the proposed structure is carried out using the finite-difference time-domain method.

A high speed processor for elliptic curve cryptography over NIST prime field

Elliptic curve cryptography (ECC), as one of the public key cryptography systems, has been widely applied to many security applications. It is challenging to implement a scalar multiplication (SM) operation which has the highest computational complexity in ECC. In this study, we propose a hardware processor which achieves high speed and high security for ECC. We first present a three-clock cycle, divide-and-conquer multiplication algorithm which greatly reduces the number of execution cycles of multiplication. We then propose a dedicated multiplication hardware structure which reuses the multiplier and optimizes data path delay. To keep multiplication running in non-idle status and executing in parallel with other modular operations, the operation scheduling of point addition and point doubling has been re-designed and optimized based on an effective segmentation and pipeline strategy. Finally, under the premise of similar computing and hardware overhead, we propose an improved high-security SM algorithm which involves random points to resist side-channel attacks. On a 55 nm complementary metal oxide semiconductor application specific integrated circuit platform, the processor costs 463k gates and requires 0.028 ms for one SM. Our results indicate that the ECC processor is superior to other state-of-the-art designs reported in the literature in terms of speed and area-time product metrics.

Design and implementation of a nano magnetic logic barrel shifter using beyond-CMOS technology

Abstract Bit manipulation plays a significant role in high-speed digital signal processing (DSP) and data computing systems, and shift and rotation operations are crucial functions in it. In general, barrel shifters are used to perform these operations effectively. Nano magnetic logic circuits are among the promising beyond-CMOS alternative technologies for the design of high-speed circuits. Most of the existing circuits that have been developed using nano magnets are combinational circuits. In this work, a barrel shifter is implemented and realised using in-plane nano magnetic logic. The proposed design is the first of its kind nano magnetic logic circuit. The nano magnetic logic circuit implementation, layout generation, simulation, and validation were performed using the ToPoliNano and ModelSim tools. The logical equivalent design was synthesised and evaluated using the Synopsys Design Compiler tool. The proposed barrel shifter was realised using majority logic has 1769037 nano magnets with a boxing area of 481 × 13104 µm2 and 3276 clock zones after optimisation with the Barycenter algorithm. The proposed barrel shifter realised using Boolean logic has 315276 nano magnets with a boxing area of 265 × 5028 µm2 and 1257 clock zones after optimisation with the Barycenter algorithm. The proposed design results demonstrate that complex systems can be developed using nano magnetic logic by combining combinational and sequential circuits.

Design of FPGA-Based SHE and SPWM Digital Switching Controllers for 21-Level Cascaded H-Bridge Multilevel Inverter Model.

Multilevel inverters are a type of power electronic circuit that converts direct current (DC) to alternating current (AC) for use in high-voltage and high-power applications. Many recent studies on multilevel inverters have used field-programmable gate arrays (FPGAs) as a switching controller device to overcome the limitations of microcontrollers or DSPs, such as limited sampling rate, low execution speed, and a limited number of IO pins. However, the design techniques of most existing FPGA-based switching controllers require large amounts of memory (RAM) for storage of sampled data points as well as complex controller architectures to generate the output gating pulses. Therefore, in this paper, we propose two types of FPGA-based digital switching controllers, namely selective harmonic elimination (SHE) and sinusoidal pulse width modulation (SPWM), for a 21-level multilevel inverter. Both switching controllers were designed with minimal hardware complexity and logic utilisation. The designed SHE switching controller mainly consists of a four-bit finite state machine (FSM) and a 13-bit counter, while the SPWM switching controller employs a simple iterative CORDIC algorithm with a small amount of data storage requirement, a six-bit up-down counter, and a few adders. Initially, both digital switching controllers (SHE and SPWM) were designed using the hardware description language (HDL) in Verilog codes and functionally verified using the developed testbenches. The designed digital switching controllers were then synthesised and downloaded to the Intel FPGA (DE2-115) board for real-time verification purposes. For system-level verification, both switching controllers were tested on five cascaded H-Bridge circuits for a 21-level multilevel inverter model using the HDL co-simulation method in MATLAB Simulink. From the synthesised logic gates, it was found that the designed SHE and SPWM switching controllers require only 186 and 369 logic elements (LEs), respectively, which is less than 1% of the total LEs in an FPGA (Cyclone IV E) chip. The execution speed of the SHE switching controller implemented in the FPGA (Cyclone IV E) chip was found to be a maximum of 99.97% faster when compared with the microcontroller (PIC16F877A). The THD percentage of the 21-level SHE digital switching controller (3.91%) was found to be 37% less than that of the SPWM digital switching controller (6.17%). In conclusion, the proposed simplified design architectures of SHE and SPWM digital switching controllers have been proven to not only require minimal logic resources, achieve high processing speeds, and function correctly when tested on a real-time FPGA board, but also generate the desired 21-level stepped sine-wave output voltage (±360 VPP) at a frequency of 50 Hz with low THD percentages when tested on a 21-level cascaded H-Bridge multilevel inverter model.

Time-delayed reservoir computing based on an optically pumped spin VCSEL for high-speed processing

Time-delayed reservoir computing based on an optically pumped spin VCSEL for high-speed processing