High-speed Parallel Processing Research Articles

Realization of quantum dot Boolean logic gate for image processing applications

A two-dimensional (2D) periodic array of gallium ars- enide GaAs quantum dots, embedded on the surface of a GaAs resonant tunneling diode (RTD), is investigated as a system for im- age processing. The embedded dot structures have been developed as a high-speed parallel processing device. The image processing task by QDs can be done through the realization of QD Boolean logic gates. It is shown that if the image data are introduced as initial conditions to these QD logic gates, the response of the system re- alizes a morphological image processing task similar to image dila- tion and erosion. © 2007 SPIE and IS&T. DOI: 10.1117/1.2723770

CFD/CSD 통합 연계기법을 이용한 횡방향 곡률이 있는 날개의 가상 플러터 시험

The coupled time-integration method with a staggered algorithm based on computational structural dynamics (CSD), finite element method (FEM) and computational fluid dynamics (CFD) has been developed in order to demonstrate physical vibration phenomena due to dynamic aeroelastic excitations. Virtual flutter tests for the spanwise curved ing model have been effectively conducted using the present advanced computational method with high speed parallel processing technique. In addition, the present system can simultaneously give a recorded data file to generate virtual animation for the flutter safety test. The results for virtual flutter test are compared with the experimental data of wind tunnel test. It is shown from the results that the effect of spanwise curvature have a tendency to decrease the flutter dynamic pressure for the same flight condition.

Nonlinear Aeroelastic Computation of a Wing/Pylon/Finned-Store Using Parallel Computing

Nonlinear aeroelastic computations are presented for a sweptback wing with underpylon/finned-store in the transonic and supersonic flow regions, where strong shock wave interactions exist. A modal-based coupled nonlinear aeroelastic analysis system with the matched-point concept has been developed using the high-speed parallel processing technique. Advanced numerical techniques such as computational structural dynamics and computational fluid dynamics are used. It is expected to provide accurate and useful engineering data in the aeroelastic and structural design of flight vehicles. For the nonlinear unsteady aerodynamics in high transonic flow region, Euler equations based on an unstructured grid system have been applied to consider fully the complex geometries. Linear and nonlinear aeroelastic computations have been conducted and are compared for the transonic and supersonic flow regions. Typically, it is shown that the advanced numerical approach gives much more conservative flutter boundary for the wing/pylon/store model than those predicted by the classical linear aerodynamic theories for high transonic flow. Also, important results indicate that in transonic flow the critical nonlinear flutter or limit-cycle oscillation-like phenomenon may be dominantly induced or within the bounds of strong possibility due to the shock coupling effect of unstable store induced vibration.

Virtual Flutter Plight Test of a Full Configuration Aircraft with Pylon/External Stores

An advanced aeroelastic analysis using a computational structural dynamics (CSD), finite element method (FEM) and computational fluid dynamics (CFD) is presented in this Paper. A general aeroelastic analysis system is originally developed and applied to realistic design problems in the transonic flow region, where strong shock wave interactions exist. The present computational approach is based on the modal-based coupled nonlinear analysis with the matched-point concept and adopts the high-speed parallel processing technique on the low-cost network based PC-clustered machines. It can give very accurate and useful engineering data on the structural dynamic design of advanced flight vehicles. For the nonlinear unsteady aerodynamics in high transonic flow region, Euler equations using the unstructured grid system have been applied to easily consider complex configurations. It is typically shown that the advanced numerical approach can give very realistic and practical results for design engineers and safe flight tests. One can find that the present study conducts a virtual flutter flight test which are usually very dangerous in reality.

고속 병렬처리 기법을 이용한 전기체 항공기 형상의 천음속/초음속 비선형 공탄성 해석

A nonlinear aeroelastic analysis system in transonic and supersonic flows has been developed using high speed parallel processing technique on the network based PC-clustered machines. This paper includes the coupling of advanced numerical techniques such as computational structural dynamics (CSD), finite element method (FEM) and computational fluid dynamics (CFD). The unsteady Euler solver on dynamic unstructured meshes is employed and coupled with computational aeroelastic solvers. Thus it can give very accurate engineering data in the structural and aeroelastic design of flight vehicles. To show the great potential of useful application, transonic and supersonic flutter analyses have been conducted for a complete aircraft model under developing in Korea.

Development of Under-sodium Three-dimensional Visual Inspection Technique Using Matrix-arrayed Ultrasonic Transducer

We have developed an advanced under-sodium ultrasonic visual inspection technique in order to observe in-vessel structures in a Fast Breeder Reactor (FBR) whose reactor vessel is filled with opaque liquid sodium. The final goal of this work is achievement of resolution equivalent to that of an image obtained by optical fiber scope. The under-sodium ultrasonic visualizing system consists of a matrix-arrayed transducer and a signal- processing device. The matrix-arrayed transducer, in which 36x36 piezoelectric elements are arranged with 5 mm interval and sealed by a thin metal diaphragm, can realize a 3-dimensional image with high resolution. Regarding signal processing, the 3-dimensional image synthetic processing and the cross correlation processing for the purpose of improving S/N ratio of ultrasonic echoes are implemented on a high-speed parallel processor. Under-sodium imaging test was carried out, and it was confirmed that a 3-dimensional image of the blind target, which was prepared without information beforehand, could be visualized clearly with less than 2.0 mm resolution under-sodium.

Ultra High-Speed Digital Feed-Back Control System

This paper proposes a method of ultra high-speed digital measurement and feedback control for treatment of the phenomenon that is moving or changing at near velocity of light. This method contains several important technologies for real-time processing and operations, those of high-speed random access control for memory system, high-speed parallel processing, high-speed input / output with high stability, means for keeping accuracy of the absolute time for control-interval and input/output timing, and so on. As one of the applications of ultra high-speed digital feed-back system, we tried to apply our method to the feed-back control system to control many bunches with large amount of electrons and positrons turning at near velocity of light in the inside of a colliding type accelerator consisting of two rings, one for electrons and one for positrons, crossing each other, and attempted a development of prototype system for said application and several kind of experiments to evaluate its performances. From results of the attempts, a prospect of realizing the application and a recognition of availabilities of our method have been obtained.

High resolution X-ray imaging using a silicon strip detector

The authors present the first images and an initial evaluation of a scanned-slot X-ray imaging system based on edge-on silicon strip detectors and high-speed low-noise parallel processing ASICs. The authors have demonstrated noiseless single photon counting above a minimal threshold of 7.2 keV. Edge scans show negligible cross talk between different channels in the ASIC. The Modulation Transfer Function (MTF) has been measured and found to agree with the ideal MTF for 100 /spl mu/m pixel size. The first images are obtained at very low exposures and show the high performance of the system. The authors also present a way of enhancing the X-ray flux to a slot by using a refractive X-ray lens. They believe this focusing device will significantly enhance the potential for scanned-slot X-ray imaging.

Optical matrix for clock distribution and synchronous operation in two-dimensional array devices

A scheme to generate an optical matrix from a mode-locked Nd:YAG laser has been theoretically explored and experimentally demonstrated. The matrix consists of highly synchronized and sequentially delayed optical pulses suitable for use with two-dimensional array optoelectronic devices and clock distribution system. The output pulses have the same state of polarization and no timing jitter is produced among the elements. Encoded outputs have been generated from the matrix using a set of photomasks. This technique can be applied to high-speed optical parallel processing.

Integrated Image Associative Memory and Its Optical Implementation

We present the concept of integrated processing to combine intuitive processing of neural networks with logical processing of the conventional digital computer. We investigate a way to embody the concept in the neural network system by introducing external constraints in terms of external input. The effect of the external input is analyzed using the generalized projection method. The concept of integrated processing is applied to an image associative memory system, and the system is optically implemented for high-speed parallel processing incorporating it with the computer. The experimental result is presented to illustrate the effectiveness of the external input to control the output of the image associative memory.

Deep-submicron HEMT technology

Abstract The current status of HEMT technology and its impact on computers and communications are presented, focusing on the advantages of the device in the deep-submicrometre dimensional range, self-aligned HEMT processing, and the HEMT LSI implemented in supercomputer and communication systems. Ultra-low-noise HEMTs are already commercially available in satellite communications, and have made a great impact in expanding the broadcasting satellite market. For ultra-high-speed digital LSI applications the 1 k gate bus-driver logic LSI has been developed to demonstrate high-speed data transfer in a high-speed parallel processing supercomputer system at room temperature, operating at 10·92 Gflops. The 7 k gate asynchronous transfer mode (ATM) switch LSI has alsi been developed to evaluate high-speed data switching for Broadband Integrated Service Digital Network (B-ISDN). The maximum operation frequency was 1·2 GHz at room temperature. The single-chip throughput was 9·6 Gb/s and a throughput of 38·4 Gb/s was achieved in a 4 × 4 ATM switching module.

Three-dimensional Omega networks for optical implementation

We discuss a class of volume three-dimensional multistage interconnection networks suitable for optical implementation. The networks are based on perfect shuffles defined on two-dimensional arrays of signal channels combined with various types of dynamic switch elements in two-dimensional arrays. A mathematical description of the two-dimensional shuffles and these switch elements is presented. The relationship between the networks in this class (three-dimensional Omega networks) is studied. Optical or optoelectronic versions of these networks can perform high-speed parallel signal processing operations.

An 8-b slice GaAs bus logic LSI for a high-speed parallel processing system

An 8-b slice GaAs bus logic LSI (BL) has been developed for a high-speed interconnection network in a multiple-instruction multiple-data stream (MIMD) parallel processing system. The BL has been designed using a novel standard-cell approach called the building-cell methodology, which leads to a high integrated density of 25000 devices in a 7*7-mm/sup 2/ chip. The BL consists of 3376 logic gates and a 76-b dual-port register file (RF), which has as a new function a multi-address read/write operation for efficient data transfer. The BL was fabricated by a 0.8- mu m WN/sub x/ gate LDD (lightly doped drain) MESFET process, and fully functionally tested with an average yield of 20%. A 10-ns cycle time operation was achieved with a power dissipation of 5.5 W. This result reveals that a network with 256 GaAs BLs and 64 processor units can realize a maximum data transfer rate of 2.56 Gbyte/s. >

Ultrahigh-speed HEMT LSI technology for supercomputer

The current status of high electron mobility transistor (HEMT) technology at Fujitsu for high-performance VLSI is presented, focusing on device performance in the submicrometer dimensional range and the HEMT LSIs implemented in supercomputer systems. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. A 1.1 K-gate bus-driver logic LSI has been developed to demonstrate the high-speed data transfer in a high-speed parallel processing system at room temperature, operating at 10.92 GFLOPS. A cryogenic 3.3 K-gate random number generator logic LSI with maximum clock frequency of 1.6 GHz has also been developed to demonstrate the high-clock-rate system operations at liquid-nitrogen temperature. For VLSI level complexity, a HEMT 64-kb static RAM with 1.2-ns access operation and a 45 K-gate gate array with 35-ps logic delay have been developed operating at room temperature, demonstrating the high performance required for future high-speed computer systems.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Parallel Processing for Real-Time Dynamic System Simulation

A parallel processing algorithm based on the recursive dynamics formulation presented in a companion paper [1] is developed for multiprocessor implementation. Lagrange multipliers associated with cut-joint constraints for closed loop systems are eliminated, resulting in a minimal set of equations of motion. Concurrent generation of the system inertia matrix and the generalized force vector using the algorithm of Ref. 1 is shown to yield finer grain parallelism than earlier recursive algorithms. A new computational structure for dynamic analysis is proposed for high speed parallel processing. Real-time simulation of a vehicle is demonstrated on an eight processor parallel computer to illustrate efficiency and effectiveness of the algorithm, even for interactive operator-in-the-loop simulation.

2-D systolic arrays for realization of 2-D convolution

An image is regarded as a 2-D array of pixels and is processed by a 2-D array architecture. The image can be acquired in the usual manner by a raster scan method which produces a 1-D array of pixels at real-time video rates. Two 2-D systolic arrays for a 2-D convolver are presented. They have an architecture which accepts this 1-D array of pixels and processes them in a 2-D array of simple processors. This high degree of parallelism is achieved through matrix-vector formulations of 2-D convolution. One array has a serial input, a serial output, and uses a minimum number of multipliers: the other array has parallel input, parallel output, and is suitable for high-speed processing using slow processing elements. Both arrays are modular with nearest-neighbor communications are are suitable for VLSI implementation. In addition, an algorithm for 2-D convolution that explicitly takes into account the boundary conditions is presented. This feature allows a large image to be partitioned so that each partition may be processed by independent 2-D convolvers. It is then possible to process only a specified section of the image or carry out high-speed parallel processing using as many 2-D convolvers as are available.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Ultrashort light pulses

A tutorial review of the field of ultrashort-pulse generation and use is presented. A brief description of laser operation is followed by a discussion of how short pulses are created. The three techniques examined-active mode locking, passive mode locking, and passive mode locking with pulse compression-produce successively shorter pulses. The potential application of ultrashort pulses to high-speed signal processing and parallel processing is considered.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 9-kbit associative memory for high-speed parallel processing applications

The authors discuss the design, development and implementation of the 9-kb (256-word*37-bit) associative memory used in the single-chip array processing element (SCAPE) chip, a CMOS VLSI associative parallel processor (APP) that integrates 256 associative processing elements (APEs) on a single 68-pad chip to achieve high-speed, cost-effective image and signal processing. It is shown that a static CMOS content-addressable memory (CAM) design is unsuited to the constraints of the SCAPE chip architecture and that a purely nMOS CAM cell provides the best compromise between the conflicting area, speed, power, and control requirements. Comprehensive details of this design are given together with an evaluation of its performance. Finally, a description of the design methodology used in the construction of the SCAPE chip is presented with a breakdown of circuit areas and operational data.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

PDOC - a database on paralel processing literature

A systematic and economic development of the large-scale computing environment at research centers has to be accompanied by some services providing a survey on the relevant literature. This paper deals with the imbedding of a database on 'High Speed Computing and Parallel Processing' literature into the computing environment at KFA J&amp;uuml;lich.

Analysis of a model for parallel image processing

An increasing awareness of the need for high speed parallel processing systems for image analysis has stimulated a great deal of interest in the design and development of such systems. Efficient processing schemes for several specific problems have been developed providing some insight into the general problems encountered in designing efficient image processing algorithms for parallel architectures. However it is still not clear what architecture or architectures are best suited for image processing in general, or how one may go about determining those which are. An approach that would allow application requirements to specify architectural features would be useful in this context. Working towards this goal, general principles are outlined for formulating parallel image processing tasks by exploiting parallelism in the algorithms and data structures employed. A synchronous parallel processing model is proposed which governs the communication and interaction between these tasks. This model presents a uniform framework for comparing and contrasting different formulation strategies. In addition, techniques are developed for analyzing instances of this model to determine a high level specification of a parallel architecture that best ‘matches’ the requirements of the corresponding application. It is also possible to derive initial estimates of the component capabilities that are required to achieve predefined performance levels. Such analysis tools are useful both in the design stage, in the selection of a specific parallel architecture, or in efficiently utilizing an existing one. In addition, the architecture independent specification of application requirements makes it a useful tool for benchmarking applications.